Patent Application
20080079735
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Portions and features of some embodiments may be included in, or substituted for, those of other embodiments. Embodiments of the invention set forth in the claims encompass all available equivalents of those claims. Embodiments of the invention may be referred to herein, individually or collectively, by the term “invention” merely for convenience and without intending to limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed.
In some embodiments, graphics controller 106 may be a graphics chip, a graphics processing unit (GPU), or a Graphics and Memory Controller Hub (GMCH), although the scope of the invention is not limited in this respect. In some embodiments, graphics controller 106 may include graphics processing circuitry 116 to perform various processing operations for graphics controller 106, and display engine 114 for providing frames of pixels over interface 112 for display panel 122. Graphics controller 106 may also include clock-generating circuitry (not separately illustrated) to generate and/or provide clock signals and/or other timing signals for use within graphics controller 106. In some embodiments, display engine 114 may provide frames of pixels in a pixel stream manner to display panel 122.
In some embodiments, processing system 102 may comprise a motherboard of a personal computer, such as a portable or laptop computer. In some embodiments, processing unit 104 may comprise a microprocessor or a central processing unit (CPU) for processing system 102, although the scope of the invention is not limited in this respect.
Memory 110 may comprise random access memory (RAM), such as dynamic random access memory (DRAM), although other types of memory such as magnetic RAM (MRAM) may be suitable. Memory 110 may include display memory 108, discussed in more detail below.
Display panel 122 may comprise display controller 124 to control the operations of display panel 122 and receive frames of pixels as well as control signals from processing system 102. Display panel 122 may also include display 134, which may be a liquid crystal display (LCD). Display 134 may have drivers, such as row drivers 130 and column drivers 132, for providing signals to drive and/or control the individual elements of display 134.
Display controller 124 may include display controller processing circuitry 125 to perform various processing operations for display controller 124, discussed in more detail below. Display controller 124 may also include lower-response-time compensation (LRTC) logic 126 to provide compensated pixel values that may compensate for a slower response time of the elements of display 134. Display controller 124 may also include look-up-table (LUT) 127, which may be used in generating the compensated pixel values. These embodiments are discussed in more detail below. In some embodiments, display controller 124 may comprise a timing control chip or a timing controller (TCON), which may coordinate the operations on display panel 122. Display controller 124 may also include other functional elements and circuitry not separately illustrated.
Processing unit 104, among other things, may process commands that may instruct graphics controller 106 to render a new image. Graphics controller 106 may generate the image in the form of pixels or pixel values, which may be provided to display controller 124 through interface 112. Display controller 124 may convert the pixel values provided by graphics controller 106 into driver signals suitable for column drivers 132 and may instruct row drivers 130 when to address a row of display 134. In some embodiments, row drivers 130 may comprise gate drivers. In some embodiments, applications, as well as other processes (e.g., mouse movement) running on processing system 102, may cause processing unit 104 to generate new and/or updated images.
In accordance with some embodiments, display controller processing circuitry 125 receives an interleaved pixel stream from graphics controller 106. The interleaved pixel stream may comprise pixels of a current frame interleaved with pixels of a prior frame. In these embodiments, display controller processing circuitry 125 selects low-response-time (LRT) compensation for each pixel of the current frame based on the values of pixels of the current frame and corresponding pixels of the prior frame. LRTC logic 126 may apply the LRT compensation to the pixels of the current frame to generate compensated pixel values 131 for column drivers 132 of display 134. Accordingly, LRT compensation may be performed by display panel 122 without the use of a frame buffer on display panel 122. In some embodiments, the interleaved pixel stream may comprise a pixel of the current frame followed by a corresponding pixel of the prior frame, although the scope of the invention is not limited in this respect as other types of pixel interleaving are suitable. In some embodiments, LUT 127 may store the LRT compensation values selected by LRTC logic 126. The selected LRT compensation values may reduce the occurrence of motion artifacts resulting from a slower response time of elements of display 134.
In some embodiments, the compensated pixel values may cause column drivers 132 to either overdrive or under-drive elements of display 134. The LRT compensation may be based on a response time of the display elements to achieve a desired luminance response.
In some embodiments, display controller processing circuitry 125 may apply gamma correction to pixels of the current frame prior to LRTC logic 126 applying the LRT compensation. In some alternate embodiments, display controller processing circuitry 125 may apply gamma correction to pixels of the current frame after LRTC logic 126 applies the LRT compensation, although the scope of the invention is not limited in this respect.
In some embodiments, display controller processing circuitry 125 may be responsive to a mode control signal provided by graphics controller 106 indicating whether an interleaved pixel stream or a non-interleaved pixel stream will be provided. In these embodiments, the non-interleaved pixel stream may comprise pixels of a current frame without pixels of a prior frame.
In some embodiments, the mode control signal may be an out-of-band signal provided, for example, during a vertical-blanking interval (VBI). In some other embodiments, the mode control signal may be an in-band signal, although the scope of the invention is not limited in this respect.
In some embodiments, when the mode control signal indicates that a non-interleaved pixel stream will be provided, display controller processing circuitry 125 either instructs LRTC logic 126 to refrain from applying LRT compensation to the pixel values of the current frame, or bypasses LRTC logic 126. Accordingly, when the image is static, no LRT compensation is required and graphics controller 106 may send only the pixels of the current frame. In some other embodiments, graphics controller 106 may send an interleaved pixel stream regardless of whether the image is static or moving.
In some embodiments, when the mode control signal indicates that a non-interleaved pixel stream will be provided, display controller 124 may receive frame data from graphics controller 106 at a frame-refresh pixel rate. When the mode control signal indicates that an interleaved pixel stream will be provided, display controller 124 may receive frame data from graphics controller 106 at twice the frame-refresh pixel rate, although the scope of the invention is not limited in this respect. In these embodiments, the frame-refresh rate may remain the same, but the amount of pixel data within each frame may double, resulting in twice the data rate (i.e., twice the frame-refresh pixel rate). In some embodiments, the data may be compressed to provide for a lower data rate.
In some embodiments, the response time of the elements of display 134 may range from 25 to 40 milliseconds (ms). In these embodiments, the rate at which display 134 is refreshed (i.e., frame-refresh pixel rate) may be about 60 Hertz, which is a 16.6 ms frame interval. Without LRT compensation, the difference between the frame-refresh pixel rate and the response time of the display elements may result in the presence of artifacts (e.g., blurring) on display 134.
In some embodiments, display controller 124 may refrain from buffering pixels of a prior frame, whether the pixels of the prior frame are received as part of the interleaved pixel stream, or whether the pixels of the prior frame were the current pixels of last frame. In this way, display panel 122 does not need a frame buffer to store pixels of the prior frame to provide LRT compensation.
In these embodiments, a register may be used to hold a number of pixels depending on the interleaving. For example, when the pixels of the current frame are interleaved on a pixel-by-pixel basis with pixels of a prior frame, the register may hold a single pixel. In other embodiments, when more than one pixel of the current frame is provided and interleaved with other pixels on a group-by-group basis (e.g., group interleaving) or a line-by-line basis (e.g., line interleaving), the register may hold a group or a line of pixels of the prior frame.
In some embodiments, display engine 114 may provide a non-interleaved pixel stream to display controller 124 in idle mode when pixel values do not change between the current frame and a predetermined number of prior frames. In these embodiments, display engine 114 may provide an interleaved pixel stream to display controller 124 in non-idle mode when one or more pixel values change between the current frame and the prior frame. In some embodiments, graphics controller 106 may instruct display controller 124 to remain in non-idle mode during video playback operations.
In accordance with some embodiments, graphics processing circuitry 116 may generate the interleaved pixel stream and display engine 114 may provide the interleaved pixel stream to display controller 124. Display controller 124 may select LRT compensation for each pixel of the current frame based on the pixels of the current frame and corresponding pixels of the prior frame without the use of a frame buffer on display panel 122.
In some embodiments, graphics processing circuitry 116 generates a mode control signal for display controller 124, indicating that a non-interleaved pixel stream will be provided. In these embodiments, graphics processing circuitry 116 may generate the mode control signal when pixel values do not change between the current frame and a predetermined number of one or more prior frames. After providing the mode control signal to display controller 124, graphics processing circuitry 116 may generate a non-interleaved pixel stream for display controller 124. In response to receipt of the mode control signal, display controller 124 may refrain from selecting and applying LRT compensation to pixels of current frames.
In some embodiments, graphics processing circuitry 116 may generate a mode control signal for display controller 124, indicating that an interleaved pixel stream will be provided. In these embodiments, graphics processing circuitry 116 may generate the mode control signal when pixel values change between a current frame and a prior frame. After providing this mode control signal to display controller 124, graphics processing circuitry 116 may generate the interleaved pixel stream comprising pixels of a current frame with pixels of a prior frame. In response to receipt of this mode control signal, display controller 124 may apply LRT compensation to pixels of current frames.
In some embodiments, display engine 114 may provide the non-interleaved pixel stream a frame-refresh pixel rate, and may provide the interleaved pixel stream at twice the frame-refresh pixel rate (i.e., the same frame-refresh rate, but at twice the data rate), although the scope of the invention is not limited in this respect. In some embodiments, graphics processing circuitry 116 may store or buffer pixels of the prior frame in display memory 108. Graphics processing circuitry 116 may retrieve the stored pixels of the prior frame from display memory 108 for use in generating the interleaved pixel stream. In some embodiments, graphics processing circuitry 116 may compare pixels of a current frame with the buffered pixels of a prior frame to determine whether or not to provide a mode control signal.
Although processing system 102 and display panel 122 are illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements, such as processing elements including digital signal processors (DSPs), and/or other hardware elements. For example, some elements may comprise one or more microprocessors, DSPs, application specific integrated circuits (ASICs), and combinations of various hardware and logic circuitry for performing at least the functions described herein. In some embodiments, the functional elements of processing system 102 and display panel 122 may refer to one or more processes operating on one or more processing elements.
In operation 202, a pixel stream may be received from a graphics controller, such as graphics controller 106 (
In operation 204, the display controller continues to receive the pixel stream. When the pixel stream is interleaved, operations 206 through 210 are performed. When the pixel stream is non-interleaved, operations 212 and 214 are performed.
In some embodiments, as part of operation 204, a mode control signal may be received from the graphics controller, indicating whether an interleaved or non-interleaved pixel stream is going to be provided. When the mode control signal indicates that an interleaved pixel stream is going to be provided, operations 206 through 210 are performed. When the mode control signal indicates that a non-interleaved pixel stream is going to be provided, operations 212 and 214 are performed.
In operation 206, the processing circuitry of the display controller may select LRT compensation from a LUT, such as LUT 127.
In operation 208, the processing circuitry of the display controller may apply gamma correction to the pixels of the current frame.
In operation 210, the LRT compensation logic of the display controller may apply the LRT compensation that was selected in operation 206 to pixels of the current frame. In these embodiments, the gamma correction of operation 208 may be applied prior to applying the LRT compensation. In some other embodiments, gamma correction may be applied after LRT compensation, however different LRT compensation values would be used.
In operation 212, the processing circuitry of the display controller may apply gamma correction to the pixels of the current frame that were received as part of a non-interleaved pixel stream.
In operation 214, the processing circuitry of the display controller may instruct LRT compensation logic to refrain from performing LRT compensation on the pixels of the current frame. In some embodiments, the processing circuitry of the display controller may bypass the LRT compensation logic, although the scope of the invention is not limited in this respect.
In operation 216, the pixel values of the current frame are provided to the display drivers. The pixel values may have LRT compensation and/or gamma correction applied as discussed above.
In operation 218, operations 202 through 216 may be repeated for pixels of the next frame received from the graphics controller. Although procedure 200 may allow the display controller to switch between modes on a frame by frame basis, in some embodiments, the display controller may remain in LRT compensation mode for at least a predetermined number of frames or a predetermined time period.
Although the individual operations of procedure 200 are illustrated and described as separate operations, one or more of the individual operations may be performed concurrently, and nothing requires that the operations be performed in the order illustrated.
Wireless communication device 300 may be almost any portable wireless communication device, such as a personal digital assistant (PDA), a laptop or portable computer with wireless communication capability, a web tablet, a wireless telephone, a wireless headset, a pager, an instant messaging device, a digital camera, an access point, a television, a medical device (e.g., a heart rate monitor, a blood pressure monitor, etc.), or other device that may receive and/or transmit information wirelessly.
In some embodiments, transceiver 302 may communicate using orthogonal frequency division multiplexed (OFDM) communication signals over a multicarrier communication channel. In some embodiments, transceiver 302 may communicate using orthogonal frequency division multiple access (OFDMA) communication signals. In some embodiments, transceiver 302 may communicate using spread-spectrum signals, although the scope of the invention is not limited in this respect.
In some embodiments, wireless communication device 300 may be part of a communication station, such as wireless local area network (WLAN) communication station including a Wireless Fidelity (WiFi) communication station, an access point (AP) or a mobile station (MS). In some other embodiments, wireless communication device 300 may be part of a broadband wireless access (BWA) network communication station, such as a Worldwide Interoperability for Microwave Access (WiMax) communication station, although the scope of the invention is not limited in this respect as wireless communication device 300 may be part of almost any wireless communication device.
In some embodiments, the frequency spectrums for the communication signals transmitted and received by wireless communication device 300 may comprise frequencies between 2 and 11 GHz, although the scope of the invention is not limited in this respect.
Antenna 304 may comprise one or more directional or omnidirectional antennas, including, for example, dipole antennas, monopole antennas, patch antennas, loop antennas, microstrip antennas or other types of antennas suitable for transmission of RF signals. In some multiple-input, multiple-output (MIMO) embodiments, two or more antennas may be used.
Unless specifically stated otherwise, terms such as processing, computing, calculating, determining, displaying, or the like, may refer to an action and/or process of one or more processing or computing systems or similar devices that may manipulate and transform data represented as physical (e.g., electronic) quantities within a processing system's registers and memory into other data similarly represented as physical quantities within the processing system's registers or memories, or other such information storage, transmission or display devices. Furthermore, as used herein, a computing device includes one or more processing elements coupled with computer-readable memory that may be volatile or non-volatile memory or a combination thereof.
Some embodiments of the invention may be implemented in one or a combination of hardware, firmware and software. Some embodiments of the invention may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by at least one processor to perform the operations described herein. A machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable medium may include read-only memory (ROM), random-access memory (RAM), magnetic disk storage media, optical storage media, flash-memory devices, electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others.
In some embodiments, the present invention provides a method comprising generating an interleaved pixel stream comprising pixels of a current frame interleaved with pixels of a prior frame, and providing the interleaved pixel stream to display controller 124 (
Some embodiments of the present invention are directed to a portable computer system comprising graphics controller 106 to generate an interleaved pixel stream, and display controller 124 (
The Abstract is provided to comply with 37 C.F.R. Section 1.72(b) requiring an abstract that will allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims.
In the foregoing detailed description, various features are occasionally grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, invention may lie in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment.
