Claims
- 1. A graphic display system for transforming and displaying computer-generated images of a pre-determined number of dimensions, D, on a display device, the display system comprising:
- a digital interpolator for converting a computer instruction into digital clock pulses for driving the display device;
- a matrix multiplier coupled to said digital interpolator for receiving said digital clock pulses and altering the sequence thereof according to data stored in said matrix multiplier, said matrix multiplier including accumulators which are each divided into an integer part and a fractional part, said integer part accumulating m bits and said fractional part accumulating n bits and having a carry/borrow output;
- m-bit counters comprising said integer part and also comprising axis counters of the display system for counting said digital clock pulses; and
- digital-to-analog converters connected to receive the output of said m-bit counters for converting said output to analog signals for driving the display device.
- 2. The graphic display system of claim 1 wherein said matrix multiplier further comprises:
- D.sup.2 registers for storing the elements of a D by D matrix, said elements being constrained to between -1 and +1 and each one of said D.sup.2 registers is connected so as to store one of said elements;
- D.sup.2 multipliers, each one thereof coupled to a different one of said D.sup.2 registers, to receive one of said matrix elements therefrom and for multiplying said one of said matrix elements with said digital clock pulses;
- D.sup.2 accumulators, each one thereof connected to a different one of said D.sup.2 multipliers, for temporarily storing the output thereof; and
- D summing means, each one coupled to D of said D.sup.2 accumulators, for receiving and summing the output of said D accumulators.
- 3. The graphic display system of claim 2 wherein said matrix multiplier further comprises D multiplexers connected to the carry/borrow output of D of said fractional accumulators.
- 4. The graphic display system of claim 3 wherein the output of said D multiplexers is connected each one to a different one of said m-bit counters.
Parent Case Info
This is a continuation, of application Ser. No. 896,538 filed Apr. 14, 1978 and now abandoned.
US Referenced Citations (6)
Continuations (1)
|
Number |
Date |
Country |
Parent |
896538 |
Apr 1978 |
|