Claims
- 1. A process of moving an array of pixel data representing an image to be displayed from a source memory space to a destination memory space, said array of pixel data being arranged in words containing a plurality of individual pixel datum, said process comprising:
- a. reading the address of a word in said source memory space;
- b. fetching said word from said source memory space;
- c. transforming each pixel datum in said word fetched from said source memory space to a colorized pixel datum by individually attaching color information to each said pixel datum, said transforming occurring substantially in parallel on all of the pixel data in each word;
- d. reading the address of a word location in said destination memory space;
- e. writing said word of colorized pixel data to said address of said word location in said destination memory space; and
- f. repeating said steps a-e for each individual pixel datum of said array.
- 2. The process of claim 1 in which each pixel datum in said source memory space contains only one bit having one or another logical state, and said transforming includes changing said pixel datum from said source memory space to one of two plural bit color codes depending upon the logical state of said pixel datum from said source memory space.
- 3. The process of claim 1 including providing two separately accessible registers containing plural bit color codes, and said transforming including accessing one or the other of said registers depending upon the logical state of said pixel datum for substituting said contained plural bit color code for said pixel datum.
- 4. The process of claim 1 including fetching words of pixel data from said destination memory space, combining each of the respective pixel, datum in said words from said source and destination memory spaces and writing the resulting words of pixel data to said destination memory space.
- 5. The process of claim 1 including selecting the number of pixel datum in each word by placing an indicator in a pixel size register.
Parent Case Info
This is a continuation of application Ser. No. 07/506,506 filed on Apr. 6, 1990, now U.S. Pat. No. 5,085,301 which is a continuation of application Ser. No. 07/361,747, filed on Jun. 1, 1989, abandoned; which is a continuation of application Ser. No. 07/178,798 filed on Mar. 31, 1988, abandoned; which is a continuation of application Ser. No. 06/795,383 filed on Nov. 06, 1985, abandoned.
US Referenced Citations (9)
Non-Patent Literature Citations (4)
Entry |
Yonezawa et al., Electronic Design, "CRT chip controls bit-mapped graphics and alphanumerics", Jun. 14, 1984, pp. 247-252, 254 and 256. |
Guttag and Hayn, "Video Display Processor Simulates Three Dimensions", Electronics, Nov. 20, 1980, pp. 123-126. |
Guttage and Macourek, "Video Display Processor", IEEE Trans. on Consumer Electronics, Feb. 1981, vol. CE-27, pp. 27-34. |
"Hitachi HD63484 Microcomputer LSI Advanced CRT Controller", pp. A0, A12, A29, Bi, B63, B72, B118, B120-121, B140-158, and B171-172, Revision 2.0 Jul. 15, 1984. |
Continuations (4)
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Number |
Date |
Country |
Parent |
506506 |
Apr 1990 |
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Parent |
361747 |
Jun 1989 |
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Parent |
178798 |
Mar 1988 |
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Parent |
795383 |
Nov 1985 |
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