Claims
- 1. A graphics data processing apparatus comprising:
- first and second register memories, each of said first and second register memories for storing therein a data word specifying X and Y coordinates; and
- a central processing unit connected to said first and second register memories for receiving data processing instructions, said data processing instructions including a coordinate manipulation instruction, comprising:
- a first arithmetic logic unit for performing arithmetic and logic operations upon the X coordinates specified by said first and second register memories, responsive to said coordinate manipulation instruction; and
- a second arithmetic logic unit for performing arithmetic and logic operations upon the Y coordinates specified by said first and second register memories, responsive to said coordinate manipulation instruction.
- 2. A graphics data processing apparatus as claimed in claim 1, wherein:
- said data words stored in said first and second register memories are represented by N bits, the most significant N/2 bits specifying said Y coordinate and the least significant N/2 bits specifying said X coordinate.
- 3. A graphics data processing apparatus as claimed in claim 1, wherein:
- said coordinate manipulation instruction is an add instruction; and
- said first arithmetic logic unit adds the X coordinate specified by the data word stored in said first register memory to the X coordinate specified by the data word stored in said second register memory thereby generating a X sum, and said second arithmetic logic unit adds the Y coordinate specified by the data word stored in said first register memory to the Y coordinate specified by the data word stored in said second register memory thereby generating a Y sum, in response to said add instruction.
- 4. A graphics data processing apparatus as claimed in claim 3, wherein:
- said central processing unit stores, in said second register memory, a data word having an X coordinate equal to said X sum and a Y coordinate equal to said Y sum, further in response to said add instruction.
- 5. A graphics data processing apparatus as claimed in claim 1, wherein:
- said coordinate manipulation instruction is a subtract instruction; and
- said first arithmetic logic unit substracts the X coordinate specified by the data word stored in said first register memory from the X coordinate specified by the data word stored in said second register memory thereby generating a X difference, and said second arithmetic logic unit subtracts the Y coordinate specified by the data word stored in said first register memory from the Y coordinate specified by the data word stored in said second register memory thereby generating a Y difference, in response to said subtract instruction.
- 6. A graphics data processing apparatus as claimed in claim 5, wherein:
- said central processing unit stores, in said second register memory, a data word having an X coordinate equal to said X difference and a Y coordinate equal to said Y difference, further in response to said subtract instruction.
- 7. A graphics data processing apparatus as claimed in claim 1, further comprising:
- a status register for storing data indicative of the results of said data processing instructions;
- and wherein:
- said coordinate manipulation instruction is a compare instruction; and
- said first arithmetic logic unit compares the X coordinate specified by the data word stored in said first register memory with the X coordinate specified by the data word stored in said second register memory, said second arithmetic logic unit compares the Y coordinate specified by the data word stored in said first register memory to the Y coordinate specified by the data word stored in said second register memory and said central processing unit stores data in said status register dependent upon the results of said comparisons, in response to said compare instruction.
- 8. A graphics data processing apparatus as claimed in claim 7, wherein:
- said status register has first and second comparison bits; and
- said central processing unit sets said first compare bit if the X coordinate specified by the data word stored in said first register memory equals the X coordinate specified by the data word stored in said second register memory and clears said first compare bit otherwise, and sets said second compare bit if the Y coordinate specified by the data word stored in said first register memory equals the Y coordinate specified by the data word stored in said second register memory and clears said second compare bit otherwise.
- 9. A graphics data processing apparatus as claimed in claim 7, wherein:
- said status register has first and second comparison bits; and
- said central processing unit sets said first compare bit if the X coordinate specified by the data word stored in said first register memory is greater than the X coordinate specified by the data word stored in said second register memory and clears said first compare bit otherwise, and sets said second compare bit if the Y coordinate specified by the data word stored in said first register memory is greater than the Y coordinate specified by the data word stored in said second register memory and clears said second compare bit otherwise.
- 10. A graphics data processing apparatus as claimed in claim 7, wherein:
- said status register has first, second, third and fourth comparison bits; and
- said central processing unit sets said first compare bit if the X coordinate specified by the data word stored in said first register memory equals the X coordinate specified by the data word stored in said second register memory and clears said first compare bit otherwise, sets said second compare bit if the X coordinate specified by the data word stored in said first register memory is greater than the X coordinate specified by the data word stored in said second register memory and clears said second compare bit otherwise, sets said third compare bit if the Y coordinate specified by the data word stored in said first register memory equals the Y coordinate specified by the data word stored in said second register memory and clears said third compare bit otherwise, and sets said fourth compare bit if the Y coordinate specified by the data word stored in said first register memory is greater than the Y coordinate specified by the data word stored in said second register memory and clears said fourth compare bit otherwise.
- 11. A graphics data processing apparatus as claimed in claim 1, wherein:
- said coordinate manipulation instruction is a move Y coordinate instruction; and
- said central processing unit stores a data word in said second register memory having an X coordinate equal to said X coordinate specified by the data word stored in said second register memory and a Y coordinate equal to said Y coordinate specified by the data word stored in said first register memory in response to said move Y coordinate instruction.
- 12. A graphics data processing apparatus as claimed in claim 1, wherein:
- said is a move X coordinate instruction; and
- said central processing unit stores a data word in said second register memory having an X coordinate equal to said X coordinate specified by the data word stored in said first register memory and a Y coordinate equal to said Y coordinate specified by the data word stored in said second register memory in response to said move X coordinate instruction.
Parent Case Info
This application is a continuation of application Ser. No. 07/368,976, filed Jun. 20, 1989, now abandoned, which was a continuation of application of Ser. No. 07/180,651 filed Mar. 31, 1988, now abandoned which was a continuation of application Ser. No. 06/804,204, filed Dec. 3, 1985, now abandoned.
US Referenced Citations (8)
Non-Patent Literature Citations (2)
Entry |
Van Aken, "An Efficient Ellipse-Drawing Algorithm," Computer Graphics and Applications (IEEE, Sep., 1984) pp. 24-35. |
NEC Electronics U.S.A. Inc., 1982 Catalog, Microcomputer Division, pp. 515-536, .mu.PD7220/GDC Graphics Display Controller. |
Continuations (3)
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Number |
Date |
Country |
Parent |
368976 |
Jun 1989 |
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Parent |
180651 |
Mar 1988 |
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Parent |
804204 |
Dec 1985 |
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