Patent Grant
7911366
Voltage mode Gray code A/D converters, such as that of
Vout=abs[2(Vin−Vref)]
where
Prior to taking the absolute value, the sign of (Vin−Vref) is observed and determines the logic state, one or zero, of each respective bit. For the MSB (most significant bit) a positive polarity remainder equals a logic one, a negative remainder equals a logic zero. The converse is true for all successive lower order bits, positive remainder equals logic zero, and negative remainder equals one. Utilizing this rule, the output of the ADC is Gray code proportional to the analog input Vin.
The remainder is multiplied by 2 before the absolute value is taken and passed on to the next succeeding stage. This allows normalization of Vref to a constant single value for each stage and reduces the accuracy requirement of each succeeding stage by a factor of 2.
Unlike other types of A/D converters, the Gray code converter requires no clocking of each bit. Ideally, the input voltage propagates through the circuit and produces valid code after a delay time equal to the summation of delay times associated with each analog operator.
The Gray code is an un-weighted binary code that changes by only one bit for each incremental increase or decrease in LSB value. This characteristic contrasts sharply with straight binary where all bits may be changing for a one bit incremental change in value. For example, the code change for the half-full-scale major carry of an 8 bit code is 01111111 to 10000000. As a result, an ADC with intrinsic Gray code output is well suited to asynchronous strobing of the data output without being susceptible to large scale errors.
Most existing implementations of the aforementioned Gray code algorithm take on the form, in one way or another, of the block diagram in
One self-steering architecture, as proposed by F. D. Waldauer (U.S. Pat. No. 3,187,325), presents an ideal case for voltage steering but is not implementable in a practical sense due to a lack of isolation between stages and the resultant instabilities created by parasitic positive feedback loops.
The Waldauer architecture is based on a balanced differential, voltage routing topology. This disclosure describes a balanced differential current routing topology.
The Waldauer architecture has fundamental issues with operational amplifier stability in its implementation due to poor analog operator input-output isolation.
Iout=abs[2(Iin−Iref)]
Vin and Vref can be converted to currents via the V/I converters shown in
In one embodiment, a Gray-code current-mode analog to digital (ADC) converter uses a Gray code current-mode ADC building block 400. The Gray code current-mode ADC building block 400 can be used to produce a Gray code bit, Bn, and a current output, Iout, that is sent to a next Gray code ADC building block. The Gray code current-mode ADC building block 400 need not use a voltage comparator in a signal path of the current output.
The Gray code current-mode ADC building block can include an output current mirror 402. The output current mirror 402 can double a current input into the output current mirror 402.
A pair 408 of transistors, M1 and M2, can be used to send a current with a value |Isig−IREF| in a first path 404 if Isig>IREF and down a second path 406 if Isig<IREF.
In this example, transistor M1 blocks current flowing to the pair from the building block input and transistor M2 blocks current flowing away from the pair to the building block input.
The current output need not be clocked before flowing to the next Gray code ADC building block.
A polarity inverting current mirror 410 can be used to invert the polarity of one possible input to the output current mirror 402. In this way, the polarity of the current output of the Gray code current-mode ADC building block can be the same whether Vsig>Vref or Vsig<Vref.
In the example of
If Iin>Iref, the resulting remainder is routed to the source of transistor M2, producing a positive voltage at Vs relative to Vbias(+2.5V). This current is then routed through the 1× N-channel current mirror 410 and then through the 2× P-channel current mirror 402.
In this example, there is no comparator involvement in the remainder current steering. The current steering is an intrinsic part of the processor circuit topology. The comparator 412 acts merely as an observer in determining the state of the bit and its propagation delay does not contribute significantly to the total conversion time.
In this example, the voltage excursion at Vs can be at least VT-Nch+VT-Pch or approx. 1.2V for a typical 0.5 um CMOS process. This greatly simplifies the design of the comparator since it need not be a precision, low offset device with high gain. It simply has to detect an approx. 1.2V transition centered on +2.5V in this example.
This straightforward implementation of the Gray code algorithm, however, can have limitations in speed and accuracy.
In one embodiment, the relatively large voltage excursion at Vs (approx. 1.2V) can create a voltage compliance issue on the signal input current, Iin, the reference current Iref and the output current Iout. This affects the accuracy of the conversion.
The source impedance looking into Vs can be large (>15KΩ) when the remainder current is small, on the order of ½ LSB, as an example. A converter with 256 ua full scale has a ½ LSB value of 0.5 ua. This high resistance, combined with source and parasitic capacitances can create a time constant that becomes the first order limitation to converter speed.
The propagation delay through the analog Operator chain can be code dependent. If the remainder current at the Vs node is negative, the current routes through transistor M1 and one current mirror to Iout. If the remainder current is positive it is routed through transistor M2 and two current mirrors to Iout. Although the time difference for each stage can be small, on the order of <5 ns, the worst case delta delay can be as much as 40 ns for an 8 bit converter.
As shown in
The schematic in
Z(Vscl)=Z(Vsol)/(1+Avol)
where
Simulations have indicated that a factor of 50 to 100 reductions in Zs can be achieved.
Dealing with the issue of code dependent propagation delay, can be fixed with a change in both converter and analog Operator architecture as shown in
In one embodiment, two Gray code current-mode ADC building blocks are used to produce a single Gray code bit. In one example, a first path goes to the output current mirror, and wherein a second path goes to a second output current mirror.
The converter architecture shown in
The bit sensing comparators now have a balanced differential signal as input. This 2× increase in comparator overdrive can simplify comparator design.
This configuration offers the possibility for achieving maximum converter resolution and speed at reasonably low power dissipation with the Gray code algorithm, albeit at the expense of a significant increase in circuit complexity.
The foregoing description of preferred embodiments of the present invention has been provided for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications that are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3187325 | Waldhauer | Jun 1965 | A |
| 4667180 | Robinson | May 1987 | A |
| 4675651 | Marbot et al. | Jun 1987 | A |
| 4745395 | Robinson | May 1988 | A |
| 5283582 | Krenik | Feb 1994 | A |
| 5572153 | Vallancourt et al. | Nov 1996 | A |
| 6313780 | Hughes et al. | Nov 2001 | B1 |
| 6972706 | Snoeijs | Dec 2005 | B2 |
| 20070139241 | Hales et al. | Jun 2007 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20100066579 A1 | Mar 2010 | US |
