Patent Application
20100085289
This disclosure relates generally to information handling systems, and more particularly to information handling systems utilizing a field-sequential display.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements can vary between different applications, information handling systems can also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information can be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems can include a variety of hardware and software components that can be configured to process, store, and communicate information and can include one or more computer systems, data storage systems, and networking systems.
Many information handling systems, including desktop and notebook computers, utilize a field-sequential display (e.g., a field-sequential liquid crystal display (LCD)) whereby each image frame is separated into its color components, and each color component is separately displayed in sequence. To illustrate, for a Red-Green-Blue (RGB)-based image signal, only the red pixel components of a multiple-color image frame (i.e., the “red field”) are displayed, followed by the display of only the green pixel components of the image frame (i.e., the “green field”), and then only the blue pixel components of the image frame (i.e., the “blue field”) are displayed. The corresponding color backlight is generated for the separate display of each color field. While displaying only one color component of a multiple-color image frame at a time can achieve greater image quality, to achieve a virtual multiple-color frame rate of X, the single-color frame sequence must be driven at a rate of at least N*X, whereby N is the number of color components in the multiple-color image frame. To illustrate, it typically is necessary to drive the field-sequential display at 180 Hertz (Hz) or more to achieve a virtual frame rate of 60 Hz in a RGB-based display while avoiding visual artifacts such as flicker or jitter. The timing requirements of this increased effective frame rate often results in increased power consumption, thereby adversely effecting the power requirements of the system.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the drawings presented herein, in which:
The use of the same reference symbols in different drawings indicates similar or identical items.
The following description in combination with the Figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other teachings can certainly be utilized in this application. The teachings can also be utilized in other applications and with several different types of architectures such as distributed computing architectures, client/server architectures, or middleware server architectures and associated components.
For purposes of this disclosure, an information handling system can include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, an information handling system can be a personal computer (e.g., a desktop computer or a notebook computer), a PDA, a consumer electronic device, a network server or storage device, a switch router, wireless router, or other network communication device, or any other suitable device and can vary in size, shape, performance, functionality, and price. The information handling system can include memory, one or more processing resources such as a central processing unit (CPU) or hardware or software control logic. Additional components of the information handling system can include one or more storage devices, one or more communications ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The information handling system can also include one or more buses operable to transmit communications between the various hardware components.
In operation, the video source 102 generates multiple-color image data 120 representative of color image content to be displayed at the field-sequential display 106. In at least one embodiment, the multiple-color image data 120 is composed of different color intensity values (e.g., red, green, and blue intensity values), whereby the color intensity values may be provided together for each image frame (e.g., each pixel of the image frame is represented by a RGB intensity tuple) or the multiple-color image data 120 can be arranged such that each color component of an image frame is sent separately as a group (e.g., all of the red intensity values for an image frame are provided, then the blue intensity values, etc.).
The timing controller 112 includes an input to receive the multiple-color image data 120, an input to receive a mode control signal 122 indicating whether the display controller 104 is to operate in a normal mode (e.g., color mode) or a low-power mode (e.g., grayscale mode), and an output to provide image data 124 to the field-sequential display 106. The field-sequential display 106 controls the transparency of the elements of the transistor matrix of the LCD 108 based on the image data 124.
In one embodiment, the timing controller 112 configures the color format and the frame rate timing of the image data 124 based on the particular mode indicated by the mode control signal 122. Responsive to the mode control signal 122 indicating operation in the normal mode, the timing controller 112 uses the multiple-color image data 120 from the video source 102 to generate the image data 124 as multiple-color image data having the same frame rate and thereby driving the field-sequential display 106 in a conventional color sequential mode. Responsive to the mode control signal 122 indicating operation in the low-power mode, the timing controller 112 converts the multiple-color image data 120 to generate the image data 124 as grayscale image data having a lower frame rate timing. The timing controller 112 then drives the field-sequential display 106 using the grayscale image data. By driving the grayscale image data at a lower frame rate timing, reduction in the power requirements of the display system 100 can be achieved in the low-power mode.
With sufficient ambient light and an effective reflective film, the conversion and display of the multiple-color image data as grayscale image data typically provides sufficient grayscale contrast without requiring backlighting. Accordingly, in one embodiment, the timing controller 112 can control the backlight 110 via a backlight control signal 126 so as to enable the backlight 110 during the normal mode and to disable the backlight 110 during the low-power mode, thereby further reducing power consumption during the low-power mode. The backlight control signal 126 can enable or disable the backlight 110 by, for example, enabling or disabling a voltage input to the backlight 110, by directing a pulse width modulation (PWM) controller to provide a particular duty cycle signal to the backlight 110, or the like.
In one embodiment, the video source 102 or other component of the information handling system signals the particular mode of operation to the timing controller 112. To illustrate, notebook computers often use timers to identify when a certain minimum inactive period has occurred and, in response, place the system in a sleep or low-power mode. A signal from the video source or from the chipset of the system that is representative of whether the notebook computer is in a full-power or low-power mode therefore can serve as the mode control signal 122. Alternately, the display controller 104 can utilize the ambient light sensor 116 and the backlight controller 114 to control the mode of operation, to control the backlight 110, or a combination thereof. It will be appreciated that as the ambient light incident on the display surface increases, the effectiveness of the backlight 110 decreases. Accordingly, in one embodiment, the backlight controller 114 uses the output of the ambient light sensor 116 to determine whether the ambient light has exceeded a predetermined threshold, and if so, the backlight controller 114 can signal the timing controller 112 to disable the backlight 110, enter the low-power mode, or both.
In the event that the display controller 104 is to operate in the normal mode, at block 206 the timing controller 112 uses the backlight control signal 126 to enable the backlight 110 of the field-sequential display 106 if not already enabled. At block 208, the timing controller 112 receives the multiple-color image data 120 from the video source 208 and at block 210 the timing controller 112 drives the field-sequential display 110 using the multiple-color image data 120 so as to generate multiple-color image content at the field-sequential display 106.
In the event that the display controller 104 is to operate in the low-power mode, at block 212 the backlight controller determines whether a backlight condition is met so as to trigger the disabling of the backlight 110. If the backlight condition is met, at block 214 the timing controller 112 disables the backlight 110 or otherwise reduces the backlighting intensity. In one embodiment, the backlight condition is met when the display controller 104 receives an indication from the video source 102 that the backlight 110 is to be disabled. To illustrate, the video source 102 communicates with the display controller 104 using, for example, the High Definition Multimedia Interface (HDMI) standard, and whereby the video source 102 can use the Display Data Channel (DDC) of the HDMI communication link to provide a backlight enable/disable indicator to the display controller 104. In another embodiment, because backlighting becomes less effective at higher ambient light intensities (which also reduces image contrast in multiple-color images), the ambient light intensity is used to control the backlight 110. In this instance, the backlight controller 114 uses the signal from the ambient light sensor 116 to determine the ambient light intensity and compares this determined intensity with a predetermined threshold intensity. In the event that the ambient light intensity exceeds this threshold, the backlight controller 114 signals the timing controller 112 to disable the backlight 110. Otherwise, the threshold is not exceeded, the backlight controller 114 signals the timing controller 112 to permit the backlight 110 to remain enabled, or to use another criterion in determining whether to disable the backlight 110.
Also while in the low-power mode, at block 216 the display controller 104 receives the multiple-color image data 120 from the video source 102. However, rather than driving the field-sequential display 106 with the multiple-color image data 120, the timing controller 112 instead generates grayscale image data based on the multiple-color image data 120 at block 218. As described in greater detail with reference to
The conversion means 300 includes an input 302 to receive a pixel component P(X) comprising three color-specific components for red, blue and green (identified as color components PR(X), PB(X), and PG(X), respectively). The conversion means 300 further includes multipliers 306, 307, 308 (implemented as hardware-based multipliers or a multiplication software routine), and summer 310 (implemented as a hardware-based summer or a summation software routine). The multiplier 306 includes an input to receive the color component PR(X), an input to receive a weighting factor WR, and an output to provide a modified color component P′R(X) resulting from a multiplication of the value of the color component PR(X) and the weighting factor WR. Likewise, the multiplier 307 includes an input to receive the color component PG(X), an input to receive a weighting factor WG, and an output to provide a modified color component P′G(X), and the multiplier 308 includes an input to receive the color component PB(X), an input to receive a weighting factor WB, and an output to provide a modified color component P′B(X). The summer 310 includes an input to receive the modified color component P′R(X), an input to receive the modified color component P′G(X), and an input to receive the modified color component P′B(X). The summer 310 is configured to generate the modified pixel component P′(X) as a sum of the modified color components P′R(X), P′G(X), and P′B(X). Thus, the operation of the grayscale generation means 300 can be summarized in the equation:
P′(X)=PR(X)*WR+PG(X)*WG+PB(X)*WB
The particular values of the weighting factors WR, WG, and WB can be programmable or hardcoded and can be determined through empirical analysis. To illustrate, application of the equation above to weighting factors 0.3, 0.59, and 0.11 for red, blue and green, respectively, and an 18 bit RGB color pixel of {1C, 0A, 29} (in hexadecimal) would result in a 6 bit grayscale value of {13} (in hexadecimal) (1C*0.3+0A*0.59+29*0.11).
According to one aspect, the chipset 410 can be referred to as a memory hub or a memory controller. For example, the chipset 410 can include an Accelerated Hub Architecture (AHA) that uses a dedicated bus to transfer data between first physical processor 402 and the nth physical processor 406. For example, the chipset 410, including an AHA enabled-chipset, can include a memory controller hub and an input/output (I/O) controller hub. As a memory controller hub, the chipset 410 can function to provide access to first physical processor 402 using first bus 404 and nth physical processor 406 using the second host bus 408. The chipset 410 can also provide a memory interface for accessing memory 412 using a memory bus 414. In a particular embodiment, the buses 404, 408, and 414 can be individual buses or part of the same bus. The chipset 410 can also provide bus control and can handle transfers between the buses 404, 408, and 414.
According to another aspect, the chipset 410 can be generally considered an application specific chipset that provides connectivity to various buses, and integrates other system functions. For example, the chipset 410 can be provided using an Intel® Hub Architecture (IHA) chipset that can also include two parts, a Graphics and AGP Memory Controller Hub (GMCH) and an I/O Controller Hub (ICH). For example, an Intel 820E, an 815E chipset, or any combination thereof, available from the Intel Corporation of Santa Clara, Calif., can provide at least a portion of the chipset 410. The chipset 410 can also be packaged as an application specific integrated circuit (ASIC).
The information handling system 400 can also include a video graphics interface 422 that can be coupled to the chipset 410 using a third host bus 424. In one form, the video graphics interface 422 can be an Accelerated Graphics Port (AGP) interface to display content within a video display unit 426. Other graphics interfaces may also be used. The video graphics interface 422 can provide a video display output 428 to the video display unit 426. The video display unit 426 can include one or more types of video displays such as a flat panel display (FPD) or other type of display device.
The information handling system 400 can also include an I/O interface 430 that can be connected via an I/O bus 420 to the chipset 410. The I/O interface 430 and I/O bus 420 can include industry standard buses or proprietary buses and respective interfaces or controllers. For example, the I/O bus 420 can also include a Peripheral Component Interconnect (PCI) bus or a high speed PCI-Express bus. In one embodiment, a PCI bus can be operated at approximately 46 MHz and a PCI-Express bus can be operated at approximately 428 MHz. PCI buses and PCI-Express buses can be provided to comply with industry standards for connecting and communicating between various PCI-enabled hardware devices. Other buses can also be provided in association with, or independent of, the I/O bus 420 including, but not limited to, industry standard buses or proprietary buses, such as Industry Standard Architecture (ISA), Small Computer Serial Interface (SCSI), Inter-Integrated Circuit (I2C), System Packet Interface (SPI), or Universal Serial buses (USBs).
In an alternate embodiment, the chipset 410 can be a chipset employing a Northbridge/Southbridge chipset configuration (not illustrated). For example, a Northbridge portion of the chipset 410 can communicate with the first physical processor 402 and can control interaction with the memory 412, the I/O bus 420 that can be operable as a PCI bus, and activities for the video graphics interface 422. The Northbridge portion can also communicate with the first physical processor 402 using first bus 404 and the second bus 408 coupled to the nth physical processor 406. The chipset 410 can also include a Southbridge portion (not illustrated) of the chipset 410 and can handle I/O functions of the chipset 410. The Southbridge portion can manage the basic forms of I/O such as Universal Serial Bus (USB), serial I/O, audio outputs, Integrated Drive Electronics (IDE), and ISA I/O for the information handling system 400.
Although only a few exemplary embodiments have been described in detail above, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the embodiments of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the embodiments of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.
