Patent Application
20250078762
The present disclosure relates to the technical field of displaying, and particularly relates to a grid-driving-circuit array and a display panel.
Currently, the pixel densities (Pixels Per Inch, PPI) of display panels are increasingly higher, and required grid driving circuits are increasingly more accordingly. Therefore, the room on the display panels for the fabrication of the grid driving circuits decreases.
Taking 3D displaying as an example, in 3D displaying, the existing displaying pixel groups are divided into a plurality of pixel units, and the pixel units display object information from different angles in cooperation with microlenses, to realize 3D displaying. If the quantity of the pixel units is higher, the effect of the 3D displaying is better. However, if the quantity of the pixel units is higher, it means that the resolution is higher. The super-high PPI increases the row quantity of the grid driving circuits, which means that the room for each of the rows decreases. Therefore, it is required to design a grid driving circuit to be used for higher-PPI display panels.
The present disclosure aims at solving at least one of the technical problems in the prior art, to provide a grid-driving-circuit array and a display panel.
In the first aspect, an embodiment of the present disclosure provides a grid-driving-circuit array, wherein the grid-driving-circuit array is applied to a display panel, the display panel is delimited into a plurality of active areas, and each of the active areas includes multiple rows of pixel units and multiple rows of grid lines; and
Optionally, each of the groups of grid driving units includes two grid driving circuits, and the two grid driving circuits include a first grid driving circuit and a second grid driving circuit, respectively;
Optionally, each of the frame-starting-up-signal outputting units in the multiplexer includes signal gating transistors and subregion gating transistors;
Optionally, if a plurality of multiplexers are provided, for the frame-starting-up-signal outputting units in each multiplexer that supply the frame starting-up signals to the same grid driving unit, control electrodes of the subregion gating transistors therein are connected to a same second gating signal line.
Optionally, the grid-driving-circuit array further includes a substrate, and the multiplexers and the reference-voltage signal lines connected thereto, the first gating signal lines and the driving-voltage signal lines which are connected to the multiplexers are provided on the substrate;
Optionally, the subregion gating transistors and the signal gating transistors in each of
Optionally, the subregion gating transistors in each of the frame-starting-up-signal outputting units are arranged sequentially side by side in the row direction; and
Optionally, a reference-voltage-signal switching line and a first gating-signal switching line are provided on the substrate;
Optionally, the substrate further includes a first conductive layer, an inter-layer insulating layer and a second conductive layer that are sequentially arranged in a direction away from the substrate;
Optionally, the first conductive layer further includes second gating-signal switching terminals, and the second gating-signal switching terminals are configured for connecting the control electrodes of the subregion gating transistors to the independent second gating-signal switching terminals, respectively.
Optionally, the second conductive layer further includes frame-starting-up-signal switching lines;
Optionally, each of the grid driving circuits includes shift registers that are cascaded;
Optionally, the controlling unit includes a first transistor and a second transistor;
Optionally, the initializing unit includes a third transistor, a control electrode of the third transistor is connected to an initializing-signal terminal, a first electrode is connected to the first node, and a second electrode is connected to a common-voltage terminal.
Optionally, the feedback unit includes a fourth transistor and a fifth transistor, a first electrode and a control electrode of the fourth transistor are connected to a second clock-signal terminal, and a second electrode of the fourth transistor is connected to the second node and a first electrode of the fifth transistor; and
Optionally, the voltage regulating unit includes a first-node discharging unit and a second-node discharging unit:
Optionally, the first-node discharging unit includes a sixth transistor, a control electrode of the sixth transistor is connected to the second node, the second electrode of the fourth transistor and the first electrode of the fifth transistor; a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to a common-voltage terminal; and
Optionally, the cascading unit includes an eighth transistor and a ninth transistor;
Optionally, the outputting unit includes a tenth transistor, an eleventh transistor and a first storage capacitor;
Optionally, the shift register further includes a correcting unit;
Optionally, the shift register further includes a storing unit:
Optionally, the voltage regulating unit further includes an auxiliary second-node discharging unit;
Optionally, the first clock-signal terminal and the second clock-signal terminal are the same, and are the same signal terminal.
Optionally, the cascading-signal terminal of the shift register of the present stage is connected to a resetting-signal terminal of the shift register of a preceding stage and a frame-starting-up-signal terminal of the shift register of a subsequent stage.
In the second aspect, an embodiment of the present disclosure further provides a display panel, wherein the display panel includes the grid-driving-circuit array according to any one of the above embodiments.
Optionally, the display panel is delimited into a pixel region and a non-pixel region; and
Optionally, the non-pixel region includes a fanning-out trace region located on one side of the pixel region, and the multiplexers are located within the fanning-out trace region.
to the present disclosure.
In order to enable a person skilled in the art to comprehend the technical solutions of the present disclosure better, the present disclosure will be further described in detail below with reference to the drawings and the particular embodiments.
Unless defined otherwise, the technical terminologies or scientific terminologies used in the present disclosure should have the meanings generally understood by a person skilled in the art of the present disclosure. The words used herein such as “first” and “second” do not indicate any sequence, quantity or priority, but are merely intended to distinguish different. components. Likewise, the words such as “a”, “an” or “the” do not indicate quantitative limitations, but indicate the existence of at least one instance. The words such as “comprise” or “include” mean that the element or article preceding the word encompasses the elements or articles and the equivalents thereof that are listed subsequent to the word, but do not exclude other elements or articles. The words such as “connect” or “couple” are not limited to physical or mechanical connections, but may include electric connections, regardless of direct connections or indirect connections. The words such as “upper”, “lower”, “left” and “right” are merely intended to indicate relative positions, and if the absolute position of the described item has changed, the relative positions might also be correspondingly changed.
The transistors used in the embodiments of the present disclosure may be thin-film transistors, field-effect transistors or the same devices of other characteristics. Because the source and the drain of the used transistors are symmetrical, their source and drain have no difference. In the embodiments of the present disclosure and the description below, in order to distinguish the source and the drain of the transistors, one of them is referred to as the first electrode, the other is referred to as the second electrode, and the grid is referred to as the control electrode. Moreover, according to the characteristics of the transistors, the transistors may be classified into N type and P type. When a P-type transistor is used, the first electrode is the source of the P-type transistor, the second electrode is the drain of the P-type transistor, and when the grid is inputted a low-level signal, the source and the drain are switched on. When an N-type transistor is used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when the grid is inputted a high-level signal, the source and the drain are switched on. The embodiments of the present disclosure and the description below illustrate by taking the case as an example for the description in which the transistors in the pixel circuit are N-type transistors.
Currently, the pixel densities (Pixels Per Inch, PPI) of display panels are increasingly higher, and increasingly more grid driving circuits are required accordingly. Therefore, the room on the display panels for the fabrication of the grid driving circuits decreases. The present disclosure, in view of the above problem, provides a high-PPI display panel with a grid-driving-circuit array, to solve the problem of insufficient room for the fabrication of the grid driving circuits caused by the increased row quantity of the pixel units.
Particularly, the grid of the data writing transistor M1 is connected to the grid-driving-signal terminal G1, the source is connected to a data-signal terminal Data, and the drain is connected to a node G. The grid of the resetting transistor M2 is connected to a second scanning-signal terminal G2, the source is connected to a resetting-signal terminal Vref, and the drain is connected to the grid of the driving transistor M5. The grid of the initializing transistor M3 is connected to a third scanning-signal terminal G3, the source is connected to an initializing-signal terminal Vini, the drain is connected to the source of the driving transistor M5 and the anode of a light emitting device D, and their connection is a connecting node S. The grid of the light-emission controlling transistor M4 is connected to a light-emission controlling-signal terminal EM, the source is connected to a first power-supply-voltage terminal ELVDD, the drain is connected to the source of the driving transistor M5, and their connection is a connecting node D. The grid of the driving transistor M5 is connected to the drain of the data writing transistor M1 and the drain of the resetting transistor M2, the source is connected to the drain of the light-emission controlling transistor M4, and the drain is connected to the anode of the light emitting device D. One terminal of the first capacitor Cst is connected to the grid of the driving transistor M5, and the other terminal is connected to the drain of the driving transistor M5. One terminal of the second capacitor Coled is connected to the anode of the light emitting device D, and the other terminal is connected to the cathode of the light emitting device D. The anode of the light emitting device D is connected to the drain of the driving transistor M5, and the cathode is connected to a second power-supply-voltage terminal ELVSS.
At the resetting stage S1, the control electrodes of the resetting transistor M2 and the initializing transistor M3 are connected to high levels, the resetting transistor M2 and the initializing transistor M3 are turned on, the control electrodes of the data writing transistor M1 and the light-emission controlling transistor M4 are connected to low levels, and the data writing transistor M1 and the light-emission controlling transistor M4 are turned off. At this point, the node G and the node S are reset, wherein the voltage of the node G is the input voltage of the resetting-signal terminal Vref, and the voltage of the node S is the input voltage of the initializing-signal terminal Vini.
At the compensation stage S2, the control electrodes of the data writing transistor M1 and the initializing transistor M3 are connected to low levels, the data writing transistor M1 and the initializing transistor M3 are turned off, the control electrodes of the resetting transistor M2 and the light-emission controlling transistor M4 are connected to high levels, and the resetting transistor M2 and the light-emission controlling transistor M4 are turned on. At this point, the voltage of the node S is compensated.
At the data-writing stage S3, the control electrode of the data writing transistor M1 is connected to a high level, the data writing transistor M1 is turned on, the control electrodes of the resetting transistor M2, the initializing transistor M3 and the light-emission controlling transistor M4 are connected to low levels, and the resetting transistor M2, the initializing transistor M3 and the light-emission controlling transistor M4 are turned off. The source of the data writing transistor M1 writes a data signal, wherein the data signal is a voltage signal, and is stored at the first capacitor Cst.
At the light-emission stage S4, the control electrode of the light-emission controlling transistor M4 is connected to a high level, the light-emission controlling transistor M1 is turned on, the control electrodes of the data writing transistor M1, the resetting transistor M2 and the initializing transistor M3 are connected to low levels, and the data writing transistor M1, the resetting transistor M2 and the initializing transistor M3 are turned off. The control electrode of the driving transistor M5 receives the data signal stored at the first capacitor Cst, and is turned on under the controlling by the data signal. At the light-emission stage S4, light regulation may be performed by pulse width modulation (PWM). In other words, the light-emission controlling signal of the light-emission controlling-signal terminal EM is a pulse signal, and the time when the light emitting device D emits light can be regulated by controlling the duty cycle of the light-emission controlling signal, thereby regulating the brightness of the light emitting device D.
It should be noted that, in an embodiment of the present disclosure, the pixel driving circuit may not only be the 5T2C (i.e., five transistors and two capacitors) structure shown in
It should be noted that the durations of the stages in the sequence diagram of the pixel driving circuit shown in
The display panel includes multiple rows of pixel units and multiple rows of grid lines. and each of the rows of grid lines supplies a grid driving signal to one of the rows of the pixel units. Each of the pixel units includes a light emitting device and a pixel driving circuit. Referring continuously to
In view of the above, the embodiments of the present disclosure provide a grid-driving-circuit array. The display panel is delimited into a plurality of active areas, and each of the active areas contains multiple rows of pixel units and multiple rows of grid lines. Each of the rows of grid lines supplies a grid driving signal to one of the rows of the pixel units. Each of the active areas corresponds to one of the grid driving units one to one, and each of the grid driving units includes one or more grid driving circuits. The grid-driving-circuit array further includes one or more multiplexers, wherein each of the multiplexers includes a plurality of frame-starting-up-signal outputting units, and each of the frame-starting-up-signal outputting units supplies a frame starting-up signal to one of the grid driving circuits of one of the grid driving units.
The grid-driving-circuit array according to the embodiments of the present disclosure will be described particularly below with reference to the particular embodiments and the drawings.
An embodiment of the present disclosure provides a grid-driving-circuit array.
In an embodiment of the present disclosure, the display panel is delimited into a plurality of active areas 1 by rows. When the display panel is a large-size display panel or a super-high-pixel-density display panel, the row quantity of its pixel units P is very high. Each of the grid driving circuits includes a plurality of shift registers 301 that are cascaded, and one of the shift registers 301 supplies a grid driving signal to one of the grid lines 4. When the row quantity of the pixel units P is excessively high, one grid driving circuit cannot supply the grid driving signals to all of the grid lines 4. Optionally, because excessively many shift registers 301 are cascaded, the signals have a certain loss, which affects the normal displaying of the display panel. Therefore, the display panel is delimited into a plurality of active areas 1, and each of the active areas 1 corresponds to one of the grid driving units 3, which can realize supplying stable grid driving signals to the grid lines 4 in large-size display panels or super-high-pixel-density display panels, and can realize subregion controlling over the display panel.
It should be noted that one row of the grid lines 4 may control merely all of or some of the pixel units P in one row of the pixel units P, but one row of the pixel units P can be correspondingly controlled by two grid lines 4. For example, one row of the pixel units P are delimited into subregions or odd-even numbers, to be controlled by two or more grid lines 4.
In some examples,
In some examples,
In some examples, if a plurality of multiplexers 2 are provided, for the frame-starting-up-signal outputting units 201 in the multiplexers 2 that supply the frame starting-up signals to the same grid driving unit 3, the control electrodes of the subregion gating transistors 402 therein are connected to the same second gating signal line 502. The quantity of the frame-starting-up-signal outputting units 201 in the multiplexers 2 is equal to the quantity of the active areas 1 of the display panel. The grid driving units 3 in one active area 1 may have a plurality of grid driving circuits, each of the grid driving circuits corresponds to one of the frame-starting-up-signal outputting units 201 in different multiplexers 2, and the control electrodes of the subregion gating transistors 402 in the frame-starting-up-signal outputting units 201 that correspond to the same active area 1 are connected to the same second gating signal line 502. In other words, the quantity of the second gating signal lines 502 is equal to the quantity of the active areas 1 of the display panel, and is not influenced by the quantity of the multiplexers 2.
In an embodiment of the present disclosure, the multiplexers 2 are used to control the grid driving circuits within the plurality of regions, which reduces the quantity of the signals, and thus reduces the quantity of the signal lines, thereby realizing a sufficient room for the fabrication of the grid driving circuits when the display panel has a high pixel density. That will be illustrated by taking the case as an example in which the display panel is delimited into 9 regions, one row of the pixel units P are divided into odd-even numbers and the pixel driving circuit in
By providing the multiplexers 2, the operations of the grid driving circuits in the grid driving units 3 can be controlled by using the multiplexers 2. One active area 1 corresponds to 5 types of signals, and, therefore, it is required to provide 5 multiplexers 2, which are a first multiplexer 21, a second multiplexer 22, a resetting multiplexer 2 for correspondingly controlling the resetting transistor, an initializing multiplexer 2 for correspondingly controlling the initializing transistor and a light-emission controlling multiplexer 2 for correspondingly controlling the light-emission controlling transistor. The display panel includes 9 subregions, and each of the 5 multiplexers 2 includes 9 frame-starting-up-signal outputting units 201. In order to control all of the grid driving circuits in the display panel to operate, 9 second gating signals, 5 driving-voltage signals, 5 first gating signals and reference-voltage signals that correspond to the 9 subregions are required, wherein the reference-voltage signals include 1 high-voltage signal and 1 low-voltage signal. Merely totally 21 signals are required to realize the controlling over all of the grid driving circuits of the display panel. As compared with the case in which the multiplexers 2 are not provided, by providing the multiplexers 2, the quantity of the signals is highly reduced, and the quantity of the signal lines is also reduced, which enables the room on the display panel available for the fabrication of the circuits to be increased to a certain extent.
In an embodiment of the present disclosure, the second multiplexer 22 is taken as an example for further description. The second multiplexer 22 correspondingly controls the second grid driving circuit 32, to supply the grid driving signals to the even-number-row grid lines 4, to realize supplying the grid driving signals to the even-number-th pixel units P in one row of the pixel units P. In order to write data into the pixel driving circuit by using the data writing transistors, it is required to control the data writing transistors to be turned on. At this point, among the frame-starting-up-signal outputting units 201 of the second multiplexer 22, the control electrodes of the signal gating transistors 401 receive the low-level signal transmitted by the first gating signal line 501, and the signal gating transistors 401 are turned off, to stop sending the reference-voltage signals to the frame-starting-up-signal terminals STU of the corresponding grid driving circuits, at which point the reference-voltage signals are low-level signal. The second gating signal lines 502 send signals to the control electrodes of the subregion gating transistors 402, and the subregion gating transistors 402 are turned on, to send the driving-voltage signals to the frame-starting-up-signal terminals STU of the corresponding grid driving circuits, at which point the frame-starting-up-signal outputting units 201 start operating.
It should be noted that the driving-voltage signals in the multiplexers 2 are different. For example, the waveforms of the driving-voltage signals of the first multiplexer 21 and the second multiplexer 22 are the waveforms of the grid driving signals in
It is realized that, when the entire pixel driving circuit is operating, the first gating signal lines 501, according to the operation time sequence of the pixel driving circuit, control all of the signal gating transistors 401 of the corresponding multiplexer 2 to be turned on or turned off, and accordingly control the operating state of the multiplexer 2. After the first gating signal has supplied the low-level signal to the corresponding multiplexer 2 to cause the signal gating transistors 401 to be turned off, the second gating signal lines 502 select the active area 1 required to operate, the realize cyclic operation or partial operation of the active areas 1.
It should be noted that the quantity of the multiplexers 2 may be varied according to the design of the pixel driving circuit, and may be regulated according to the structural design of the display panel. The quantity of the frame-starting-up-signal outputting units 201 included by each of the multiplexers 2 may be equal to the quantity of the subregions of the display panel, and is not particularly limited further herein.
In an embodiment of the present disclosure,
In some examples, on the basis of the above-described structures, a
reference-voltage-signal switching line 602′ and a first gating-signal switching line 501′ are provided on the substrate. The reference-voltage-signal switching line 602′ and the first gating-signal switching line 501′ extend in the column direction, and the reference-voltage-signal switching line 602′ and the first gating-signal switching line 501′ are separated in the row direction. The reference-voltage-signal switching line 602′ is electrically connected to the reference-voltage signal line 602. The first gating-signal switching line 501′ is electrically connected to the first gating signal line 501. The reference-voltage-signal switching line 602′ and the first gating-signal switching line 501′ extend in the column direction, which facilitates the connection to the circuit board on one side of the display panel, to receive the corresponding signals.
In some examples, on the basis of the above-described structures, the substrate further includes a first conductive layer 802, an inter-layer insulating layer 803 and a second conductive layer 804 that are sequentially arranged in the direction further away from the substrate. The control electrodes of the signal gating transistors 401, the control electrodes of the subregion gating transistors 402, the reference-voltage signal line 602 and the first gating signal line 501 are located at the first conductive layer 802. The driving-voltage signal line 601, the reference-voltage-signal switching line 602′ and the first gating-signal switching line 501′ are located at the second conductive layer 804. The reference-voltage-signal switching line 602′ is electrically connected to the reference-voltage signal line 602 by a first connecting via hole penetrating the inter-layer insulating layer 803. The first gating-signal switching line 501′ is electrically connected to the first gating signal line 501 by a second connecting via hole penetrating the inter-layer insulating layer 803. The driving-voltage signal line 601 is electrically connected to the first electrode of the subregion gating transistor 402 by a third connecting via hole penetrating the inter-layer insulating layer 803. The first electrodes of the subregion gating transistors 402 are connected to the independent third connecting via holes. The reference-voltage signal line 602 and the driving-voltage signal line 601 may also be provided with reference-voltage-signal lead wires and driving-voltage-signal lead wires that extend in the column direction and are arranged in parallel in the row direction. The reference-voltage-signal lead wires correspond to the signal gating transistors 401 one to one, and the driving-voltage-signal lead wires correspond to the subregion gating transistors 402 one to one. The reference-voltage-signal lead wires and the driving-voltage-signal lead wires may be provided in the first conductive layer 802, the second conductive layer 804 or another film layer, which is not particularly limited further herein. The side of the first conductive layer 802 that is closer to the substrate further includes a first semiconductor layer 801. The first semiconductor layer 801 is used to fabricate the active layers of the subregion gating transistors 402 and the signal gating transistors 401, the arrangement modes of which are the same as the arrangement modes of the subregion gating transistors 402 and the signal gating transistors 401, and are not described repeatedly herein. A grid insulating layer is between the first semiconductor layer 801 and the first conductive layer 802.
In some examples, the first conductive layer 802 further includes second gating-signal switching terminals 502′, and the second gating-signal switching terminals 502′ are configured for connecting the control electrodes of the subregion gating transistors 402 to the independent second gating-signal switching terminals 502′. The second gating-signal terminals are connected to the corresponding second gating signal lines 502. The second gating signal lines 502 may be provided in the first conductive layer 802, the second conductive layer 804 or another film layer according to practical demands and product designs, which is not particularly limited further herein.
In some examples, the second conductive layer 804 further includes frame-starting-up-signal switching lines 7. The frame-starting-up-signal switching lines 7 are individually connected to a frame-starting-up-signal terminal STU of the grid driving circuit corresponding thereto. The frame-starting-up-signal switching lines 7 extend in the column direction, and the frame-starting-up-signal switching lines 7 are arranged in parallel in the row direction. The frame-starting-up-signal switching lines 7 are connected to the second electrodes of the signal gating transistors 401 by fourth connecting via holes penetrating the inter-layer insulating layer 803, and the second electrodes of the signal gating transistors 401 are electrically connected to the frame-starting-up-signal switching lines 7 by the independent fourth connecting via holes. The frame-starting-up-signal switching lines 7 are connected to the second electrodes of the subregion gating transistors 402 by fifth connecting via holes penetrating the inter-layer insulating layer 803, and the second electrodes of the subregion gating transistors 402 are electrically connected to the frame-starting-up-signal switching lines 7 by the independent fifth connecting via holes.
In an embodiment of the present disclosure,
In some examples, as shown in
In an embodiment of the present disclosure, the first node Q is the connection point of the second electrodes of the first transistor T1 and the second transistor T2, the first electrode of the third transistor T3, the control electrode of the fifth transistor T5, the first electrode of the sixth transistor, and the control electrodes of the eighth transistor and the tenth transistor. The second node QB is the connection point of the first electrode of the fifth transistor T5, the first electrode of the seventh transistor T7, the control electrodes of the ninth transistor and the eleventh transistor T11, and the first electrode of a second storing unit 3018. Therefore, the voltage of the first node Q controls the switching of the eighth transistor and the tenth transistor, and the voltage of the second node QB controls the switching of the ninth transistor and the eleventh transistor T11. Therefore, in order to cause the cascading unit 3015 to output the cascading signal and cause the outputting unit 3016 to output the grid driving signal, it is required to cause the first node Q to be at a high electric potential, and cause the second node QB to be at a low electric potential.
In some examples, the controlling unit 3011 includes a first transistor T1 and a second transistor T2. The control electrode of the first transistor T1 is connected to the frame-starting-up-signal terminal STU, the first electrode is connected to a first level-signal terminal CN, and the second electrode is connected to the second electrode of the second transistor T2 and the first node Q. The control electrode of the second transistor T2 is connected to the resetting-signal terminal STD, and the first electrode is connected to a second level-signal terminal CNB. The control electrode of the first transistor T1 is connected to the frame-starting-up-signal terminal STU, and the frame-starting-up-signal terminal STU is connected to the cascading-signal terminal CR of the shift register 301 of the preceding stage. The control electrode of the second transistor T2 is connected to the resetting-signal terminal STD, and the resetting-signal terminal STD is connected to the cascading-signal terminal CR of the shift register 301 of the subsequent stage. If the displaying mode of the display panel is forward scan, the electric properties of the first level-signal terminal CN and the second level-signal terminal CNB are opposite, the first level signal CN is a high-level signal, and the second level signal CNB is a low-level signal. If the displaying mode of the display panel is reverse scan, the first level signal CN is a low-level signal, and the second level signal CNB is a high-level signal. All of the embodiments of the present disclosure illustrate by taking the case as an example in which the displaying mode of the display panel is forward scan. After the first transistor T1 has received the frame starting-up signal, the first transistor T1 is switched on, and the high-level first level signal CN charges the first node Q. After the second transistor T2 has received the resetting signal, the second transistor T2 is switched on, the low-level second level signal CNB discharges the first node Q.
In some examples, the initializing unit 3012 includes a third transistor T3, the control electrode of the third transistor T3 is connected to an initializing-signal terminal RST, the first electrode is connected to the first node Q, and the second electrode is connected to a common-voltage terminal VGL. The third transistor T3 is turned on merely before the display panel displays, and initializes the voltage of the first node Q.
In some examples, the feedback unit 3013 includes a fourth transistor T4 and a fifth transistor T5, the first electrode and the control electrode of the fourth transistor T4 are connected to a second clock-signal terminal CLKb, and the second electrode is connected to the second node QB and the first electrode of the fifth transistor T5. The control electrode of the fifth transistor T5 is connected to the first node Q, and the second electrode is connected to the common-voltage terminal VGL. When the shift register 301 is outputting, the first node Q is at a high electric potential, the fifth transistor T5 is turned on under the controlling by the first node Q, the first electrode of the fifth transistor T5 is connected to the second node QB, and the fifth transistor T5, after being turned on, discharges the second node QB. After the outputting of the shift register 301 is completed, the shift register 301 charges the second node QB under the controlling by the third clock signal CLKc, and the voltage signal supplied by the third clock signal CLKc is stored in a second storage capacitor C2.
In some examples, the voltage regulating unit 3014 includes a first-node-Q discharging unit and a second-node-QB discharging unit. The first-node-Q discharging unit, after the outputting of the shift register 301 is completed, under the controlling by the voltage of the second node QB, discharges the first node Q. The second-node-QB discharging unit, when the shift register 301 is outputting, discharges the second node QB.
Particularly, the first-node-Q discharging unit includes a sixth transistor, the control electrode of the sixth transistor is connected to the second node QB, the second electrode of the fourth transistor T4 and the first electrode of the fifth transistor T5, the first electrode is connected to the first node Q, and the second electrode is connected to the common-voltage terminal VGL. After the outputting of the shift register 301 is completed, the feedback unit 3013 charges the second node QB, at which point the second node QB is at a high electric potential, and the sixth transistor is turned on, to discharge to the first node Q. The second-node-QB discharging unit includes a seventh transistor T7, the control electrode of the seventh transistor T7 is connected to a cascading-signal terminal CR, the first electrode is connected to the common-voltage terminal VGL, and the second electrode is connected to the second node QB. The grid driving signal and the cascading signal of the shift register 301 are outputted simultaneously. The control electrode of the seventh transistor T7 is connected to a cascading-signal terminal CR. In outputting, the seventh transistor T7 is turned on, to discharge to the second node QB, to ensure that the second node QB, when outputting, is at a low-level. The ninth transistor and the eleventh transistor T11 are not turned on to influence the outputting of the cascading signal and the grid driving signal.
In some examples, the cascading unit 3015 includes an eighth transistor and a ninth transistor. The control electrode of the eighth transistor is connected to the first node Q, the first electrode is connected to the second clock-signal terminal CLKb, and the second electrode is connected to the first electrode of the ninth transistor. The control electrode of the ninth transistor is connected to the second node QB, and the second electrode is connected to the common-voltage terminal VGL. The connection point of the second electrode of the eighth transistor and the first electrode of the ninth transistor is used as a cascading-signal terminal CR of the shift register 301. The ninth transistor, after the outputting of the cascading signal is completed, is turned on under the controlling by the voltage of the second node QB, to pull down the electric potential of the cascading-signal terminal CR.
In some examples, the outputting unit 3016 includes a tenth transistor, an eleventh transistor T11 and a first storage capacitor C1. The control electrode of the tenth transistor is connected to the first node Q and the first electrode of the first storage capacitor C1, the first electrode is connected to a first clock-signal terminal CLKa, and the second electrode is connected to the first electrode of the eleventh transistor T11 and the second electrode of the first storage capacitor C1. The control electrode of the eleventh transistor T11 is connected to the second node QB, and the second electrode is connected to the common-voltage terminal VGL. The connection point of the second electrode of the tenth transistor, the first electrode of the eleventh transistor T11 and the second electrode of the first storage capacitor C1 is used as a grid-driving-signal terminal OUT of the shift register 301. The eleventh transistor T11, after the outputting of the grid driving signal is completed, is turned on under the controlling by the voltage of the second node QB, to pull down the electric potential of the grid-driving-signal terminal OUT.
In some examples, the time domains and the amplitudes of the first clock signal and the second clock signal CLKb are totally the same, and, therefore, they may be connected to the same clock-signal line, to reduce the quantity of the signal lines, which facilitates the fabrication of a narrow border frame. The first clock-signal terminal CLKa and the second clock-signal terminal CLKb may also be separate, to be connected to different clock-signal lines, to prevent that, when a plurality of shift registers 301 are cascaded, the clock signal received by the shift register 301 of the final stage has loss. When the displaying device is a large-size display panel, each of the subregions has a high row quantity of the pixels, the clock signal might have loss in transmission, and the first clock-signal terminal CLKa and the second clock-signal terminal CLKb may be separate as two clock-signal lines to be controlled separately. When it is required to realize a narrow border frame, the first clock-signal terminal CLKa and the second clock-signal terminal CLKb may be connected to the same clock-signal line, to reduce the occupied area of the border frame.
In some examples, on the basis of the above-described structures, the shift register 301 further includes a correcting unit 3017. The correcting unit 3017 is configured for, under the controlling by an enabling-signal terminal EN, enabling the shift register 301 to output a correction controlling signal. The correcting unit 3017 includes a twelfth transistor T12 and a thirteenth transistor T13. The control electrode and the first electrode of the twelfth transistor T12 and the enabling-signal terminal EN are connected to the control electrode of the thirteenth transistor T13, and the second electrode is connected to the grid-driving-signal terminal OUT. The first electrode of the thirteenth transistor T13 is electrically connected to the common-voltage terminal VGL, and the second electrode is electrically connected to the second node QB. In normal displaying, the enabling signal maintains at a low electric potential, and the twelfth transistor T12 and the thirteenth transistor T13 are in the off-state. When abnormality in displaying happens, the enabling signal changes into a high electric potential, and the twelfth transistor T12 and the thirteenth transistor T13 are in the on-state. The enabling signal is directly used as the grid driving signal to be sent to the pixel driving circuit, to correct the abnormality in displaying. The particular type of the enabling signal and the particular correcting method for the pixel driving circuit are not particularly limited further herein.
In some examples, the shift register 301 further includes a storing unit 3018. The storing unit 3018 is configured for storing the voltage of the second node QB. The storing unit 3018 includes a second storage capacitor C2, the first electrode of the second storage capacitor C2 is connected to the second node QB, and the second electrode is connected to the common-voltage terminal VGL.
In some examples, as shown in
In order to describe the structure of the shift register 301 according to the present disclosure better, it will be illustrated below with reference to particular examples. Referring continuously to
In order to describe the working process of the grid driving circuit according to the embodiments of the present disclosure better, it will be illustrated below with reference to the particular embodiments. Referring continuously to
In an embodiment of the present disclosure,
It should be noted that the second semiconductor layer of the grid driving circuit may be in the same plane as that of the first semiconductor layer of the multiplexer, the third conductive layer of the grid driving circuit may be in the same plane as that of the first conductive layer of the multiplexer, and the fourth conductive layer of the grid driving circuit may be in the same plane as that of the second conductive layer of the multiplexer.
The grid-driving-circuit array according to the embodiments of the present disclosure may also be used in the technique of 3D displaying, so as to, by providing the subregions of the display panel, realize different clarities of different subregions. According to the demands on the refresh frequency in displaying, for different regions, the pixel units P are combined for the displaying, to reduce the resolutions of the subregions. In the existing IC, the signal refresh time should not be less than 1.45 μs. For ultrahigh-resolution displaying, for example, a resolution of 3840×2160, one pixel group has 11 pixel units P in the horizontal direction and three rows of RGB pixels in the vertical direction, i.e., 3840×11 columns of pixels in the horizontal direction and 2160×3 rows of pixels the vertical direction. When the refresh frequency is 30 Hz, it can be realized that 6 regions are of a high definition and 3 regions are of a medium definition, or that 7 regions are of a high definition and 2 regions are of a low definition. Therefore, by using the multiplexers 2 to control the grid driving units 3 of the active areas 1, subregions displaying can be realized in which different regions have different clarities, to be used in high-PPI 3D displaying techniques.
An embodiment of the present disclosure further provides a display panel, wherein the display panel includes the grid-driving-circuit array according to any one of the above embodiments. The display panel is delimited into a pixel region and a non-pixel region. The grid driving units and the multiplexers of the grid-driving-circuit array are located within the non-pixel region. The non-pixel region includes a fanning-out trace region located on one side of the pixel region, and the multiplexers are located within the fanning-out trace region, and the grid-driving-circuit array is located on the lateral side of the display panel.
It should be understood that the above-described structure is merely an example, and may be adjusted according to practical demands of products, which is not particularly limited further herein.
It can be understood that the above embodiments are merely exemplary embodiments intended to describe the principle of the present disclosure, but the present disclosure is not limited thereto. A person skilled in the art may make various variations and improvements without departing from the spirit and the essence of the present disclosure, and those variations and improvements are also considered as falling within the protection scope of the present disclosure.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2023/085635 | 3/31/2023 | WO |
