The subject matter disclosed herein relates generally to industrial controllers for controlling industrial processes or machinery. More specifically, a hardware based system for managing timers associated with connections to the industrial controller is disclosed.
Industrial controllers are special purpose computers used for controlling factory automation and the like. The control program executed by the industrial controller is normally highly customized to a particular control application. Special control languages, such as “relay ladder logic” are normally used to facilitate programming of the device. The stored control programs may be continuously executed in a series of execution cycles, repeated periodically, or executed based on events. Due to the potentially high costs associated with downtime of an industrial process such as an assembly line, the industrial controller must ensure predictable high-speed execution of the instructions for reliable real-time control.
Under the direction of the stored program, the industrial controller periodically examines a series of inputs reflecting the status of the controlled process and changes outputs affecting the control of the process. The inputs and outputs may be binary (i.e., “on” or “off”) or, alternatively, analog inputs and outputs taking on a continuous range of values may also be used. The binary inputs and outputs may be represented by single bits of data; the analog inputs and outputs may be represented by multiple bit data words.
In order to ensure predictable control of the process, the communication between the controller and the inputs and outputs must be highly reliable and performed at well-defined periods. The controller must also verify that the input and output (I/O) devices connected to the controller continue operating properly. Typically, the controller includes a task which periodically monitors operation of the I/O devices. The monitoring task may, for example, check that the I/O devices have recently communicated with the controller. If an I/O device stops communicating with the controller, the controller may optionally try to restore communications with the I/O device or set a fault message indicating that the I/O device has ceased operating.
However, as industrial processes grow in complexity, an increasing number of devices are being connected to the industrial controller. The increasing number of devices causes the monitoring task to execute for an increasing amount of time, resulting in a reduction of processing time available to the control program. If too many devices are connected to the industrial controller, the controller may no longer be able to ensure predictable high-speed execution of the control program. Presently, an industrial controller can monitor up to about two hundred fifty I/O devices before the task of monitoring I/O devices demands too much processing time and bandwidth.
Consequently, it would be desirable to provide a monitoring system that executes independently of the processor to verify that the I/O devices connected to the industrial controller continue proper operation. It would also be desirable to significantly increase the number of I/O devices that can be monitored to accommodate the increasing number of connections required by more complex industrial processes.
The present invention provides a hardware implemented connection monitoring system. A timer array establishes an input and an output connection timer for each connection between the processor and an I/O device where an I/O device may be any device capable of providing input or output signals to the processor. A state machine periodically steps through the timer array to update the accumulated values of the timers and to monitor if any of the timers has reached a preset, timer done value. If a connection timer reaches the timer done value, the state machine loads the state of the connection timer into an event buffer and generates an interrupt for the processor. The processor reads the event buffer, identifies whether the expired timer was an input timer or an output timer, and takes action accordingly.
In one embodiment of the invention, a connection monitoring system for an industrial controller includes a processor executing a program to periodically communicate with multiple Input/Output (I/O) devices connected to the processor. A hardware timer array includes at least one connection timer associated with each of the of I/O devices. A state machine executes separately from the processor to monitor each connection timer to provide a signal to the processor in response to a change in state of the timer.
Thus, it is a feature of the invention that a system executing independently of the processor increases the processing time available on the processor and monitors the connections between the I/O devices and the processor.
As another aspect of the invention, the timer array may allocate both an input and an output timer for each of the I/O devices connected to the processor. Thus, it is another feature of the invention that the timer array supports bidirectional communication for any I/O device.
As yet another aspect of the invention, the connection monitoring system includes a dedicated interface between the hardware timer array and the state machine. The dedicated interface provides quick access to the timer array by the state machine and reduces the bandwidth requirements for accessing memory in the controller.
As another aspect of the invention, the connection monitoring system includes a command buffer for transmitting messages between the processor and the state machine and an event buffer for transmitting the signals between the state machine and the processor upon the change in state of the connection timer. The connection monitoring system may also include at least one additional event buffer and the state machine may selectively load the signal from each timer into one of the event buffers. Multiple event buffers may, for example, permit the state machine to separate state change events, such as input or output time-out events, prior to transmitting the state of the timers to the processor, or, alternately, the event buffers may be processed by separate processors or by separate processing cores executing on a single processor.
The connection monitoring system may also include at least one additional state machine wherein each of the state machines monitors a portion of the timer array. Multiple state machines optionally permit the timers to be scanned more frequently or permit a reduction in the clock speed.
In another embodiment of the invention, a connection monitoring system for an industrial controller includes a first and a second processor. At least one of the processors executes a program to periodically communicate with at least one of a plurality of Input/Output (I/O) devices. A hardware timer array includes at least one timer associated with each of the plurality of I/O devices. A first state machine executes separately from each of the processors to monitor each timer to provide a signal to at least one of the processors upon expiration of the timer. The connection monitoring system also includes a dedicated communication channel between the hardware timer array and the first state machine. A command buffer transmits messages between at least one of the processors and the first state machine, and a first event buffer transmits the signals between the first state machine and the at least one processor upon expiration of the timer.
As another aspect of the invention, the connection monitoring system may include at least one additional state machine, and each of the state machines monitors the state of a portion of the timer array. The connection monitoring system may also include a second event buffer. The state of each timer may be selectively loaded into one of the event buffers. The processors may interface with the state machine in different configurations. For example, the first processor may read from the first event buffer and the second processor may read from the second event buffer. Optionally, the first processor may interface with the command buffer and the second processor may interface with the event buffer.
Thus, it is another feature of this invention that the state machine may interface with a multi-processor controller. The system may be flexibly configured such that each processor interfaces to either the command or the event buffer of the state machine, or, optionally, the state machine may include multiple command or event buffers such that each processor performs a portion of the interface with each buffer.
These and other advantages and features of the invention will become apparent to those skilled in the art from the detailed description and the accompanying drawings. It should be understood, however, that the detailed description and accompanying drawings, while indicating preferred embodiments of the present invention, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the present invention without departing from the spirit thereof, and the invention includes all such modifications.
Various exemplary embodiments of the subject matter disclosed herein are illustrated in the accompanying drawings in which like reference numerals represent like parts throughout, and in which:
In describing the various embodiments of the invention which are illustrated in the drawings, specific terminology will be resorted to for the sake of clarity. However, it is not intended that the invention be limited to the specific terms so selected and it is understood that each specific term includes all technical equivalents which operate in a similar manner to accomplish a similar purpose. For example, the word “connected,” “attached,” or terms similar thereto are often used. They are not limited to direct connection but include connection through other elements where such connection is recognized as being equivalent by those skilled in the art.
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The processor module 14 also includes a connection monitoring system 40 in communication with the processor 30. The connection monitoring system 40 includes a state machine 42 communicating with a second memory 44. Preferably, a dedicated interface 43, such as a data bus, exists between the state machine 42 and the second memory 44. The state machine 42 also communicates with the processor 30 via an event buffer 46 and a command buffer 48. The connection monitoring system 40 may additionally generate an interrupt signal 50 to the processor indicating data has been written to the event buffer 46. Preferably, the processor 30 and the connection monitoring system 40 are implemented as separate blocks on a single application specific integrated circuit (ASIC). Optionally, any number of ASICs or individual processor, memory, and buffer devices may be used to implement the processor 30 and connection monitoring system 40 as illustrated in
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The processor module 14 also includes a connection monitoring system 40. The connection monitoring system 40 includes a state machine 42 communicating with a second memory 44. Preferably, a dedicated communication path 43 exists between the state machine 42 and the second memory 44, permitting rapid access of the data stored in the second memory 44 by the state machine 42. As illustrated in
In operation, the connection monitoring system 40 uses the state machine 42 to manage the hardware timer array 128 for monitoring the status of each of the connections between the processor 30 and one of the I/O devices 20. The timer array 128 is stored in the second memory 44 such that the state machine 42 has dedicated access to the timer array 128 via the interface 43. Referring to
At step 102, the state machine 42 processes each of the connection timers 130 in the timer array 128. Referring to
The hardware timer array 128 includes at least one and preferably a pair of connection timers 130 associated with each connection between the processor 30 and one of the I/O devices 20. Connection timers 130 may be allocated for any connection to the processor 14, including, but not limited to, analog or digital inputs or outputs from I/O devices 20, additional controllers 10, network interface modules, or user interfaces, Each I/O device 20 will respectively provide either an input value to the processor 30 or receive an output value from the processor 30. Because industrial controllers 10 require program execution that is highly-dependable and repeated at well-defined intervals, the processor 14 preferably receives from or transmits to each of the I/O devices 20 an I/O signal 18 at a predefined Requested Packet Interval (RPI). In addition, the controller 10 may be configured to establish a “heartbeat” communication between the processor 30 and each I/O device 20. The heartbeat is a communication transmitted at a longer periodic interval than the interval between data communications and is used to verify that the I/O device 20 is functioning properly. For example, the processor 30 may periodically send an input device a message to verify that it is active and/or that it is capable of changing state. An output device may also be configured to periodically send the processor 30 a message to indicate that it is receiving the output signals 18 and that it is functioning properly.
The combination of data signals and heartbeat signals result in many I/O devices 20 requiring bi-directional communication between the processor 30 and the I/O device 20. By associating a pair of connection timers 130 with each I/O device 20, the state machine 42 can monitor communications both transmitted to and from the processor 30. The preset register 134 of each timer 130 may be set to a different value such that the communications to and from each I/O device 20 may be monitored at a different rates, for example for I/O data or for heartbeat signals.
Although, the industrial controller 10 requires dependable communications between the processor 30 and the I/O devices 20, it is expected and acceptable that some communication errors will occur. If the processor 30 or the I/O device 20 fails to receive a communication within the RPI, either the original communication may be resent or a new communication may be sent. The controller 10 may be configured to identify the maximum length of time permitted between successful communications between the processor 30 and an I/O device 20 that may occur before action is taken. For example, the processor 30 may be configured such that the maximum length of time between successful data signal communications is four times the RPI or twenty times the RPI between successful heartbeat communications.
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The event buffer 46 is used to communicate events, or changes in state, of a timer 130, such as the expiration of a timer 130, from the state machine 42 to the processor 30. Because the events in the event buffer 46 may be used to force a write from the processor 30 to an I/O device 20, the events in the buffer 46 may also include immediate output commands sent from the processor 30 to the state machine 42 triggering a communication prior to the expiration of a timer 130.
Processing the event buffer 46, as indicated by step 104, includes monitoring timer events in the state machine 42 and output commands from the processor 30 to trigger action by the processor 30. Referring next to
The event buffer 46 is preferably a first-in-first-out (FIFO) buffer managed by the state machine 42. The event buffer 46 has a finite depth and transfers a limited number of events to the processor 30 at periodic intervals. At step 158, the state machine 42 checks to see if there are events in the queue to be transmitted to the processor 30. If there are no events in the queue, processing of the event buffer 46 for that interval is complete. If there are events in the queue to be transmitted, the state machine 42 checks if there is space in the event buffer 46 to add another event at step 160. If there is space in the event buffer 46, the state machine 42 passes the next event in the queue into the event buffer 46 at step 162. In step 164, the state machine determines if additional events remain in the queue. If any events remain in the queue, the state machine returns to step 160 to check if there is any space remaining in the event buffer 46. If all events in the queue have been transferred to the event buffer 46, the state machine 42 generates an interrupt signal 50 to notify the processor 30 that there are events in the event buffer 46 that require processing. In one embodiment, the event buffer 46 has a depth of sixteen events to be transmitted during each interval. Optionally, the event buffer 46 may have any suitable depth or the connection monitoring system 40 may include multiple event buffers 46.
The processor 30 services the interrupt signals 50 from the connection monitoring system 40 as well as signals 36 to or from the I/O devices 20. During normal operation, an input module, for example, will periodically transmit an input signal 36 to the processor 30 and the processor 30 will send an output signal 36 to an output module. Upon completion of a normal communication between the processor 30 and an I/O device 20, the processor 30 may send a reset timer command to the state machine 42, resetting the accumulator register of the timer 130 associated with the input or output communication for the respective I/O device 20.
If the interrupt signal 50 from the connection monitoring system 40 is set, the processor reads the events from the event buffer 46 and takes appropriate action. The event may indicate that normal communications have not occurred within the predefined time limit or that the processor 30 is to process a heartbeat communication. If an input module has not communicated with the processor 30 within the predefined time, the processor may declare a fault condition. The processor 30 may be preconfigured to take different levels of action, depending on how critical the faulted input device is to the controlled process. The processor 30 may, for example, permit the controlled process to continue and only post a fault message or the processor 30 may require an immediate shut down of the controlled process. If the processor 30 has not successfully communicated with an output module within the predefined time, the processor 30 may immediately send a message to the output module. The action taken by the processor 30 in response to an output module timeout is also preferably preconfigured according to the specific output device.
The program executing on the processor 30 may also require immediate rather than periodic updates of some of the I/O devices 20. The processor 30 may send a command to the state machine 42 identifying to which I/O device an immediate output is desired. The state machine 42 places the timer information in the event buffer 46 and sets the interrupt signal 50. The processor 30 services the interrupt signal 50 and sends a message to the identified I/O device 20.
Although utilizing the state machine 42 to process immediate output commands integrates this feature with the communication monitoring performed by the state machine 42, the potential exists for a program to command an immediate output to one or more I/O devices 20 at too frequent of a time interval, such that the state machine 42 cannot properly manage the timer array 128. Consequently, when the state machine 42 receives an immediate output request, the state machine 42 compares the value of the accumulator register 132 to the value of the preset register 134 for the timer 130 associated with the target I/O device 20. The state machine 42 prevents the immediate output request from occurring until a minimum time has occurred from the previous output request. Preferably, at least 25% of the time set in the preset register will have passed prior to allowing subsequent output requests to be processed.
The command buffer 48 allows the processor 30 to interface with the timer array 128. Referring to
Because it is possible that a significant number of timers 130 may have the same RPI, the processor 30 may configure the timers 130 to be offset from each other. For example, a controller 10 may include many of the same type of I/O devices 20. Each of these I/O devices 20 would either be written to or have the heartbeat signal received at the same RPI. Consequently, each of the timers 130 associated with and configured to monitor communications with these I/O devices 20 would initially have the same preset value and would expire at the same time. In order to prevent a potential overload of the queue for the event buffer 46, an offset, or varying offsets, may initially be set in the timers 130 to stagger expiration of the timers 130. In one embodiment, the processor 30 may load different initial values into the accumulator register 132 of each timer 130 having identical default preset values such that the initial expiration of these timers occurs at varying time intervals. Subsequent expirations of the timers 130 will occur at the preset interval from the initial expiration, causing the timers 130 to continue to expire at times offset from each other.
Referring again to
In yet another embodiment, the connection monitoring system 40 may include multiple command buffers 48 and multiple event buffers 46 each configured substantially as described above. Each buffer may be configured to interface with a portion of the timer array 128 or to interface with one of multiple processors, 30 or 31, or multiple cores in a single processor. It is also contemplated that multiple state machines 42 may be included to manage portions of a timer array 128 and may similarly interface with one of multiple processors, 30 or 31, or multiple cores in a single processor. Still other embodiments may utilize varying numbers and interconnections of processors, 30 or 31, event buffers 46, command buffers 48, and state machines 42 to realize varying efficiencies of processing and responsiveness to timer events.
It should be understood that the invention is not limited in its application to the details of construction and arrangements of the components set forth herein. The invention is capable of other embodiments and of being practiced or carried out in various ways. Variations and modifications of the foregoing are within the scope of the present invention. It also being understood that the invention disclosed and defined herein extends to all alternative combinations of two or more of the individual features mentioned or evident from the text and/or drawings. All of these different combinations constitute various alternative aspects of the present invention. The embodiments described herein explain the best modes known for practicing the invention and will enable others skilled in the art to utilize the invention