Patent Application
20140068220
The present invention relates generally to a hardware based memory allocation system with directly connected memory, and more specifically, to a hardware based memory allocation system that efficiently manages memory blocks associated with a high-capacity, multi-channel memory across a large number of requestors for memory data transfer.
Computer systems are used on a personal level and on a commercial level such as in data centers which are generally large centralized facilities of computer systems that provide Internet and/or intranet services supporting businesses and organizations. A typical data center can house various types of electronic equipment, such as computer systems, domain name system (DNS) servers, network switches, routers, and data storage devices. A typical data center can have hundreds or thousands of interconnected servers communicating with each other and external devices via a switching architecture comprising the switches and routers. Conventional data centers can also be configured for virtualization, permitting servers or the like to share network interface cards (NICs), hard disk drives, or other hardware. A complex switch fabric can facilitate communications between the servers.
Data transfer requests between computers are typically implemented in a formatted unit of data called a data packet carried by a packet mode computer network which is standard in today's operating systems and networks. When data is transferred between devices, it is necessarily stored for some period of time into one or more memory devices.
Computer systems store, manipulate and transfer data in memory devices such as, but not limited to, random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), through-silicon via (TSV), etc.
Conventional data transfer and memory allocation is provided by software algorithms specific to the particular operating system, memory type and application requirement. These software algorithms tend to become very complex, expensive, relatively slow, difficult to trouble-shoot, and consuming extensive processing time and resources especially when attempting to manage memory blocks within a high capacity multi-channel memory across a large number of data requestors.
Certain aspects and embodiments of the invention provide a hardware based memory allocation system with directly connected memory to optimize (i.e., improve under certain conditions) the allocation and transfer of data to and from memory and improving overall speed, reliability and performance of computer systems.
Certain aspects and embodiments of the present invention provide a hardware based memory allocation system with directly connected memory for facilitating data transfer without the requirement of a software algorithm.
In accordance with an aspect, provided in one embodiment is a hardware based memory allocation system in a computer including: a memory module formatted with memory blocks; an input controller, in communications with the memory module and receiving a transfer request from a requestor, for transferring data from a source to the memory module; an output controller, in communications with the memory module and the input controller, for transferring data from the memory module to a destination; and a block allocator, in communications the input controller and the output controller, for maintaining a Block Descriptor Index (BDI) of Free List (FL) Addresses, each FL address pointing to a Block Descriptor Page (BDP) having a plurality of Memory Block (MB) addresses, each MB address pointing to a free memory block in the memory module.
In accordance with another aspect, provided in a further embodiment is a computer memory allocation method including the steps of: receiving a request from a requestor to transfer data from a source to a memory module formatted with memory blocks; transferring data from the source to the memory module according to instructions from an input controller; and communicating a location of a free memory block in the memory module according to a Block Descriptor Index (BDI) of Free List (FL) Addresses, each FL address pointing to a Block Descriptor Page (BDP) having a plurality of Memory Block (MB) addresses, each MB address pointing to a free memory block in the memory module, wherein the BDI and BDP are maintained by a block allocator in communications with the input controller and an output controller.
The above and further advantages of this invention may be better understood by referring to the following description in conjunction with the accompanying drawings, in which like numerals indicate like structural elements and features in various figures. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.
In the following description, specific details are set forth although it should be appreciated by one of ordinary skill that the systems and methods can be practiced without at least some of the details. In some instances, known features or processes are not described in detail so as not to obscure the present invention.
In order to efficiently manage highly parallel, multi-channel memory with a large number of requestors for memory data transfer, a block allocator (BA) is located at a central location and preferably associated with memory controller logic. The memory, which may be organized as discrete memory accessible through multiple channels, is divided into blocks of a fixed size, where the size is implementation specific and chosen to maximize overall efficiency. In order to efficiently allocate blocks to requestors the BA maintains a block of block pointers called the Block Description Page (BDP), as well as a block of pointers that indicate a location of each BDP called the Block Descriptor Index (BDI).
The system 100 includes: a memory module 108; an input controller 104 connected via line 118 to the memory module 108 and via line 114 to a source 102 in order to receive a request from a requestor device (not shown) and to receive data from the source 102. The system 100 also includes an output controller 110 connected via line 126 to the destination device 112, via line 120 to the input controller 104 and via line 124 to the memory module 108 for transferring data from the memory module 108 to the destination device 112; and a block allocator 106 connected via line 130 to the input controller 104 and via line 122 to the output controller 110.
The memory module or other storage device 108 contains memory such as, but not limited to, TSV, RAM, SRAM, DRAM etc. Note that the memory module storage device 108 may be any type of data storage device whether long term or transient and whether labeled as memory, a switch, or any other device which holds data for some length of time. For consistency, we will refer to the storage device as memory module 108.
Organization of the data in memory is provided by formatting the memory into application specific sized memory blocks according to the needs of a given application. A memory pool, or a fixed size memory block allocation, allows dynamic memory allocation whereby memory block sizes are preallocated for optimization of particular data transfer applications to and from the memory module 108.
An allocated memory block is typically represented with a handle and an access pointer to the allocated memory. The handle can be divided into a pool index, a memory block index and a version. The pool and memory block index allow fast access to the corresponding memory block with the handle, while the version, which is incremented at each new allocation, allows detection of handles whose memory block is already freed. Additionally, memory pools of memory blocks allow memory allocation with constant execution time and no fragmentation, and fixed-size memory pools of memory blocks do not need to store allocation metadata for each allocation, describing characteristics like the size of the allocated memory block.
The memory block allocator 106 of the present invention shown in
The requestor for moving or transferring data to, from, or through the hardware based memory allocation system 100 simply makes a request by way of the input controller 104. Once the data transfer request is made, the requestor does not receive any specific information about the transfer operation since the transfer of data is performed strictly at a hardware level.
A request for data to be saved into memory or retrieved from memory is initiated with the requestor device such as the source device 102 in
The requested information is typically formatted for transfer as a data packet 132 which is a formatted unit of data carried by a packet mode computer network, standard in today's operating systems and networks. A data packet 132 consists of two kinds of data: control data and user data also know as payload data. The control data provides data that the network needs to deliver the payload data, for example, source and destination addresses, error detection codes like checksums, and sequencing information. Typically control data is found in packet headers and trailers, with payload data packed in between. Different communications protocols use different conventions for distinguishing between the elements and for formatting the data. In Binary Synchronous Transmission, the packet is formatted in 8-bit bytes, and special characters are used to delimit the different elements. Other protocols like Ethernet, establish the start of the header and data elements by their location relative to the start of the packet. Some protocols format the information at a bit level instead of a byte level.
Data Transfer from a Source Device
The input controller 104 first receives a request from the requestor device, which in this case is the source 102, to send data to memory for storage. At least in the switch the request is really to just move data, and the memory is hidden from the requestor. Any number of data packets 132 could be transferred from one or more sources 102 to one or more memory devices 108 and further to one or more destination devices 112. Also, all communications between components of the system 100, and with externally located sources and destinations, could be either hard-wired or wireless.
The block allocator 106, along with the input controller 104 and the output controller 110, control the data flow to and from the memory module 108. After the input controller 104 receives the request via connector 114 for transferring data either to the memory module 108 for storage, or to the destination device 112, then the input controller 104 sends a request via connector 130 to the block allocator 106 for a list of free memory block addresses in the memory module 108. The block allocator 106 keeps track of all free memory blocks in the memory module 108, keeping track of all free memory blocks available for use.
In the alternative, it may improve speed and efficiency if the output controller 110 releases memory blocks that have been freed up back to the input controller 104 rather than to the block allocator. Also, the input controller 104 may request a list of free memory block addresses available in the memory module 108 prior to receiving any specific external request for data transfer in order to improve performance. By pre-fetching of a list of free memory blocks or by maintaining a full list of free memory block addresses at all times, the input controller 104 will reduce the number of requests to the block allocator 106, thus increasing overall speed and efficiency.
Block descriptor page 220 is located in the memory module 108 and contains a list of free memory block addresses 222-1, 222-2, 222-3 to 222-n (where n is a positive integer); block descriptor page 230 also located in memory module 108 contains a list of free memory block addresses 224-1, 224-2, 224-3 to 224-n; etc. Free memory block address 222-1 points to free memory block DAT0, free memory block address 222-1 points to free memory block DAT1, free memory block address 222-3 points to free memory block DAT2, etc. As shown in
Typically the data packet 132 (
Once the input controller 104 receives the list of free memory blocks available in the memory module 108 from the block allocator 106 via connector 130, then the block allocator 106 would likely remove them from its list. The input controller 104 will write data from data packets 132 received via connector 114 from the source 102 to the memory blocks, allocated by the block allocator 106, in the memory module 108 via connector 118. After the data is transferred, the block allocator 106 will remove the blocks where the newly transferred data resides in memory from its free block address list in the BDI.
Data Transfer to a Destination Device
The input controller 104 first receives a request from the requestor device to transfer data from memory to a destination device. Either a single or multiple data packets 132 can be transferred from one or more memory devices 108 to one or more destination devices 112. The input controller 104 first informs the output controller 110 via connector 120 that a request has been made to retrieve data from memory, and then sends the starting address in memory of the requested data. The procedure is similar to the input operation described above.
If a request is made to retrieve a data packet 132 from the memory module 108 whereby the data packet is stored in 16 memory blocks DAT0-DAT15, then the output controller 110 will first read the DAT0 which includes the next address NXT=Addr0 pointing to DAT1. DAT1 includes a pointer to the next address NXT=Addr1, DAT2 includes a pointer to the NXT=Addr2, etc. until the complete data packet 132 is reassembled. After reassembly the output controller 110 transfers the reassembled data packet 132 via connector 126 to the destination device 132 as shown in
Further detail of the memory block allocation operation is apparent in view of
The memory within the memory module 108 is formatted into memory blocks 240 which are individually labeled in
In
In this example, the first free memory block address listed in memory block or BDP 220 is address MBAddrO (corresponding to address 222-1 in
One embodiment of a computer memory allocation method can be viewed in conjunction with above description including the drawings and the hardware based memory allocation system 100 of
Each of the memory module 108, input controller 104, output controller 110 and block allocator 106 are hardware devices located within a computer system. The plurality of MB addresses of the BDP are assigned to free memory blocks in different memory channels in the memory module 108. The request for transferring data to the memory module is received by the input controller 104 which, in turn, notifies the block allocator 106 of the transfer request. The block allocator 106 sends one or more FL addresses of the BDI to the input controller 104. The data packet or other information to be transferred and received from the source 102 is then transferred via the input controller from the source 102 to the memory module 108 via the plurality of MB addresses associated with the BDP and the associated one or more FL addresses.
The input controller 104 transfers the data packet from the source 102 to the memory module 108, each MB address used for the transfer including a pointer to a next free memory block of the plurality of MB addresses until a final pointer designates a last block of the data packet being transferred.
Another embodiment of a computer memory allocation method includes the step of receiving, via the input controller, a request for transferring data from the memory module 108 to a destination 112 and notifying the output controller 110 of the request. The output controller 110 reads the memory blocks of the data packet to be read in the memory module 108, reassembles the data packet to be read when received from the read memory blocks, transfers the reassembled data packet to the destination 112, and sends the MB addresses of the transferred data packet to the block allocator 106, wherein the block allocator will add the MB addresses of the transferred data packet to the BDI of FL addresses. Alternately, the output controller 110 sends the MB addresses of the transferred data packet to the input controller 104 and sends a pointer indexing the MB addresses of the transferred data packet to the block allocator 108. Each memory block of the data packet to be read includes a pointer to a next memory block, until a final pointer designates a last memory block of the data packet being read.
While the invention has been shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention.
