Hardware implementation of network testing and performance monitoring in a network device

Abstract

An embodiment of the present invention offloads the generation and monitoring of test packets from a Central processing Unit (CPU) to a dedicated network integrated circuit, such as a router, bridge or switch chip associated with the CPU. The CPU may download test routines and test data to the network IC, which then generates the test packets, identifies and handles received test packets, collects test statistics, and performs other test functions all without loading the CPU. The CPU may be notified when certain events occur, such as when throughput or jitter thresholds for the network are exceeded.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the nature and advantages of the present invention may be realized by reference to the following drawings. In the appended figures, similar components or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.

FIG. 1 is a simplified block diagram illustrating an apparatus and its components providing functionality according to various embodiments of the present invention.

FIG. 2 is a simplified high-level block diagram illustrating the ingress control pipe functionality according to various embodiments of the present invention.

FIG. 3 is a simplified block diagram illustrating the packet generation functionality of an apparatus according to various embodiments of the present invention.

FIG. 4 is a simplified block diagram illustrating the packet reception and response functionality of an apparatus according to various embodiments of the present invention.

FIG. 5 is a simplified block diagram illustrating the response packet generation reception functionality of an apparatus according to various embodiments of the present invention.

FIGS. 6A-6D are simplified block diagrams providing exemplary illustrations of path testing achieved according to various embodiments of the present invention.

FIG. 7A is a flowchart illustrating the packet generation functionality according to various embodiments of the present invention.

FIG. 7B is a flowchart illustrating the packet monitoring functionality according to various embodiments of the present invention.

FIG. 8 is a flowchart illustrating an alternative aspect of the packet generation functionality according to various embodiments of the present invention.

FIG. 9 is a flowchart illustrating the packet reception and response functionality according to various embodiments of the present invention.

FIG. 10 is a flowchart illustrating a system of test packet generation and monitoring according to various embodiments of the present invention.

Claims

1. A method of generating payload data for a plurality of test packets to be transmitted by an integrated circuit, the method comprising: planting a set of data to a buffer allocated to supply payload data for the plurality of test packets;reading the planted set of data from the buffer for use as payload data in a first test packet;reading the planted set of data from the buffer for use as payload data in a second test packet;processing a plurality of data packets received by the integrated circuit to determine forwarding information for the plurality of data packets; andtransmitting the first test packet, the second test packet, and one or more data packets of the plurality out of the integrated circuit directed to a network.

2. The method of claim 1, further comprising: generating the first test packet in response to a received packet identified as an incoming test packet, wherein the planted set of data does not comprise the payload of the incoming test packet.

3. The method of claim 2, further comprising: generating the second test packet in response to the incoming test packet.

4. The method of claim 2, wherein, the generating step is performed without loading a Central Processing Unit (CPU) coupled with the integrated circuit and configured to download test parameters for the integrated circuit.

5. The method of claim 1, further comprising: receiving a response packet, which comprises information from the first test packet and additional information from a node which the first test packet passed through in the network; andstoring information from the response packet in the integrated circuit without loading a Central Processing Unit (CPU) coupled with the integrated circuit and configured to download test parameters for the integrated circuit.

6. The method of claim 5, further comprising: appending a first timestamp to the first test packet before it is transmitted out of the integrated circuit; andassociating a second timestamp with the response packet after it is received at the integrated circuit, wherein the response packet includes information comprising the first timestamp.

7. The method of claim 5, wherein the additional information includes a timestamp from the node.

8. The method of claim 1, further comprising: allocating a plurality of buffers as buffers to be read from to generate a payload for each test packet, wherein the buffer comprises a buffer of the plurality.

9. The method of claim 8, further comprising: generating a plurality of additional test packets each with payload read from the buffer, wherein each of at least a subset of the plurality comprise a different sequence number;transmitting the plurality of additional test packets out of the integrated circuit; andreceiving a plurality of additional response packets which are generated external to the integrated circuit, and in response to the plurality of additional test packets which were transmitted out of the integrated circuit.

10. The method of claim 9, further comprising: measuring jitter and packet loss based on the plurality of additional response packets received without loading a Central Processing Unit (CPU) coupled with the integrated circuit and configured to download test parameters for the integrated circuit; andreporting to the CPU when specified jitter and packet loss metrics are measured.

11. The method of claim 1, further comprising: randomizing the set of data after it is read from the buffer, for use as payload data in a third test packet; andmodifying the set of data after it is read from the buffer, for use as payload data in a fourth test packet.

12. The method of claim 11, further comprising: reading the set of data from the buffer for subsequent test packets without depleting additional buffer resources.

13. The method of claim 1, wherein the planting of the set of data in the buffer is initiated by instructions executed by a Central Processing Unit (CPU), and wherein the reading steps, the processing step, and the transmitting step are each executed without loading the CPU.

14. The method of claim 1, wherein the test packet and response packet comprise a frame from a protocol selected from the group consisting of Internet Protocol, Medium Access Control, Internet Control Message Protocol, Real-Time Transport Protocol, Transmission Control Protocol, and User Datagram Protocol.

15. The method of claim 1, wherein the plurality of data packets received each comprise a header.

16. A method of receiving a test packet at a network device, the method comprising: parsing a header of each of a plurality of data packets received at a network device;filtering a subset of the parsed headers based on identification of each as a test packet header;storing information from each filtered header; andprocessing unfiltered headers to determine forwarding information for data packets associated with the unfiltered headers.

17. The method of claim 16, further comprising: releasing buffers storing payload data from each filtered header.

18. The method of claim 16, further comprising: transmitting a test packet from the network device directed at a network,wherein one or more of the filtered headers comprise headers of response packets triggered by the test packet at a node in the network.

19. The method of claim 16, further comprising: generating a response packet triggered by one or more filtered headers.

20. The method of claim 16, further comprising: generating a plurality of response packets based on a filtered header, the generating step triggered by the identification of the filtered header as a test packet header.

21. The method of claim 20, wherein each test packet of the plurality comprises a different timestamp and different sequence number.

22. The method of claim 16, further comprising: associating a first timestamp with a filtered header after entry to the network device; andappending a egress timestamp to a responsive test packet triggered by the filtered header, wherein the responsive test packet includes information comprising the first timestamp.

23. The method of claim 16, further comprising: monitoring a communication path associated with one or more of the filtered headers; andsending failure notification when information stored from one or more of the filtered headers indicates failure on the communication path.

24. An apparatus for test packet generation from a single integrated circuit configured to forward network traffic, the apparatus comprising: a memory access unit configured to plant a set of data to a buffer allocated to supply payload data for a plurality of test packets;a test packet generator coupled with one or more egress ports, the test packet generator configured to: read the planted set of data from the buffer for use as payload data in a first test packet;read the planted set of data from the buffer for use as payload data in a second test packet; andgenerate a first header for the first test packet and a second header for the second test packet;a forwarding engine coupled with an ingress port and the one or more egress ports, and configured to process a plurality of received data packets comprising the network traffic to determine forwarding information for the plurality of received data packets; anda transmit unit configured to transmit the first test packet, the second test packet, and the network traffic through at least one of the one or more egress ports and directed at a network.

25. The apparatus of claim 24, further comprising: a test packet monitor coupled with the ingress port, and configured to identify a received data packet as an incoming test packet,wherein the test packet generator is further configured to generate the first test packet in response to the incoming test packet, and the planted set of data does not comprise the payload of the incoming test packet.

26. The apparatus of claim 25, wherein, the test packet generator is further configured to generate the second test packet in response to the incoming test packet.

27. The apparatus of claim 25, further comprising: a Central Processing Unit (CPU) coupled with the integrated circuit and configured to download test parameters for the integrated circuit,wherein the test packet monitor further comprises a Ternary Content Addressable Memory (TCAM) used to identify a received data packet as an incoming test packet.

28. The apparatus of claim 24, further comprising: a test packet monitor coupled with the ingress port, and configured to receive a response packet comprising information from the first test packet and additional information from a node which the first test packet passed through in the network; anda control unit configured to store information from the response packet in the integrated circuit without loading a Central Processing Unit (CPU) coupled with the integrated circuit and configured to download test parameters for the integrated circuit.

29. The apparatus of claim 28, wherein, the test packet generator is further configured to append a first timestamp to the first test packet before it is transmitted out of the integrated circuit; andthe control unit is further configured to associate a second timestamp with the response packet after it is received at the integrated circuit, wherein the response packet includes information comprising the first timestamp.

30. The apparatus of claim 28, wherein the additional information includes a timestamp from the node.

31. The apparatus of claim 24, wherein, the control unit is further configured to allocate a plurality of buffers as buffers to be read from to generate a payload for each test packet, wherein the buffer comprises a buffer of the plurality.

32. The apparatus of claim 31, wherein, the test packet generator is further configured to generate a plurality of additional test packets with payload read from the buffer, wherein each of at least a subset of the plurality comprise a different sequence number;the transmit unit is further configured to transmit the plurality of additional test packets out of the integrated circuit; andthe apparatus further comprises a test packet monitor configured to identify a plurality of additional response packets which are generated external to the integrated circuit, and in response to the plurality of additional test packets which were transmitted out of the integrated circuit.

33. The apparatus of claim 32, wherein said test packet monitor further comprises a test traffic termination/monitoring component configured to measure jitter and packet loss based on the plurality of additional response packets received without loading a Central Processing Unit (CPU) coupled with the integrated circuit and configured to download test parameters for the integrated circuit; andreport to the CPU when specified jitter and packet loss metrics are measured.

34. The apparatus of claim 24, wherein, the test packet generator is further configured to: generate a first plurality of additional test packets of variable size at random time intervals; andgenerate a second plurality of additional test packets of predefined size at regular intervals,wherein the set of data in the buffer is to be read and modified in generating a payload for each additional test packet.

35. The apparatus of claim 34, wherein, the test packet generator is further configured to read the set of data from the buffer for subsequent test packets without depleting additional buffer resources.

36. The apparatus of claim 24, wherein the apparatus is further coupled with an external Central Processing Unit (CPU) configured to provide the set of data for the buffer, wherein the test packet generator, the forwarding engine, and the transmit unit are configured to execute the read, generate, process, and transmit functions without loading the CPU.

37. The apparatus of claim 24, wherein the first test packet and second test packet comprise a frame from a protocol selected from the group consisting of Internet Protocol, Medium Access Control, Internet Control Message Protocol, Real-Time Transport Protocol, Transmission Control Protocol, and User Datagram Protocol.

38. The apparatus of claim 24, wherein the plurality of data packets received each comprise a header.

39. An apparatus for test packet monitoring from a single integrated circuit configured to forward network traffic, the apparatus comprising: an ingress port configured to receive a plurality of data packets;a test packet monitor coupled with the ingress port, the test packet monitor configured to filter a subset of the plurality of data packets based on an identification as test packets;a forwarding engine coupled with the ingress port and an egress port, and configured to process unfiltered data packets to determine forwarding information for the unfiltered data packets;a control unit configured to store information from each of the filtered data packets; anda transmit unit configured to one or more unfiltered data packets of the plurality through the egress port.

40. The apparatus of claim 39, further comprising: a memory access unit configured to release buffers storing payload data from each of the filtered packets.

41. The apparatus of claim 39, wherein, the transmit unit is configured to transmit a test packet through the egress port directed at a network; andone or more of the filtered data packets comprise response packets triggered by the test packet at a node in the network.

42. The apparatus of claim 39, further comprising a test packet generator coupled with the test packet monitor and the egress port, the test packet generator configured to generate a response packet triggered by one or more of the filtered data packets.

43. The apparatus of claim 39, further comprising a test packet generator coupled with the test packet monitor and the egress port, the test packet generator configured to generate a plurality of responsive test packets triggered by the identification of the filtered data packets as test packets.

44. The apparatus of claim 43, wherein, each response packet of the plurality comprises a different timestamp and different sequence number.

45. The apparatus of claim 39, wherein, the control unit is further configured to: associate a first timestamp with a filtered data packet after entry to the network device; andappend an egress timestamp to a response packet triggered by the filtered header, wherein the response packet includes information comprising the first timestamp.

46. The apparatus of claim 39, wherein the test packet monitor is further configured to notify a Central Processing Unit (CPU) coupled with the apparatus if a filtered data packet indicates failure on a monitored communication path.