Claims
- 1. An integrated circuit for implementing the secure hash algorithm, comprising:
a data path configured to process an input message pursuant to the secure algorithm; and a controller configured to control operation of the data path; wherein the data path and the controller are implemented using hardware components.
- 2. The integrated circuit of claim 1 wherein the hardware components used to implement the data path and the controller are reconfigurable.
- 3. The integrated circuit of claim 1 wherein the controller further includes an address control module and a finite state machine; and
wherein the finite state machine and the address control module cooperate with each other to provide a physical memory address and control bits, the physical memory address and the controls are used to control operation of the data path.
- 4. The integrated circuit of claim 3 wherein the address control module further includes:
a pico code memory configured to store a plurality of pico codes; wherein each pico code is designed to generate the control bits that are used to control the operation of the data path; and wherein information from each pico code is used to generate a physical memory address for accessing a memory configured to store a plurality of variables that are used to carry out the secure hash algorithm.
- 5. The integrated circuit of claim 4 wherein the plurality of variables include a plurality of longwords, a plurality of intermediate variables, a plurality of initialization constants, and a plurality of processing constants.
- 6. A communication device having the integrated circuit of claim 1.
- 7. An integrated circuit for implementing the secure hash algorithm, comprising:
a data path circuit comprising:
a memory configured to store a plurality of variables that are used to carry out the secure hash algorithm; a first multiplexor coupled to the memory; a first register coupled to the first multiplexor; a shifter coupled to the first register; an arithmetic logic unit coupled to the shifter and the first multiplexor; a second register coupled to the arithmetic logic unit; and a second multiplexor coupled to the second register, the memory and the arithmetic logic unit; and a controller configured to control operation of the data path circuit, comprising:
an address control module; and a finite state machine operable in conjunction with the address control module to generate a physical memory address for accessing the memory and a plurality of control bits, the physical memory address and the plurality of control bits are used to control operation of the data path circuit.
- 8. The integrated circuit of claim 7 wherein the data path circuit and the controller are each implemented using reconfigurable hardware components.
- 9. The integrated circuit of claim 7 wherein the address control module further includes:
a pico code memory configured to store a plurality of pico codes; wherein each pico code is designed to generate the plurality of control bits that are used to control the operation of the data path circuit; and wherein information from each pico code is used to generate the physical memory address for accessing the memory.
- 10. The integrated circuit of claim 7 wherein the plurality of variables include a plurality of longwords, a plurality of intermediate variables, a plurality of initialization constants, and a plurality of processing constants.
- 11. A communication device having the integrated circuit of claim 7.
CROSS-REFERENCES TO RELATED APPLICATION(S)
[0001] The present application is a continuation-in-part application of U.S. patent application Ser. No. 09/815,122 entitled “ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS,” filed on Mar. 22, 2001, the disclosure of which is hereby incorporated by reference in their entirety as if set forth in full herein for all purposes.
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
09815122 |
Mar 2001 |
US |
Child |
10093156 |
Mar 2002 |
US |