Patent Application
20230112720
Direct memory access (DMA) is used to transfer data directly without intervention of a central processing unit (CPU) core. In order for this transfer to function correctly, DMA channels need to be properly configured prior to the data transfer.
Typically, when a protocol is applied to the input data, software running on the CPU parses the protocol's headers, extracts the payload of the input data, transcodes the data, performs any necessary data manipulation, and transfers the input data to the proper location within the destination memory.
The length or quantity of the input data is typically not known in advance to the software, so the software must parse it, typically in an interrupt request (IRQ) routine, and then setup and execute the job accordingly.
This process of parsing, transcoding, and data manipulation requires numerous interactions between the hardware physical interface and the software. This requires real-time handling of the data, consumes CPU processing time, and requires the use of a large hardware first-in first-out (FIFO) memory in order to maintain the physical interface data flow without losing data.
Overview
In an implementation, a hardware direct memory access controller is provided. The hardware direct memory access controller includes an input port configured to receive data from an electronic device for direct memory access, an output port configured to provide data for direct memory access transfer, and processing circuitry coupled with the input port and output port.
The processing circuitry is configured to receive data comprising a header and payload from the electronic device via the input port, parse the header to determine data parameters including a transaction length and an input data format, and select a target destination for the data based at least in part on the data parameters.
The processing circuitry is also configured to allocate memory within the target destination based at least in part on the transaction length, and to format the payload for direct memory access based at least in part on the data parameters. The processing circuitry is further configured to transfer the formatted payload for storage within the allocated memory within the target destination via the output port using direct memory access.
In another implementation, a method for operating a hardware direct memory access controller is provides. The method includes receiving data comprising a header and payload from an electronic device via an input port, parsing the header to determine data parameters including a transaction length and an input data format, and selecting a target destination for the data based at least in part on the data parameters.
The method further includes allocating memory within the target destination based at least in part on the transaction length, formatting the payload for direct memory access based at least in part on the data parameters, and transferring the formatted payload for storage within the allocated memory within the target destination via an output port using direct memory access.
In a further implementation, an electronic device is provided. The electronic device includes an input/output port configured to transfer data between the electronic device and an external electronic device, a memory configured to store data received from the external electronic device, and a hardware direct memory access controller coupled with the input/output port and the memory.
The hardware direct memory access controller is configured to receive data comprising a header and payload from the external electronic device via the input/output port, parse the header to determine data parameters including a transaction length and an input data format, and to select a target destination within the memory for the data based at least in part on the data parameters.
The hardware direct memory access controller is further configured to allocate memory within the target destination based at least in part on the transaction length, format the payload for direct memory access based at least in part on the data parameters, and to transfer the formatted payload for storage within the memory via the input/output port using direct memory access.
Many aspects of the disclosure can be better understood with reference to the following drawings. While several implementations are described in connection with these drawings, the disclosure is not limited to the implementations disclosed herein. On the contrary, the intent is to cover all alternatives, modifications, and equivalents.
In current complex electronic devices such as a system on a chip (SoC) device, a microcontroller (MCU) is used to manage any direct memory access (DMA) operations within the device. The MCU generates a job descriptor for the DMA operation describing the data payload and the location in memory to store the data in a storage operation, or to read the data in a read operation. A FIFO is used as a jitter buffer between the peripheral and the internal memory accesses.
For transmit operations, the DMA or the MCU copy data to the FIFO and the peripheral copies the data from the FIFO and transfers it over an interface (such as a serial peripheral interface (SPI), secure digital input output (SDIO), universal asynchronous receiver-transmitter (UART), and the like). For receive operations, the peripheral receives data from the interface and stores it in the FIFO. The MCU or DMA module then copy the data to the storage memory. This operation of the FIFO overcomes jitters and allows the MCU or the DMA module to work in intervals.
By transferring the required DMA management operations from the MCU to a dedicated hardware DMA module within the device, the MCU is available to process other instructions not involving the DMA routine, resulting in increased MCU efficiency.
In this example embodiment, microcontroller 130, hardware DMA controller 140, serial interface 150, RAM memory 160, and bus 121 comprise system on a chip (SoC) 120. In this example embodiment, serial interface 150 further comprises a transmit FIFO 152 and a receive FIFO 154.
Serial interface 150 communicates with the host microcontroller 110 over physical interface 122. Microcontroller 130, hardware DMA controller 140, serial interface 150 and RAM memory 160 communicate with each other over bus 121. In this example embodiment, modules coupled with bus 121 are initiator or target modules. Initiator modules are nodes on the bus that are capable of initiating transactions. Microcontroller 130 is an initiator, while serial interface 150 is a target. This means that microcontroller 130 is able to access serial interface 150 and read or write data to and from it.
Hardware DMA controller 140 operates as both an initiator and a target. It operates as a target to allow microcontroller 130 to control and set jobs, and operates as an initiator in order to read data from the receive FIFO 154 within serial interface 150 and to copy that data to RAM memory 160. It also operates as an initiator in order to read data from RAM memory 160 and to copy that data into the transmit FIFO 152 within serial interface 150.
Note that
In this example embodiment, hardware DMA controller 140 performs on-the-fly DMA transaction data parsing and execution without the need for direct control from microcontroller 130. When hardware DMA controller 140 receives input data from serial interface 150, it parses a header of the input data to detect the transaction length and data format, sets the target destination within RAM memory 160, allocates space within the correct memory pool within RAM memory 160, performs any necessary bit swizzling and transcoding of the input data.
These operations within hardware DMA controller 140 eliminates the need for pre-defined configurations, reduces MCU processing requirements and its associated software footprint, eliminates redundant software allocation, and avoids any possibility of a FIFO overflow.
In this example embodiment, hardware DMA controller 140 is configured to perform peripheral-to-memory, memory-to-peripheral, and memory-to-memory DMA transactions.
In operation, system on a chip receives input data comprising a header and payload from host microcontroller 110 over physical interface 122. Physical interface 122 comprises any of a wide variety of data interfaces including, but not limited to, serial peripheral interface (SPI), secure digital input output (SDIO), universal asynchronous receiver-transmitter (UART), and the like. The input physical data format is often unknown to system on a chip 120 prior to receiving the data. Hardware DMA controller 140 determines which format the input data comprises from a list of possible physical data formats to be received.
Once the physical data format is determined, hardware DMA controller 140 parses the header of the input data to determine correct data parameters for use in storing the data in RAM memory 160. For example, hardware DMA controller 140 determines the transaction length, or quantity of data to be stored, and the digital format of the input data.
Based upon the header, hardware DMA controller 140 determines a target destination for the data. Hardware DMA controller 140 allocates memory within the target destination based on the data parameters extracted from the header of the input data.
These data parameters include the data format, quantity of data, and the like. Hardware DMA controller 140 determines where to store the data within the target destination based at least in part on these data parameters. Memory allocation includes selecting between memory partitions within the target destination where the memory is partitioned according to data type.
Hardware DMA controller 140 then determines any bit swizzling necessary or data transcoding required before the data is stored in RAM memory 160, and performs the required bit swizzling and/or data transcoding on the payload.
Bit swizzling is a term or art, particularly within computer graphics, used to describe the process of composing vectors by arbitrarily rearranging and combining components of other vectors. Transcoding is also a term of art used to describe the process of converting data from one data format to another.
Data formatting, bit swizzling, and transcoding are done on the fly by hardware DMA controller 140 so that hardware DMA controller 140 transfers the formatted payload for storage within the allocated memory within the target destination via an output port using direct memory access, while still receiving, formatting, bit swizzling, and transcoding incoming data. These data formatting, bit swizzling, and transcoding operations are typically performed on a per word basis, 32 or 64 bits at a time.
I/O Port 222 communicates with the host 230 over physical interface 242. I/O port 222 exchanges data with hardware DMA controller 220 over link 241, and hardware DMA controller 220 exchanges transcoded data with memory 224 over link 240. Hardware DMA controller 220 also provides a data format to network processor/MCU 226 over link 243.
Note that
In this example embodiment, hardware DMA controller 220 performs on-the-fly DMA transaction data parsing and execution without the need for direct control from network processor/MCU 226. When hardware DMA controller 220 receives input data from I/O port 222, it parses a header of the input data to detect the transaction length and data format, sets the target destination within memory 224, allocates space within the correct memory pool within memory 224, performs any necessary bit swizzling and transcoding of the input data, and optionally performs an enhanced scatter-gather mode for data fragmentation and aggregation.
These operations within hardware DMA controller 220 eliminates the need for pre-defined configurations, reduces MCU processing requirements and its associated software footprint, eliminates redundant software allocation, and avoids any possibility of a FIFO overflow.
In this example embodiment, hardware DMA controller 220 is configured to perform peripheral-to-memory, memory-to-peripheral, and memory-to-memory DMA transactions.
In operation, electronic device 210 receives input data comprising a header and payload from host 230 over physical interface 242. Physical interface 242 comprises any of a wide variety of data interfaces including, but not limited to, serial peripheral interface (SPI), secure digital input output (SDIO), universal asynchronous receiver-transmitter (UART), and the like. The input physical data format is often unknown to electronic device 210 prior to receiving the data. Hardware DMA controller 220 determines which format the input data comprises from a list of possible physical data formats to be received.
Once the physical data format is determined, hardware DMA controller 220 parses the header of the input data to determine correct data parameters for use in storing the data in memory 224. For example, hardware DMA controller 220 determines the transaction length, or quantity of data to be stored, and the digital format of the input data.
Based upon the header, hardware DMA controller 220 determines a target destination for the data. This target destination may be memory 224, an external memory (not illustrated), an external device linked via Wi-Fi antenna 228, or the like. Hardware DMA controller 220 allocates memory within the target destination based on the data parameters extracted from the header of the input data.
These data parameters include the data format, quantity of data, and the like. Hardware DMA controller 220 determines where to store the data within the target destination based at least in part on these data parameters. Memory allocation includes selecting between memory partitions within the target destination where the memory is partitioned according to data type. Optionally, hardware DMA controller 220 performs data aggregation when receiving data from a memory and data fragmentation when allocating data to the memory. In some example embodiments of the present invention, this aggregation and fragmentation is executed as a scatter-gather mode for interfacing with the target destination.
Hardware DMA controller 220 then determines any bit swizzling necessary or data transcoding required before the data is stored in memory 224, and performs the required bit swizzling and/or data transcoding on the payload.
Bit swizzling is a term or art, particularly within computer graphics, used to describe the process of composing vectors by arbitrarily rearranging and combining components of other vectors. Transcoding is also a term of art used to describe the process of converting data from one data format to another.
Data formatting, bit swizzling, and transcoding are done on the fly by hardware DMA controller 220 so that hardware DMA controller 220 transfers the formatted payload for storage within the allocated memory within the target destination via an output port using direct memory access, while still receiving, formatting, bit swizzling, and transcoding incoming data. These data formatting, bit swizzling, and transcoding operations are typically performed on a per word basis, 32 or 64 bits at a time.
In this example embodiment, header processing module 344 and data processing modules 346-352 are instruction modules configured to direct processing circuitry within hardware DMA controller 340 to operate as described herein. Some data processing modules 346-352 are optional and are not used in every DMA operation performed by hardware DMA controller 340.
Header parsing module 344 directs processing circuitry within hardware DMA controller 340 to parse the header 342 of the input data to determine correct data parameters for use in storing the data in memory 360. For example, header parsing module 344 determines the transaction length, or quantity of data to be stored, and the digital format of the input data.
Based at least in part on the data parameters determined by header parsing module 344, hardware DMA controller 340 determines any bit swizzling necessary or data transcoding required before the data is stored in memory 360, and performs the required bit swizzling and/or data transcoding on the payload.
Bit swizzling is a term or art, particularly within computer graphics, describing the process of composing vectors by arbitrarily rearranging and combining components of other vectors. Transcoding is also a term of art describing the process of converting data from one data format to another.
As needed, data bit swizzling module 346 directs processing circuitry within hardware DMA controller 340 to perform the necessary bit swizzling. Also as needed, data transcoding module 348 directs processing circuitry within hardware DMA controller 340 to perform the necessary data transcoding. Data aggregation module 350 directs processing circuitry within hardware DMA controller 340 to perform any necessary data aggregation in any type of scatter-gather memory operation. Data fragmentation module 352 directs processing circuitry within hardware DMA controller 340 to perform any necessary data fragmentation in any type of scatter-gather memory operation.
Once the payload is properly formatted for storage, hardware DMA controller 340 transfers the formatted payload for storage within the allocated memory within the target destination 360 via an output port using direct memory access.
In this example, data within the payload may be in either a big-endian or little-endian format.
For data of short length, the data [0xAABB] is stored in memory location order [AA], [BB], as big-endian 406 data, while the same data is stored in memory location order [BB], [AA], as little endian-data 408. Similarly, for data of long length, the data [0xAABBCCDD] is stored in memory location order [AA], [BB], [CC], [DD], as big-endian 410 data, while the same data is stored in memory location order [DD], [CC], [BB], [AA], as little-endian 412 data.
Hardware DMA controller 340 to formats data between the big-endian format and the little-endian format as necessary based on the format of the input data and the format of data within memory 360.
In this example embodiment, hardware DMA controller 340 receives data comprising a header and payload from an electronic device 310 via an input port, (operation 500). Hardware DMA controller 340 parses the header to determine data parameters including transaction length and input data format, (operation 502)
Hardware DMA controller 340 selects a target destination 360 for the data based at least in part on the data parameters, (operation 504). Hardware DMA controller 340 allocates memory within the target destination 360 for the data, (operation 506).
Hardware DMA controller 340 formats the payload for direct memory access based at least in part on the data parameters, (operation 508). In an example embodiment, this format operation is performed on a chunk or word basis and is repeated until the entire payload has been received. Hardware DMA controller 340 then transfers the formatted payload for storage within the allocated memory within the target destination 360 via the output port using direct memory access, (operation 510). In an example embodiment, this transfer operation is also performed on a chunk or word basis and is repeated until the entire payload has been stored.
In this example embodiment, hardware DMA controller 600 comprises input port 610, processing circuitry 620, output port 630, and internal storage system 640. In one example configuration, input port 610 comprises circuitry configured to receive input data from an electronic device 310 for storage in a memory. Output port 630 comprises circuitry configured to send data and commands to a storage system or memory 360. In some embodiments, input port 610 and output port 630 are combined into a single input/output (I/O) port.
Processing circuitry 620 comprises electronic circuitry configured to perform the tasks of a hardware DMA controller 340 as described above. Processing circuitry 620 may be embedded in a complex electronic device 320 in some embodiments. Examples of processing circuitry 620 include general purpose central processing units, application specific processors, and logic devices, as well as any other type of processing device, combinations, or variations thereof. Processing circuitry 620 can be implemented within a single processing device but can also be distributed across multiple processing devices or sub-systems that cooperate in executing program instructions.
In an example embodiment, hardware DMA controller 600 is implemented as an application specific module and custom processing circuitry 620 is provided to perform the functions described herein via one or more hardware modules including header parsing module 621, data bit swizzling module 622, data transcoding module 623, data aggregation module 624, data fragmentation module 625, and memory allocation module 626.
Internal storage system 640 comprises any non-transitory computer readable storage media capable of storing data. Internal storage system 640 also includes various data structures 650 which comprise one or more databases, tables, lists, or other data structures, including a list of physical data formats, digital data formats, data buffers, and the like used by processing circuitry 620. Internal storage system 640 can include volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data.
Internal storage system 640 can be implemented as a single storage device but can also be implemented across multiple storage devices, sub-systems, or modules co-located or distributed relative to each other. Internal storage system 640 can comprise additional elements, such as a controller capable of communicating with processing circuitry 620. Examples of storage media include random access memory, read only memory, magnetic disks, optical disks, flash memory, virtual memory and non-virtual memory, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and that can be accessed by an instruction execution system, as well as any combination or variation thereof.
In this example embodiment, internal storage system 640 also includes one or more FIFOs 660, such as Tx FIFO 152, and Rx FIFO 154 from
Header processing module 621 within processing circuitry 620 parses the data header in order to determine data parameters including transaction length and input data format. Data bit swizzling module 622 within processing circuitry 620 performs any required data bit swizzling. Data transcoding module 623 within processing circuitry 620 performs any required data transcoding. In some examples, data transcoding module 623 also performs any data formatting, such as illustrated in
Data aggregation module 624 within processing circuitry 620 performs any required data aggregation in scatter-gather type modes. For example, data aggregation module 624 performs data aggregation on a plurality of data payloads.
Data fragmentation module 625 within processing circuitry 620 performs any required data fragmentation in scatter-gather type modes. For example, data fragmentation module 665 performs data fragmentation on the payload, by partitioning the payload in to a plurality of data partitions, processing each data partition separately, allocating a plurality of memory locations within the target destination corresponding to the plurality of data partitions, and storing each of the plurality of data partitions in one of the plurality of memory locations.
Memory allocation module 626 within processing circuitry 620 allocates memory for storage of the data.
The included descriptions and figures depict specific embodiments to teach those skilled in the art how to make and use the best mode. For the purpose of teaching inventive principles, some conventional aspects have been simplified or omitted. Those skilled in the art will appreciate variations from these embodiments that fall within the scope of the invention. Those skilled in the art will also appreciate that the features described above may be combined in various ways to form multiple embodiments. As a result, the invention is not limited to the specific embodiments described above, but only by the claims and their equivalents.
