Harmonic boost signals in up/down direct/super heterodyne conversions for advanced receiver/transmitter architecture

Abstract

A harmonic boosting technique for achieving higher overall system performance is described here. The technique is applicable to devices such as converter, combiner, synthesizer, and voltage control oscillator. A converter has anti-parallel diode pair (hereafter called APDP) cell or a modified Gilbert cell circuit for mixing an input signal with local oscillator (hereinafter called LO). A combiner has a combining circuit to combine even harmonics from LO. A synthesizer has a digitally synthesized network or a multiplier circuit for producing the even harmonics. A voltage control oscillator (hereafter called VCO) has a voltage control circuit for generating very low base frequencies.

Description

TECHNICAL FIELD OF THE INVENTION

[0002] The present invention relates to harmonic boosting techniques affecting the design and the performance of converters, combiners or adders, synthesizers or frequency multipliers, and voltage control oscillators. Such harmonic boosting techniques are useful in communications applications including wireless, satellite, radar, microwave, and radio systems. More specifically, the present invention relates to harmonic boosting techniques especially useful in reducing power consumption during boosting output signals while maintaining a high degree of linearity and low interior interference.

BACKGROUND OF THE INVENTION

[0003] With the tremendous growth of wireless communication industry, and migration to higher frequency and bandwidth, the need for better high frequency mixing techniques continues to grow significantly. As a result, sub-harmonic mixing techniques, which historically have been used for millimeter-wave applications, are no longer strangers to mainstream wireless applications such as cell phone and wireless local area network (WLAN) systems. Sub-harmonic passive mixers that exhibit excellent linearity performance are becoming even more attractive for the next generation wireless hardware. However, the difficulty of integrating passive mixers on chip remains in the requirement of high LO (local oscillator) power, which leads to significant problems through radiation and substrate coupling and increases the power consumption of the LO buffers.

[0004] Currently, most communications and semiconductor companies have concentrated on the development of System On Chip (SOC) technology. However, SOC technology presents severe challenges in the area of heat dissipation and interior interference and manufacture process. Traditionally, up and down converters require the presence of a high frequency LO and synthesizer. Once a high frequency LO and synthesizer are introduced to the up and down converters, the associated parasitic capacitance and inductance causes increased power leakage which in turn leads to higher interior interference. Hence, the implementation of the SOC paradigm becomes more difficult.

[0005] In past years, harmonic implementations have focused on second sub-harmonic operations in the converters. However, there is a need for a harmonic boosting technique that uses multiple sub-harmonics with the inherent advantage of lower LO power and frequency. As a result, high frequency circuits causing coupling and matching issues are eliminated. In the meantime, the present invention allows interior interference to be reduced.

SUMMARY OF THE INVENTION

[0006] The present invention demonstrates a harmonic boosting technique capable of reducing a LO power and frequency, thus providing one solution for achieving SOC chipset commercialization. SOC systems that use the harmonic boosting technique of the present invention have lower overall cost, internal interference, power consumption, while providing high linearity and compact benefits. Further, the present invention provides lower frequency operation devices including a converter, a combiner, a synthesizer and a VCO.

[0007] The present invention achieves this by providing circuits for different chipset applications with the harmonic boosting technique requirements described as follows.

[0008] This technique improves the implementation of SOC technology by providing a solution to current bottlenecks within the SOC process. Using the technique of the present invention, the RF subsystem will operate with a lower noise figure as well as lower overall power consumption. This is particularly useful in internet edge devices and wireless devices such as, but not limited to, current and future communications systems using GSM, GPRS, CDMA2000, WCDMA, DCS, and Blue Tooth, etc.

[0009] In one embodiment for a SOC chipset or a board-level application for transceivers, the harmonic boosting technique includes a voltage controlled oscillator (VCO). The VCO generates outputs:

[0010] LOnr=a receiving RF/2n; or

[0011] LOnt=a transmitting RF/2n, where n=1, 2, 3, 4 . . .

[0012] A digital synthesizer or frequency multiplier device receives the output signal of the VCO and produces signals of two sets of output signals at n sub-output ports. These signals are LO1r, LO2r . . . LOnr at the first set of sub-output ports, and LO1t, LO2t . . . LOnt; at the second;

[0013] LO1r=a receiving RF/2;

[0014] LOnr=LO1r/n;

[0015] LO1t=a transmitting RF/2; and

[0016] LOnt=LO1t/n.

[0017] A combiner or adder that combines these output signals with inputs having frequencies LO1r, LO2r . . . LOnr and LO1t, LO2t . . . LOnt, to generate the combiner's or adder's two outputs, LOr for a down converter input and LOt for up converter input. An anti-parallel diode pair (APDP) circuit, a modified Gilbert circuit, or other like circuit as known to those skilled in the art may be used as the down converter. This APDP or modified Gilbert circuit, mixes an RF signal with the LOr to produce a zero-IF or an IF signal. An APDP circuit, modified Gilbert cell, or other like circuit as known to those skilled in the art may also be used as the up converter to take a zero-IF signal or an IF signal with the LOt output to produce a transmitting RF output signal.

[0018] Additionally, other embodiments of the harmonic boosting technique may be constructed from a series of discrete devices in a transceiver for a board-level product or implementation. Here the functions are divided among a series of discrete devices, for example, the VCO circuit may be one discrete device that generates a frequency output. This frequency output which may include a received RF signal divided by 2n, LOnr or a transmitted RF signal divided by 2n, LOnt or both LOnr and LOnt. A discrete digital synthesizer or frequency multiplier device receives the VCO output and produces two sets of output signals that include n frequencies LO1r, LO2r LOnr in the first set, and LO1t, LO2t . . . LOnt in the second set from an input comprising a frequency LOnr or LOnt, where n=1, 2, 3, 4 . . . These two sets of signals are provided as the input to a discrete combiner or adder device. The combiner or adder, as stated previously, combines the two sets of outputs from the digital synthesizer or frequency multiplier device to create a LOr output for a down converter LO frequency and an LOL output frequency for a up converter LO frequency.

[0019] An APDP cell, a modified Gilbert cell, or other like circuit as is known to those skilled in the art, forms part of the down converter device with a combiner or adder.

[0020] Similarly, the up converter circuit includes an APDP cell, modified Gilbert cell, or other like circuit as is known to those skilled in the art, and a combiner or adder.

[0021] Another embodiment for a digital synthesizer or frequency multiplier device, the digital synthesizer or frequency multiplier circuits include a digital synthesizer or frequency multiplier generating two sets of n outputs that include frequencies LO1r, LO2r . . . LOnr and frequencies LO1t, LO2t . . . LOnt that are provided to an integrated combiner or adder as inputs. The combiner or adder portion of the discrete device combines the inputs having frequency which include LO1r, LO2r . . . LOnr and LO1t, LO2t . . . LOnt frequencies, where n=1, 2, 3, 4 . . . , to generate an LOr output for a down converter LO frequency and an LOt output frequency for a up converter LO frequency.

[0022] In another embodiment for a digital synthesizer or frequency multiplier device, the digital synthesizer or frequency multiplier circuits include a VCO circuit that generates an output that includes frequencies of a receiver RF divided by 2n, LOnr or a transmitting RF divided 2n, LOnt or both LOnr and LOnt, where n=1, 2, 3, 4 . . . This output is provided as the input to an integrated digital synthesizer or frequency multiplier. The digital synthesizer or frequency multiplier generating two sets of outputs that include n frequencies: LOr, LO2r . . . LOnr and LO1t, LO2t . . . LOnt. These signals are provided to the integrated combiner or adder as inputs wherein the combiner or adder combines the n frequency inputs a LOr output for a down converter LO frequency and an LOt output frequency for a up converter LO frequency.

BRIEF DESCRIPTION OF THE DRAWINGS

[0023] For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numerals indicate like features and wherein:

[0024] FIG. 1 is a schematic diagram of preferred embodiment of the present invention configured as a harmonic boosting technique for a SOC chipset or a board-level application for transceiver;

[0025] FIG. 2 depicts a schematic diagram of a voltage control oscillator (VCO) used to implement the harmonic boosting technique of the present invention;

[0026] FIG. 3 depicts a schematic diagram of a digital synthesizer or frequency multiplier used to implement the harmonic boosting technique implemented of the present invention;

[0027] FIG. 4 is a schematic diagram of a combiner or an adder used to implement the harmonic boosting technique of the present invention;

[0028] FIG. 5 provides a schematic diagram of a digital synthesizer or frequency multiplier used to implement the harmonic boosting technique implemented of the present invention;

[0029] FIG. 6 is a schematic diagram of a digital synthesizer or frequency multiplier used to implement the harmonic boosting technique implemented of the present invention;

[0030] FIG. 7 provides a schematic diagram of a down converter used to implement the harmonic boosting technique of the present invention;

[0031] FIG. 8 illustrates a schematic diagram of an up converter used to implement the harmonic boosting technique of the present invention;

[0032] FIG. 9 provides an illustration of a schematic diagram of the APDP harmonic down-conversion mixer, for the receiving mixer basis;

[0033] FIG. 10 provides an illustration of a schematic diagram of the APDP harmonic up-conversion mixer, for the transmitting mixer basis;

[0034] FIG. 11 provides a schematic diagram of the modified Gilbert cell down-conversion mixer, for the receiving mixer basis;

[0035] FIG. 12 provides a schematic diagram of the modified Gilbert cell up-conversion mixer, for the transmitting mixer basis.

DETAILED DESCRIPTION OF THE INVENTION

[0036] Preferred embodiments of the present invention are illustrated in the Figures, like numerals being used to refer to like and corresponding parts of the various drawings.

[0037] Although the present invention is described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as described by the appended claims.

[0038] Referring to the figures in which like numerals refer to like positions thereof, FIG. 1 provides a circuit block diagram configured to implement a harmonic boosting technique for a SOC chipset or a board-level application for transceivers. VCO 110 generates output signals, LOnr=a receiving RF/2n; or LOnt=a transmitting RF/2n, where n=1, 2, 3, 4 . . . at output port 112. This output is provided to digital synthesizer or frequency multiplier 120 through input port 122. Digital synthesizer or a frequency multiplier circuit 120 has two sets of n sub-output ports. The first set of outputs are from port LO1r 124, from port LO2r 126, and from port LOnr . . . 128. The second set of n sub-output ports are LO1t from port 121, LO2t from port 123, and LOnt from port 125, where: n =1, 2, 3, 4 . . . .

[0039] The following definitions are provided for those signals:

[0040] LO1r=a receiving RF/2;

[0041] LOnr=LO1r/n;

[0042] LO1t=a transmitting RF/2;

[0043] LOnt=LO1t/n.

[0044] The signals from the two sets of n sub-ports are provided as inputs to combiner or adder circuit 130. The inputs are received at input port 134 as signal LO1r, port 136 as signal LO2r, port 138 as signal LOnr, port 131 as signal LO1t, port 133 as signal LO2t, and port 135 as signal LOnt. Circuit 130 combines the two n frequencies inputs together to create outputs 132 (LOr) for a down converter input and 137 (LOt) for up converter input. An APDP circuit, a modified Gilbert circuit, or other like circuit as known to those skilled in the art, in down converter 140, mixes a received RF signal with LOr 144 to produce a zero-IF or an IF signal 146. An APDP circuit, modified Gilbert cell, or other like circuit as known to those skilled in the art, in up converter 150 mixes a zero-IF signal an IF signal 156 with LOt 154 to produce transmitted RF output signal 152.

[0045] The present invention need not be limited to a SOC implementation. The harmonic boosting technique may also be implemented by discreted devices in a transceiver for board-level products.

[0046] FIG. 2 functionally depicts a discrete VCO device 200 which generates output 212. Output 212 includes a frequency output which is a received RF divided by 2n, LOnr or a transmitted RF divided 2n, LO1t or both LOnr and LOnt.

[0047] A discrete FIG. 3 functionally depicts digital synthesizer or frequency multiplier device 300 which receives the output of the VCO device 200 shown in FIG. 2 to produce an output that includes two sets of n frequency signals at output ports 324 (LO1r), 326 (LO2r) . . . 328 (LOnr) and port 321 (LO1t), 323 (LO2t) . . . 325 (LOnt) from input LOnr or LOnt, where n=1, 2, 3, 4 . . . .

[0048] FIG. 4 functionally depicts a combiner or adder circuit 400 which combines inputs from digital synthesizer or frequency multiplier device 300. These inputs signals are shown at input ports 434 (LO1r), 436 (LO2r) . . . 438 (LOnr) and 431 (LO1t), 433 (LO2t) 435 (LOnt) where n=1, 2, 3, 4 . . . . Combiner or adder circuit 400 produces an output (LOr) at port 432 for a down converter LO frequency and an output (LOt) at port 437 for an up converter LO frequency.

[0049] FIG. 5 depicts a single discrete board level component 500, which combines digital synthesizer or frequency multiplier circuits 520 of FIG. 3 and combiner or adder 530 of FIG. 4. This device functions similarly to the description of FIGS. 3 and 4. Digital synthesizer or frequency multiplier 520 generates a frequency output LO1r at port 524, LO2r at port 526, LOnr at port 528, and frequency outputs LO1t, LO2t, . . . LOnt at ports 521, 523, and . . . 525, respectively, as combiner or adder inputs. Adder or combiner 530 is incorporated into one discrete device 500 and receives frequency inputs and (LO1r), (LO2r), (LOnr), (LO1t), (LO2t) (LOnt), from ports 534, 536, 538, 531, 533, and 535, respectively, where n=1, 2, 3, 4 . . . to produce output LOr at output 532 for a down converter LO frequency and output LOt at port 537 for a up converter LO frequency.

[0050] FIG. 6 depicts yet another discrete device that combines the VCO device of FIG. 2, digital synthesizer of frequency multiplier device of FIG. 3, and combiner or adder of FIG. 4, into one discrete device 600. These devices function identically to the previous descriptions in FIGS. 2, 3, and 4. VCO circuit 610 generates an output LOnt or LOnr 612, which is provided to the digital synthesizer or frequency multiplier input 622. Digital synthesizer or frequency multiplier 620 generates outputs LO1r, LO2r, LOnr and LO1t LO2t LOnt at ports 624, 626, 628, 621, 623, and 625, respectively. These outputs are received by combiner or adder ports 634, 636, 638, 631, 633, and 635, to generate output LOr at port 632 for a down converter LO frequency and output LOt at port 637 for an up converter LO frequency.

[0051] The down converter is functionally depicted as a discrete device 700 shown in FIG. 7. This circuit includes an APDP cell, a modified Gilbert cell, or other like circuit known to those skilled in the art, circuit 740 comprising LO input port 744 for signal LO1r, RF input port 742, and zero-IF or IF output port 746. Combiner or adder 730 has a n frequency inputs from input ports 734 for signal LO1r, 736 for signal LO2r . . . and 738 for signal LOnr, and a output port 732 for signal LOr, where n=1, 2, 3, 4 . . . and LOr=a receiving RF/2 and LOnr=LO1r/n.

[0052] FIG. 8 functionally depicts a discrete up converter device. Up converter circuit 800 includes an APDP cell or a modified Gilbert cell circuit 840 comprising LO input port 844 for signal LOt and RF output port 846 and zero-IF and IF input port 846. Combiner or adder 830 has n frequencies inputs LO1t LO2t, . . . LOnt, at ports 834, 836, and 838, respectively, where n=1, 2, 3, 4 . . . and LO1t=a receiving RF/2 and LOnt=LO1t/n.

[0053] Measurements indicate performance having very high IIP2 (more than 50 dBM) and IIP3 (more than 20 dBM), high dynamic range (more than 95 dB), and reducing conversion loss 6 dB as well.

[0054] An APDP harmonic down-conversion mixer, a modified Gilbert cell down-conversion mixer, may be used to generate a harmonic signal in the receiving path. An APDP harmonic up-conversion mixer, or a modified Gilbert cell up-conversion mixer also may be utilized to generate a harmonic signal in the transmitting path.

[0055] A nonlinear device, such as active/passive device, transistors (or tubes)/diodes, has a voltage transfer function that could be written as a Taylor series as follows: 1$\begin{array}{cc}{v}_{\mathrm{out}}=a_0+a_1{v}_{\mathrm{in}}+a_2{v}_{\mathrm{in}}^2+a_3{v}_{\mathrm{in}}^3+a_4{v}_{\mathrm{in}}^4+a_5{v}_{\mathrm{in}}^5+\dots .& \left(1\right)\end{array}$

[0056] The aivini into a same bandwidth via a up/down conversion mixers generating, with a local oscillator (LO) frequency 2$\frac{1}{i}{f}_{\mathrm{LO}}^i.$

[0057] An adder sums up the signals in the system, which are boosted to generate the desired signal. Here, the i is 1, 2, 3, 4, 5 . . . , n and so on. The desired signal S can be indicated as following. 3$\begin{array}{cc}S=\sum _0^n{a}_i{v}_{\mathrm{in}}^i\mathrm{in}a\mathrm{same}\mathrm{intermodulation}/\mathrm{analog}\mathrm{baseband}& \left(2\right)\end{array}$

[0058] Basically, the up/down conversion mixer, with a local oscillator frequency 4$\frac{1}{i}{f}_{\mathrm{LO}}^i,$

[0059] converts the fundamental frequency and the harmonic to one IF/Analog/RF baseband. Then, these are summed to become the boosted to the desired signal strength as shown in equation 2. The embodiment depicted in FIG. 9 includes a passive mixer, anti-parallel diode pair (APDP) harmonic mixer or active mixer, modified Gilbert cell mixer. A schematic diagram of the APDP harmonic down-conversion mixer 900, for the receiving mixer basis, again is illustrated in FIG. 9. This Figure depicts a high pass filter 910 which receives input fRF. Low pass filter 920 receives input 5$\frac{1}{i}{f}_{\mathrm{LO}}^i$

[0060] 922 . High pass filter 910 and low pass filter 920 are connected to APDP 930. Output fABB/1F is provided at ports 926 and 936 and is defined as: 6$\begin{array}{cc}{f}_{\mathrm{ABB}/1F}=f_{\mathrm{RF}}-i\frac{1}{i}{f}_{\mathrm{LO}}^i& \end{array}$

[0061] A schematic diagram of the APDP harmonic up-conversion mixer 1000, for the transmitting mixer basis, is illustrated in FIG. 10. This circuit is similar in construction as that of FIG. 9. However, the arrangement of the high and low pass filters are reversed. High pass filter 1020 receives input 7$\frac{1}{i}{f}_{\mathrm{LO}}^i$

[0062] 1022 . Low pass filter 1010 receives input fABB/IF. 1012 The generated output is fRF at points 1026 and 1036. and is defined as: 8$f_{\mathrm{RF}}=f_{\mathrm{ABB}/1F}+i\frac{1}{i}{f}_{\mathrm{LO}}^i$

[0063] FIG. 11 provides a schematic diagram of the modified Gilbert cell down-conversion mixer 1100. The modified Gilbert cell down-conversion mixer 1100 receives input fRF at ports 1106 and 1108, and receives input 9$\frac{1}{i}{f}_{\mathrm{LO}}^i$

[0064] at ports 1102 and 1104. Output fABB/1F is provided at ports 1101 and 1103 and is defined as: 10$f_{\mathrm{ABB}/1F}=f_{\mathrm{RF}}-i\frac{1}{i}{f}_{\mathrm{LO}}^i$

[0065] FIG. 12 provides a schematic diagram of the modified Gilbert cell up-conversion mixer. The modified Gilbert cell up-conversion mixer 1200 receives input fABB/1F at ports 1206 and 1208 and receives input 11$\frac{1}{i}{f}_{\mathrm{LO}}^i$

[0066] at ports 1202 and 1204. Output fRF is provided at ports 1201 and 1203 and is defined as: 12$f_{\mathrm{RF}}=f_{\frac{\mathrm{ABB}}{1F}}+i\frac{1}{i}{f}_{\mathrm{LO}}^i$

[0067] The present invention provides many advantages. A desired signal in the system architecture of the present invention, is a product of harmonic signals, summed from harmonic signals. There are several significant advantages to this architecture. First, the present invention allows for lower power consumption. Harmonic signals boost the desired signal strength. This means a decrease in amplifier number, and a gain value in each amplifier stage as well. This is especially true in the case involving high power amplifier within a transmitter. Thus, the APDP mixer dose not require the current consumption levels of other solutions seen during no signal intervals.

[0068] The present invention also provides an improved Noise Figure. Converting the harmonic signals into the desired signal reduces the system noise figure.

[0069] Additionally, the present invention provides a higher voltage gain as the desired signals are summed from each harmonic.

[0070] Since most of the internal components are diodes, the device may be easily miniaturized and manufactured using CMOS technology as an integrated SOC. Alternatively, the present invention may use discrete board level components to implement the method of the present invention.

[0071] In summary, the present invention provides a harmonic boosting technique for achieving higher overall system performance. The technique may be applied using discrete devices such as converter, combiner, synthesizer, and voltage control oscillator. A converter uses an anti-parallel diode pair cell or a modified Gilbert cell circuit to combine or mix an input signal with local oscillator (hereinafter called LO). A combiner uses combining circuitry to combine harmonics from the LO. A synthesizer, using a digitally synthesized network or a multiplier circuit, produces the harmonics. A voltage control oscillator with a voltage control circuit generates very low base frequencies.

[0072] The present invention demonstrates that harmonic boosting technique can reduce LO power and frequency thus providing necessary solutions for achieving SOC chipset commercialization. In addition to the compact size, the SOC process using this technique has lower cost, lower internal interference, lower power consumption and high lineraity.

[0073] Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as described by the appended claims.

Claims

1. A harmonic boosting technique that uses reduced LO power and frequency, comprising the steps of: generating an output with a voltage controlled oscillator (VCO), wherein the outputs comprise LOnr or LOnt, and wherein the outputs are received by a digital synthesizer or frequency multiplier device; producing two sets of output signals for the digital synthesizer or frequency multiplier device at n sub-output ports; combining these two sets of output signals with an input in a combiner or adder circuit to generate a first input for a down converter and a second input for an up converter; mixing a received RF signal with the first input with the down converter to produce a zero-IF or an IF signal; and mixing a zero-IF signal or an IF signal with the second input within the up converter to produce a transmitting RF output signal.

2. The method of claim 1, wherein LOnr is equal to LO1r/n and LO1r is equal to a receiving RF; and wherein LOnt is equal to LO1t/n and LO1t is equal to a transmitting RF/2.

3. The method of claim 1, wherein the two sets of output signals comprise: LO1r, LO2r . . . LOnr at a first set of sub-output ports; and LO1t, LO2t . . . LOnt where n 1, 2, 3, 4 . . . ; at a second set of sub-output ports.

4. The method of claim 1, wherein the inputs have frequencies LO1r, LO2r . . . LOnr and LO1t, LO2t . . . LOnt.

5. The method of claim 1, wherein said first input is LOr and said second input is LOt.

6. The method of claim 1, wherein said down converter comprises an anti-parallel diode pair circuit or a modified Gilbert circuit.

7. The method of claim 1, wherein said down converter comprises an anti-parallel diode pair circuit or a modified Gilbert circuit.

8. The method of claim 1, wherein said steps are executed by circuits within a single CMOS or SiBiCMOS chip.

9. The method of claim 1, wherein said steps are executed by discrete devices mounted on a circuit board.

10. An apparatus to harmonically boost signals in order to reduce LO power and frequency, comprising: a voltage controlled oscillator (VCO) which generates outputs LOnr or LOnt; a digital synthesizer or frequency multiplier device that receives outputs LOnr or LOnt from the voltage controlled oscillator and produces two sets of output signals at n sub-output ports; a combiner or adder circuit that combines these two sets of output signals with an input to generate a first input for a down converter and a second input for an up converter; a RF signal which is mixed with the first input in the down converter to produce a zero-IF or an IF signal; and a transmitting RF output signal produced by mixing the zero-IF signal or IF signal with the second input within the up converter.

11. The apparatus of claim 10, wherein LOnr is equal to LO1r/n and LO1r is equal to a receiving RF/2; and Wherein LOnt is equal to LO1t/n and LO1t is equal to a transmitting RF/2.

12. The apparatus of claim 10, wherein the two sets of output signals comprise: LO1r, LO2r . . . LOnr at a first set of sub-output ports; and LO1t, LO2t . . . LOnt where n=1, 2, 3, 4 . . . ; at a second set of sub-output ports.

13. The apparatus of claim 10, wherein the inputs have frequencies LO1r, LO2r . . . LOnr and LO1t, LO2t . . . LOnt.

14. The apparatus of claim 10, wherein said first input is LOr and said second input is LOt.

15. The apparatus of claim 10, wherein said down converter comprises an anti-parallel diode pair circuit or a modified Gilbert circuit.

16. The apparatus of claim 10, wherein said down converter comprises an anti-parallel diode pair circuit or a modified Gilbert circuit.

17. The apparatus of claim 10, wherein said steps are executed by circuits comprising a System on Chip.

18. The apparatus of claim 10, wherein said steps are executed by discrete devices mounted on a circuit board.

19. The apparatus of 18, wherein said voltage control oscillator comprises a discrete board level component.

20. The apparatus of 18, wherein said digital synthesizer or frequency multiplier device comprise a discrete board level component.