Patent Grant
7388959
This invention relates to the field of electronic amplifiers and more particularly to the field of signal conditioning circuits used in audio amplifiers for the purpose of reproducing music and delivering it to a speaker or other reproduction means.
This application provides information that relates to and extends the subject mater found in Ser. No. 08/377,903 filed Jan. 24, 1995 for “A LOW INPUT SIGNAL BANDWIDTH COMPRESSOR AND AMPLIFIER CONTROL CIRCUIT” which issued on Apr. 23, 1996 as U.S. Pat. No. 5,510,752; and, to Ser. No. 09/636,168 filed Apr. 22, 1996 for “A LOW INPUT SIGNAL BANDWIDTH COMPRESSOR AND AMPLIFIER CONTROL CIRCUIT WITH A STATE VARIABLE PRE-AMPLIFIER” which issued on Apr. 7, 1998 as U.S. Pat. No. 5,736,897”; and, Ser. No. 09/444,541 filed Nov. 22, 1999 for “AN AUDIO BOOST CIRCUT”, all of which have a common inventor and assignee. Each of the applications mentioned herein are incorporated herein by reference in their entirety.
The above referenced issued U.S. Pat. No. 5,736,897 shows a state-variable filter used as a Pre-Amplifier that receives an input program signal and processes the input program signal to provide three band-pass signals comprising a low band-pass signal (LFRCMIPS), a mid-range band pass signal (MFRCMIPS) and a high band-pass signal (HFRCMIPS) to respective inputs of a summing amplifier. The three signal components are then summed and output as a compensated signal at its output. The ‘897’ Patent then shows the compensated signal being processed by a “Compander” Circuit first introduced in the above referenced U.S. Pat. No. 5,510,752. Application Ser. No. 09/444,541 referenced above shows the compensated signal at the output of the state-variable filter driving an audio boost circuit.
The compensated signal is free of harmonic distortion in each of the above mentioned topologies. A determination has been made that some applications benefit from the introduction of a predetermined amount of harmonic distortion into the compensated signal out of the pre amplifier. This application provides an initial input amplifier that receives the program signal and provides a buffered program signal. The buffered program signal is sampled by a Harmonic Generator circuit. The Harmonic Generator circuit then generates a family of harmonic signals that are summed with the buffered program signal for cumulative processing by the state variable filter to provide a composite compensated signal having a predetermined component of harmonics.
The above-noted problems, and others, are overcome in accordance with this invention using a Harmonic Generator for audio applications and a Pre-Amplifier circuit formed from a Buffer Circuit coupled to an IPS (input program signal) for buffering the input program signal to provide a BIPS (Buffered Input Program Signal). The buffer circuit provides a BIPS (Buffered Input Program Signal) to the Modulator and to the Summer. The Modulator is a circuit that is coupled to receive the buffered input program signal. The Modulator generates harmonics in response to changes in amplitude of the BIPS to provide a MIPS (Modulated Input Program Signal. The Summer circuit adds the BIPS (buffered input program signal) and the MIPS (Modulated Input Program Signal) to provide a CMIPS (Composite Modulated Input Program Signal). The Pre-Amplifier is coupled to be receive the CMIPS and to provide a COS (Compensated Output Signal) that includes harmonics generated by the Harmonic Generator circuit.
Details of the invention, and of preferred embodiments thereof, will be further understood upon reference to the drawing, wherein:
a and 4b are schematic block diagrams of an embodiment using signal processing software and or hardware to perform the function of the Harmonic Generator and Pre-Amplifier Circuit.
A Modulator Circuit 22 receives the BIPS at the Modulator Circuit Input terminal 24 and adds harmonics to the content of the BIPS. The Modulator Circuit 22 provides the modified BIPS as the MBIPS (Modulated Buffered Input Program Signal) at the Modulator Circuit Output Terminal 26.
A Summing Circuit 28 adds the BIPS at the Summing Circuit First input 30 and the MBIPS at Summing Circuit Second Input 32 to provide a CMIPS (Composite Modulated Input Program Signal) at the Summing Circuit Output 34.
The Pre-Amplifier 14 is coupled to receive the CMIPS at the Pre-Amplifier Input 36. The Pre-Amplifier 14 amplifies and conditions the CMIPS and outputs a COS (Composite Operating Signal) at the Pre-Amplifier Output 39.
The Pre-Amplifier 14 is further characterized in
The Pre-Amplifier 14 also includes a State-Variable Summing Amplifier 52 coupled to add the LFRCMIPS, the MFRCMIPS, and the HFRCMIPS signal components at State-Variable Summing Amplifier First, Second and Third Inputs 54, 56 and 58 respectively, to provide the COS at the Pre-Amplifier Output 39.
The Harmonic Generator Circuit
The Modulator Circuit 22 has a third resistor 82 that has a first end 84 coupled to the amplifier output terminal 62, and to the first feedback resistor first terminal 72. A second end 86 is connected to the common connection of anode 88 of a first diode D1 and the cathode 90 of a second diode D2. The first and second diodes D1, D2, each have a respective and opposed common cathode 92 and anode 94 coupled to ground. The connection formed by the connection of the third resistor second end 86 with the respective common anode and cathode of the first diode D1 and second diode D2 is the Modulator Output Terminal 26. The second feedback resistor 76 is manually adjusted in value to change the amplitude and the harmonic content of the MBIPS (Modulated Buffered Input Program Signal) present at the Modulator Output Terminal 26.
The Summing Circuit 28 has an operational amplifier 96 that has an inverting input 98, a non-inverting input 100 coupled to ground and an output terminal 102. A first input resistor 104, a second input resistor 106 and a feedback resistor 108 are used in the Summing Circuit 28. Each of the three resistors has a respective first end and a second end. The Summing Circuit First Input 30 is connected to the first end of the first input resistor 104. The Summing Circuit Second Input 32 is connected to the first end of the second input resistor 106. The first end of the feedback resistor 108 is connected to the Summing Circuit 28 Output Terminal 34. The second end of the first input resistor 104, the second end of the second input resistor 106 and the second end of the feedback resistor 108 are each connected to the operational amplifier inverting input 98. The operational amplifier output terminal 102 is connected to the Summing Circuit Output Terminal 34 where it outputs the analog sum of the BIPS and the MBIPS signals as the CMIPS.
The Harmonic Generator circuit 12 receives an IPS (input Program Signal) at INPUT terminal 18 from a signal source such as a CD Player, magnetic read head or a stylus on a turn table (not shown). The IPS is connected to the input of the Buffer Circuit 16 via an input decoupling capacitor 134 and resistor 136. The capacitor 134 blocks any dc component on the IPS signal input from reaching non-inverting input of operational amplifier 138.
The IPS is reproduced as the BIPS (Buffered Input Program Signal) at the Buffer Circuit output 20. The BIPS is also coupled to the Modulator Circuit 22 Input 24. The Modulator Circuit 22 responds to the BIPS and generates harmonics in the BIPS to provide the MBIPS (Modulated Buffered Input Program Signal) at the Modulator Output 26.
In some alternative embodiments, resistor 76 may be a selected value resistor might be used. The first feedback resistor 70 is shown as a fixed value feedback resistor. In other embodiments, the values of both resistors 76 and 70 are adjusted to control the positive, non-inverting gain of the amplifier. If resistor 70 is designated R70 and resistor 76 is designated R76, the gain of the amplifier stage can be shown to be approximately (R70+R76)/R76. R70 is the value of the first feedback resistor 70 and R76 is the adjusted value of the second feedback resistor 76. It should be noted that the gain of the stage increases without limit as the value of resistor 76 is adjusted to a value approaching zero. It is therefore good practice to interpose a fixed resistor having a predetermined value in series with resistor 76 to limit the maximum gain of the stage in the event that resistor 76 is inadvertently adjusted to zero. The minimum gain of the stage is two as resistor 76 is adjusted to 10K if resistor 70 also has a value of 10K ohms
In operation, the series divider formed by resistors 70 and variable resistor 76 samples the buffered program IPS from the amplifier output 62. While operating in its linear range, operational amplifier 60 has an open loop gain in the hundreds of thousands, and provides an output voltage at amplifier output 62 that is sufficient to drive the voltage difference between amplifier inputs at 66 and 64 to virtually zero. Since the voltage at non-inverting input 66 is the BIPS signal level and since the amplifier will force the voltage at the inverting input 64 to be virtually equal to the voltage at the non-inverting input 66, the voltage at the operational amplifier's output 62 will be virtually equal to the voltage at the non-inverting input 66 but amplified by a factor of (R70+R76)/R76.
The output of amplifier 60 at output 62 drives the third resistor 82 which is followed by the anti-parallel or back-to-back diode clamping circuit of D1 and D2. The voltage across the diodes is an exponential relationship that depends oil the value of the forward bias current at any instant in time. At low volume, the forward bias currents are limited to levels below hard clamping. The circuit of D1 and D2 diodes operate to generate non-linear effects or harmonics as the forward bias currents passing through them is increased. The harmonics are then added back into the program signal by the Summing Circuit 28 to form the CMIPS (Composite Modulated Input Program Signal). The CMIPS is then coupled to the input of a Pre-Amplifier 14 which includes the combination of the All-Pass State-Variable Filter 40 with the State Variable Summing Amplifier 52 as shown in
There is a practical limit for the operation of the back to back diode clamp of D1 and D2. As the volume or amplitude of the IPS drops to a limit at which the output is difficult to hear as an output from an audio system, the importance of the modulation diminishes due to the reduced audibility of the information from the speaker or other reproduction device.
In operation, within the circuit 22, diodes D1 and D2 are typically biased past their initial point of conduction well into their nonlinear conduction range. Both forward and backward conduction is present accompanied by clamping above and below ground in response to the alternating BIPS signal driving resistor 82 to force alternating currents through the back to back diodes D1 and D2. Operation of the diodes in their initial turn on or conduction range is low at very low levels of output volume.
As the amplitude of the input signal drops to a point at which the diodes are only lightly forward biased, the result on the output is minimal. Anything above the 0.6 V across either diode produces sufficient harmonics to be of interest. Resistor R76 is adjusted to increase the gain of amplifier thereby increasing the level of the drive voltage applied to the current limiting resistor R82 at node 84 for a given level of the BIPS signal. As the diodes are driven harder into conduction, the level of harmonic richness is increased.
The clamping function of the anti-parallel diodes D1 and D2 limits the amplitude of the signal voltage that can be obtained at the Modulator Output Terminal 26 to a peak to peak value under +/−700 mV. The clamping circuit of D1 and D2 uses the third resistor 82 to limit the current through diodes D1 and D2 as each diode is driven into partial conduction as the signal voltage swings above and below ground.
R76 is typically adjusted to cause the BIPS driving R82 to have an amplitude sufficient to drive enough current through the diodes D1 and D2 to cause the forward voltage drop across each to exceed 0.6 volt. This adjustment insures the production of a CMIPS signal that is sufficiently rich in harmonics to produce the desired effect for the amplifier and speaker system that is being used. Resistor 106 is adjusted to control the signal level of the harmonics that are actually blended with the BIPS to form an acceptable CMIPS.
In operation, the characteristics of the harmonics change as the music gets louder or softer or as different selections of music are made. A user adjusts resistor 76 and resistor 106 to obtain a preferred response in real time as the music is reproduced by the system and its speaker(s). The adjustment of resistor 76 controls the amount of harmonics that are produced (the amplitude of the MBIPS) for a predetermined amplitude of the BIPS. Resistor 106 controls the amount of the harmonics that are added to the BIPS to form the CMIPS (Composite Modulated Input Program Signal) that is delivered to the input of the Pre-Amplifier within phantom block 14 in
The All-Pass State-Variable Pre-Amplifier
The design of an All-Pass State-Variable Pre-Amplifier 14 composed of the All-Pass Variable Filter 40 and a State-Variable Summing Amplifier 52 is characterized in U.S. Pat. No. 5,736,897 which is referenced above. The ‘897’ patent provides a detailed and design procedure and schematic for the All-Pass State-Variable Pre-Amplifier 14.
Referring now to
In a more detailed embodiment, the All-Pass State Variable Filter 40 in the Pre-Amplifier 14, is further characterized as having a First Integrator 120 having an input 122 coupled to receive the HFRCMIPS from the Input Summing And Damping Amplifier output 116. The First Integrator has an Output 124 that provides the MFRCMIPS to the input 114 of the Input Summing And Damping Amplifier 110.
A Second Integrator 126 has an input 130 that is coupled to receive the MFRCMIPS from the First Integrator Output 124. The Second Integrator 126 also has an Output 132 that outputs the LFRCMIPS onto signal line 50. The State-Variable Summing Amplifier First Input 54 is connected to receive the LFRCMIPS from signal line 50. The Second Input 56 is connected to receive the MFRCMIPS from signal line. 48. The Third Input 58 is connected to receive the HFRCMIPS from signal line 46. The State-Variable Summing Amplifier 52 adds the respective LFRCMIPS, the MFRCMIPS and the HFRCMIPS to provide the State-Variable Summing Amplifier Output 39. The MFRCMIPS is inverted in phase with respect to the HFRCMIPS and the LFRCMIPS signal components due to the inversion of the signals provided by the operational amplifiers used in the All-Pass State Variable Filter 40.
The Input Summing And Damping Amplifier circuit 110 has a portion of the mid-range band-pass signal MFRCMIPS fed to the non-inverting input 142 of amplifier 140 for damping. The output of amplifier 140 is the HFRCMIPS which is coupled to the negative input 144 of a second operational amplifier 146 within First Integrator 120. The first integrator 120 inverts and integrates the HFRCMIPS. The HFRCMIPS is then coupled to the State-Variable Summing Amplifier 52 high pass input 54 via signal line 46.
The first integrator 120 integrates the HFRCMIPS signal to provide the mid-range band-pass signal MFRCMIPS at first integrator output 124. The mid-range band-pass signal MFRCMIPS is fed to the damping input 114 of the Input Summing And Damping Amplifier circuit 110 and to the mid-range band-pass input, the second input, 56 of the Summing Amplifier 52 on signal line 48 and via resistor 116 to the negative input 150 of a third operational amplifier 152 in the Second Integrator 126.
The Second Integrator 126 responds to the mid-range band-pass signal MFRCMIPS on signal line 48 and provides a low band-pass signal LFRCMIPS at the second integrator output terminal 132 to the State-Variable Summing Amplifier 52 low band-pass signal input, the first input, 54 and to the second input 112 of the input Summing And Damping Amplifier Circuit 110 via signal line 50.
The damping circuit of the Input Summing And Damping Amplifier Circuit 110 comprises an input resistor 154 that has a first terminal connected to receive the mid-range band-pass signal at damping input 114. The second terminal of resistor 154 is coupled to the first terminal of resistor 156 and to the non-inverting input of operational amplifier 140. The second terminal of resistor 156 is coupled to a reference ground. The ratio of resistors 154 and 156 establish the “Q” of the state-variable filter. The higher the ratio of the resistors 74 and 76, the higher the Q. The Q of the All-Pass State-Variable Pre-Amplifier 14 of
One of the objectives of the state-variable filter is to set the phase shift and gains up such that the mid-range band-pass frequency signals are about 180 degrees out of phase with the signal components in the lower frequency band and in the higher-frequency band. The ratio of the damping resistors, the gains and break frequencies of the amplifiers and integrator are set for a desired Q and band-pass.
The State-Variable Summing Amplifier 52 has a low frequency band-pass gain adjustment resistor 160, and a high range band-pass frequency gain adjustment pot 162 that permit the user to make a final adjustment for a particular circuit and component configuration. The adjustable inputs to the State-Variable Summing Amplifier 52 permit the user to control the gain for the LFRCMIPS and HFRCMIPS signal.
The circuit of the State Variable Pre-Amp of
The All-Pass State-Variable Pre-Amplifier 14 also provides a time delay that is adjusted to obtain about 2.5 ms time delay at 20 Hz. The 20 Hz components are physically delayed in real time by up to 2.5 ms with respect to the high frequency components. The design objectives for audio applications are taught in U.S. Pat. No. 4,638,258 issued on Jan. 20, 1987 for a Reference Load Amplifier Correction System, to Robert C. Crooks.
Referring again to
Q=(R1+R2)/3R2=0.67 Eq. 1
where R1 is resistor 154 and R2 is resistor 156 in
Viewing the circuit heuristically, the higher reactance of the smaller capacitance for mid-range band-pass amplifier (C1=0.0033 μF), capacitor 122 within the first integrator 120 sets the gain of the amplifier to higher values at lower frequencies than that of the low range band-pass amplifier within the second integrator 126 (capacitance C2=0.033 μF), capacitor 117. It can also be seen that the mid-range band-pass amplifier of first integrator 120 is a single pole filter. The feed back signal MFRCMIPS to the damping resistors results in a controlled Q in the mid-range frequencies band
In general, the Q of a band-pass filter is defined as the bandwidth divided by the center frequency. The design of the state-variable filter of
The object of the design of the All-Pass State-Variable Pre-Amplifier 14 of
fc=½πRC2 Eq. 2
where R and C are the value of resistor 116 and capacitor 117. The high frequency break is set by the
fc=½πRC1 Eq. 3
where the value of R and C1 are those of resistor 121 and capacitor 122.
Once the Q is selected, the ratio of resistor 154 to resistor 156 can be calculated from the equation. In the case of the All-Pass State-Variable Pre-Amplifier of
The Q was then adjusted using the pots for the variable resistors 160 and 162 to provide the best match to the curves in the earlier patent to Crook. The Q and the break points were selected to match the response characteristic of the resulting circuit to the curves in the earlier patent to yield the same phase shifts, time delays and frequency response. The resistors 70 and 76 are set for a gain of nine but a slightly higher gain of 12 would be preferred.
The outputs HFRCMIPS, MFRCMIPS and LFRCMIPS of the state-variable filer 40 represent three independent state variables. The procedure for adjusting the band-pass and gain as proposed in the above referenced text “The Active Filter Handbook” by Frank P. Tedeschi, at pages 178-182 is to set the value of C1 and C2 to be equal and to adjust the ratio of R1 and R2 and to obtain the desired Q. In addition, in the circuit of
a shows a digital signal processing alternative to the analog process of
In the alternative,
In the embodiments of both
While certain specific relationships, materials and other parameters have been detailed in the above description of preferred embodiments, those can be varied, where suitable, with similar results. Other applications, and variation of the present invention will occur to those skilled in the art upon reading the present disclosure. Those variations are also intended to be included within the scope of this invention as defined in the appended claims.
This application claims benefit from and is a non-provisional filing based upon the prior provisional application Ser. No. 60/497,095 filed Aug. 22, 2003.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4638258 | Crooks | Jan 1987 | A |
| 4672671 | Kennedy | Jun 1987 | A |
| 5032796 | Tiers et al. | Jul 1991 | A |
| 5510752 | Gagon | Apr 1996 | A |
| 5736897 | Gagon | Apr 1998 | A |
| 5737432 | Werrbach | Apr 1998 | A |
| 6111961 | Hedrick et al. | Aug 2000 | A |
| 6275593 | Garcia et al. | Aug 2001 | B1 |
| 6845165 | Motohashi et al. | Jan 2005 | B1 |
| 7054455 | Aarts | May 2006 | B2 |
| 20030044023 | Larsen | Mar 2003 | A1 |
| 20030044024 | Aarts et al. | Mar 2003 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20050041821 A1 | Feb 2005 | US |
| Number | Date | Country | |
|---|---|---|---|
| 60497095 | Aug 2003 | US |
