Patent Application
20150288412
The present description relates to an apparatus and a method related to radio transceiver. More particularly, the present description relates to an apparatus and a method related to harmonic rejection mixers in receiver and/or transmitter.
Abbreviations
In receivers and transmitters, the mixer converts signals from/to LO frequency and its harmonics. Typically mixer uses double balanced structure, and therefore, the level of even-order harmonics at mixer output is very low. However, odd order harmonics of LO are not rejected by the double balanced structure. In modern CMOS processes implementing passive mixer topologies require rail-to-rail clocking waveforms of LO with very high harmonic content. The LO harmonic causes several unwanted features in TX and RX as discussed below.
C-IM3 can be generated in such a radio transmitter by two mechanisms (see
The baseband nonlinearity generates third-order harmonic distortion in I/Q path. These BB HD3 signals are directly up-converted by the modulator to C-IM3 frequency (fLO+3fBB), which is at the opposite side of the wanted signal.
2. C-IM3 Due to the Intermodulation between the Wanted Signal and RF HD3:
The modulator outputs the wanted signal (fLO−fBB) as well as RF HD3 (3fLO+fBB) due to LO 3rd-order harmonics. These signals are subjected to nonlinearities of the PGA after the mixer. The 3rd-order intermodulation product between the wanted signal and RF HD3 is then located at (3fLO+fBB)−2(fLO−fBB)=fLO+3fBB.
In addition to C-IM3 problem, harmonic components cause also problems when TX output signal is upconverted to bandwidth where it folds to RX band. An example of this behavior is when TX is transmitting at band 17 then its 3rd harmonic folds to RX band 4 which greatly deteriorates receiver performance.
The latter C-IM3 mechanism is usually overcome using harmonic rejection mixers. Then the 3rd harmonic is rejected (or greatly attenuated in practice) and C-IM3 term does not occur due to LO harmonic. Using these harmonic rejection mixers means that there are separate dedicated mixer cells for each LO phase. Accordingly, the area of the harmonic rejection mixer is significantly larger because of three different mixer cores required to produce harmonic rejection.
In receiver side, the biggest problem due to squarewave LO is the conversion from LO 3rd harmonic to the baseband. The down-converted blocker signal from 3rd harmonic can degrade the signal-to-noise-ratio of the desired signal, or even block the reception altogether via compression or intermodulation.
For example, cellular radio operating around 800 MHz vicinity (e.g. Band 20, DL: 791-821 MHz, marked as LORX, B20) can down-convert signal from 2.4-GHz frequency area where other radios, e.g. WLAN, operates (marked as 2.4 GHz ISM, see
Correspondingly, DLs operating around 1700-1900 MHz range (e.g. Bands 3 and 9) can get corrupted from down-converted 5-GHz WLAN signal.
Thus in both, transmitter and receiver, the LO 3rd harmonic component causes undesired features.
Harmonic rejection mixer principle was proposed by Weldon et al in “A 1.75-GHz Highly Integrated Narrow-Band CMOS Transmitter With Harmonic-Rejection Mixers”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, December 2001. The harmonic rejection is based on the harmonics of square waves. When three ideal square waves are summed (with one of them (f2(t)) scaled by sqrt(2)), the third and fifth harmonics are cancelled. As the summed waveform shows, it is a “reconstruction” of a sinusoidal signal based on square waves.
At
A basic block diagram of traditional H3 rejection mixer is shown on the left side of
One implementation to weight the RF paths is shown on the right side of
In one or all of the paths, a switch (MOSFET) controlled at its gate by the respective LO phase signal may comprise a double-balanced mixer cell, as shown in the insert on the upper right of
Another implementation example of the prior art (according to the basic principle outlined on the left side of
The mixer shown on the left corresponds to the mixers of each path of
On the right side of
Further details, features, objects, and advantages are apparent from the following detailed description of the preferred embodiments of the present invention which is to be taken in conjunction with the appended drawings.
It is an object of the present invention to improve the prior art.
According to a first aspect of the invention, there is provided an apparatus, comprising a local oscillator configured to oscillate at a carrier frequency and having plural output ports, wherein the local oscillator is configured to provide a signal of a respective phase at each of the plural output ports, wherein the respective phases are different from each other; a plurality of branches, wherein each branch corresponds to one of the plural output ports and comprises a mixer unit, wherein, for each branch, the signal of the respective phase is applied to an input port of the mixer unit and the mixer unit is configured to modulate a baseband signal by the signal of the respective phase of the local oscillator to obtain, at its output port, a respective modulated signal and; a combiner configured to add the modulated signals from the branches to obtain a total signal to be output to a load; wherein at least one of the branches comprises a multi-switch, wherein for each of the at least one multi-switches: an output terminal of the multi-switch is connected to the respective input port of the mixer unit, the multi-switch comprises plural input terminals and is configured to connect one of the input terminals to the output terminal and to disconnect the others of the input terminals from the output terminal, and each of the input terminals is connected to one of the output ports of the local oscillator.
According to a second aspect of the invention, there is provided a method applied to a monitored apparatus, wherein the monitored apparatus comprises plural branches and each branch is adapted to modulate a baseband signal with a signal of a local oscillator of a respective phase to obtain a respective modulated signal of the branch and the respective phases are different from each other, a combiner to combine the modulated output signals of the branches into a total signal, and at least one of the branches comprises a weighting means adapted to weight the respective modulated signal, wherein the method comprises detecting if the total signal comprises a frequency component of a frequency different from the carrier frequency with a level higher than a predefined level; adapting, by the weighting means, the modulated signal of the at least one branch comprising the weighting means in order to reduce the level of the frequency component. The method may be a control method. The weighting means may be a weighting element or a weighting circuitry.
According to a third aspect of the invention, there is provided an apparatus, comprising plural branches, wherein each branch is adapted to modulate a baseband signal with a signal of a local oscillator of a respective phase to obtain a respective modulated signal of the branch and the respective phases are different from each other, and at least one of the branches comprises a weighting means adapted to weight the respective modulated signal; a combiner adapted to combine the modulated output signals of the branches into a total signal, a detecting means adapted to detect if the total signal comprises a frequency component of a frequency different from the carrier frequency with a level higher than a predefined level; a control means adapted to control the weighting means in order to reduce the level of the frequency component below the predefined level. The detecting means may be a detector. The control means may be a controller. The weighting means may be a weighting element or a weighting circuitry.
According to a fourth aspect of the invention, there is provided a method applied to an apparatus, wherein the apparatus comprises plural branches, wherein each branch is adapted to modulate a baseband signal with a signal of a local oscillator of a respective phase to obtain a respective modulated signal of the branch and the respective phases are different from each other, and at least one of the branches comprises a weighting means adapted to weight the respective modulated signal; a combiner adapted to combine the modulated output signals of the branches into a total signal, and the method comprises detecting if the total signal comprises a frequency component of a frequency different from the carrier frequency with a level higher than a predefined level; and controlling the weighting means in order to reduce the level of the frequency component below the predefined level. The weighting means may be a weighting element or weighting circuitry.
According to a fifth aspect of the invention, there is provided an apparatus, comprising a plurality of branches, wherein each branch comprises a mixer unit, wherein each of the mixer units is configured to modulate a baseband signal by a signal of a respective phase of a local oscillator; a combiner configured to add the signals from the branches to obtain a total signal to be output to a load; wherein at least one of the branches comprises a gain control transistor, wherein one of a source and a drain of the gain control transistor is connected to the respective mixer unit, and the other of the source and the drain of the gain control transistor is connected to the combiner.
According to some embodiments of the invention, at least one of the following advantages may be achieved:
It is to be understood that any of the above modifications can be applied singly or in combination to the respective aspects to which they refer, unless they are explicitly stated as excluding alternatives.
Herein below, certain embodiments of the present invention are described in detail with reference to the accompanying drawings, wherein the features of the embodiments can be freely combined with each other unless otherwise described. However, it is to be expressly understood that the description of certain embodiments is given for by way of example only, and that it is by no way intended to be understood as limiting the invention to the disclosed details.
Moreover, it is to be understood that a recited apparatus is configured to perform the corresponding method, although in some cases only the apparatus or only the method are described.
A disadvantage of the harmonic rejection mixer shown in
Also, 45-degree phase is always present. In some cases, there may be bands or resource block allocations where extremely good C-IM3 or ISR3 performance is not needed. Thus, the 45-degree LO generation might not be needed. Since the 45-degree path consumes power, in these cases it might be advantageous not to have the 45-degree path.
In
The harmonic rejection mixers comprise three paths. Each path comprises two or three MOSFETs in the sequence Mlo, Mbb and optionally Magc from the voltage terminal Vref to the output terminal I_tot, to which a load (not shown in
The three paths are connected in parallel between the terminals Vref and I_tot.
In each path, Mlo is controlled, at its gate, by a respective phase (e.g. 0°, 45°, or 90°) of LO. Mlo acts as a switch, i.e. the control signal switches Mlo on or off, as indicated by the rectangular control signal in the corresponding inserts. In some embodiments, one or more of the respective phase signal may be enabled or disabled by the signal “en” (e.g.
In each path, Mbb is controlled, at its gate, by BB. Mbb operates in the amplifying (or linear) mode, as shown by the control signal in the corresponding inserts. The BB control signal may be biased.
The signal of the 45° path is enhanced by sqrt(2) compared to the two other paths. This is achieved by a transistor width which is increased by sqrt(2) compared to the corresponding transistor width of the other two paths. In some embodiments, only the width of Mbb of the 45° path is increased by sqrt(2) (e.g. shown in
Magc, if present, is controlled, at its gate, by a binary control signal AGC. Thus, Magc may be switched on or off. During operation, if harmonic rejection is required, Magc is typically switched on.
In
Through the insertion of Magc in one or more of the paths, the isolation between the different Mlo transistors is improved. Thus, harmonic rejection may be increased.
In addition, Magc may be used to adapt the levels of the signals such that harmonic rejection is improved. Since the 0° and 90° path should have the same amplification, if there is a single Magc only, it should be inserted preferably into the 45° path. Correspondingly, if there are two Magc's, they should be inserted preferably into the 0° and 90° paths. Thus, by different amplification factors of the Magc or Magc's, for example, manufacturing tolerances may be compensated.
The combination of Mlo and Mbb in each path may be replaced by one of the other mixer topologies shown in
Note that the harmonic rejection mixers of
Alternatively, each of the paths of any one of the harmonic rejection mixers of
Furthermore, in all of the harmonic rejection mixers of
In case a C-IM3 specification (or another harmonic rejection specification such as H3, H5, ISR3, ISR5) is to be fulfilled in a band without using mixer's C-IM3 rejection property (i.e. a specified maximum level of C-IM3 is not exceeded) but more output power would be required, conventionally more mixer cells in parallel are used.
In the last three combinations, the level of the 0° signal is amplified by 1+sqrt(2), 2, and 2sqrt(2), respectively.
The mixer cells of
The configurable harmonic rejection mixer of
A detailed implementation example of the principle shown in
One, two, or three of the three paths of the harmonic rejection mixer comprise several mixer unit cells in parallel (in
Preferably, all the mixer unit cells are identical. In particular, the transistors of all of the mixer unit cells may have equal widths. If all mixer unit cells are identical, matching will be better. However, in general, the unit cells do not need to be identical.
In embodiments with plural mixer unit cells in at least one path, harmonic rejection dependency on the LO signal's rise/fall time may be rather easily eliminated (see below).
The configurable harmonic rejection mixer with plural mixer unit cells in at least one path suits well for DAC style mixer cells in transmitters.
The number of mixer unit cells in each path may be fixed. Alternatively, the number of unit cells may be switchable. For example, some or all of the mixer unit cells may be switched on/off by an enabling signal which passes or blocks the respective LO phase from the Mlo transistor, as discussed with respect to
A detailed implementation example of the principle shown in
The concepts outlined with respect to
In
In general, in some embodiments, there are at least two mixer unit cells in one of the paths which may be driven by at least two different LO phases. That is, one two or three of the paths may each comprise two or more mixer unit cells which may be driven by two or three different LO phases. In some or all of the paths, each mixer unit cell may be driven by two or three different LO phases.
The mixer unit cells may be identical, or some of them may be different from the others. The number of mixer unit cells in each path may be the same or different from the others. Some or all of the mixer unit cells may be switched on/off, e.g. by an enabling signal.
The unit mixer cells of one path may be controlled by the same LO phase. However, in some embodiments, each of the unit mixer cells of one path may be controlled by its respective phase. In this case, the harmonic rejection mixer may be considered as comprising x+y+z parallel paths each with a single mixer unit cell, wherein x, y, and z are the respective numbers of unit cells in each of the three paths when considered as harmonic rejection mixer.
A detailed implementation example of the principle shown in
From simulations it has been shown that harmonic rejection is dependent on the rise/fall time of the LO-signal especially for a mixer that is shown in
H3 rejection dependency on LO signal's rise/fall time can be understood by investigating LO phases that are shown at
When LO signal phase 0° is active (high), during half of the time it is active (section 1. at the upper part of
Therefore LO-45 mixer core is exhibiting different loading than LO-0 and LO-90 mixer unit cells through common reference point which, in
This is the root cause mechanism why LO signals rise/fall time will also have effect on harmonic rejection because depending on what is the rise/fall time it will change the LO-45 mixer core signal value relative to LO-0/LO-90 mixer cores. This can be seen from the bottom part at
This difference can be compensated e.g. by using a kind of structure that is shown at the
Next, examples of how much harmonic rejection can be achieved by tuning number of active elements are shown for different duty cycles and for 3rd and 5th harmonic in
At
At
At
At
It is also noticed that for duty cycle 50 percent case the optimum values to have 3rd harmonic rejection and for 5th harmonic rejection differ significantly from each other but for duty cycle 25 percent case the optimum values vary much less, so when using duty cycle 25 percent tuning either one of the harmonics will also improve the other one greatly. Also, better rejection is achievable by using duty cycle 50 percent compared to using duty cycle 25 percent but in case of duty cycle 50 percent the wanted signal level is lower. Therefore, the harmonic rejection mixer with duty cycle 25 percent is actually able to produce more signal than that with duty cycle 50 percent, and that is shown at
In detail,
As an alternative, for compensation of the different signals, AGCs with different gains may be used.
Embodiments of the description comprise a method, wherein the level of an unwanted signal component (e.g. H3 or H5) is monitored, and the gain of at least one of the branches of the harmonic rejection mixer is adapted such that the level of the unwanted signal component is reduced.
Also, embodiments of the description comprise an apparatus, comprising a monitoring means (e.g. a monitoring processor) adapted to monitor the level of the unwanted signal component, and a control means (e.g. a control processor) adapted control the gain of at least one of the branches of the harmonic rejection mixer such that the level of the unwanted signal component is reduced.
A feedback loop such as that shown in
For example, if the LO amplitude is 1V and duty-cycle is 50%, the DC term should be 0.5V. But if the monitored DC values is larger than 0.5V, it is noticed that the LO waveform is not a square wave but has finite rise/fall slopes as shown in
By controlling supply voltage of Divider (Vsupply) one may adjust rise/fall times of the LO signal and when this property is combined with duty cycle information that one may have from the low pass filter one may tune LO duty cycle to match wanted value.
Controlling the divider supply voltage leads to another useful property. LO waveform is heavily dependent on process corner and temperature (sharp transitions in cold temperature and in fast process corner). Thus, in fruitful conditions, the LO transitions could be slowed down and still feasible performance could be achieved. That can be achieved by decreasing the supply voltage which also results in current consumption saving. Alternatively, in worse conditions (in hot and slow process corner) there could be a need to sharpen the waveform thus requiring higher supply voltage and increased current consumption. As a result, with DC component monitor, the LO waveform can be made more constant over process and temperature ranges and optimized current consumption is achieved. Thus, “overdesign” can be avoided (design to meet the performance in the worst case conditions.)
LO may generate its frequency (carrier frequency) directly, or by frequency dividing or frequency multiplying of another directly generated signal.
Embodiments of the invention are shown with three paths (0°, 45°, and 90°). However, other embodiments may comprise two paths, or four or more paths with different LO phases applied.
Embodiments of the invention may be employed in senders and/or receivers of network elements of a 3GPP network. They may be employed also in senders and/or receivers of other mobile networks such as CDMA, EDGE, UMTS, LTE, LTE-A, GSM, WLAN networks, etc, and also in other senders and/or receivers. In particular, they may be deployed in a terminal (terminal device, user equipment) of the respective technology which may be e.g. a mobile phone, a smart phone, a PDA, a laptop or any other terminal. Also, they may be deployed in base stations of the respective technology such as eNodeB, NodeB, BTS, Access Point etc.
Names of network elements, protocols, and methods are based on current standards. In other versions or other technologies, the names of these network elements and/or protocols and/or methods may be different, as long as they provide a corresponding functionality.
The figures show logical or functional structures of example embodiments. They are not intended to show an arrangement of the components on a circuit board, substrate, etc. I.e., the arrangement of the components may or may not correspond to the logical or functional structure.
If not otherwise stated or otherwise made clear from the context, the statement that two entities are different means that they perform different functions. It does not necessarily mean that they are based on different hardware. That is, each of the entities described in the present description may be based on a different hardware, or some or all of the entities may be based on the same hardware.
Implementations of any of the above described blocks, apparatuses, systems, techniques or methods include, as non limiting examples, implementations as hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.
Such hardware may be hardware type independent and may be implemented using any known or future developed hardware technology or any hybrids of these, such as MOS (Metal Oxide Semiconductor), CMOS (Complementary MOS), BiMOS (Bipolar MOS), BiCMOS (Bipolar CMOS), ECL (Emitter Coupled Logic), TTL (Transistor-Transistor Logic), etc., using for example ASIC (Application Specific IC (Integrated Circuit)) components, FPGA (Field-programmable Gate Arrays) components, CPLD (Complex Programmable Logic Device) components or DSP (Digital Signal Processor) components. MOS components (e.g. transistors) may be implemented in NMOS or PMOS technology. Different MOS components may be based on the same or different of these technologies.
A device/apparatus may be represented by a semiconductor chip, a chipset, or a (hardware) module comprising such chip or chipset; this, however, does not exclude the possibility that a functionality of a device/apparatus or module, instead of being hardware implemented, be implemented as software in a (software) module such as a computer program or a computer program product comprising executable software code portions for execution/being run on a hardware-based processor. A device may be regarded as a device/apparatus or as an assembly of more than one device/apparatus, whether functionally in cooperation with each other or functionally independently of each other. The components of a device may be in a same device housing or in different device housings.
For example, method steps may be implemented in software, firmware, or hardware, in the latter case using any known or future developed hardware technology or any hybrids of these, as described hereinabove. The method steps may be implemented in a mixture of software, firmware, and hardware.
Various embodiments of a UE may include, but are not limited to, mobile stations, cellular telephones, personal digital assistants (PDAs) having wireless communication capabilities, portable computers having wireless communication capabilities, image capture devices such as digital cameras having wireless communication capabilities, gaming devices having wireless communication capabilities, music storage and playback appliances having wireless communication capabilities, Internet appliances permitting wireless Internet access and browsing, as well as portable units or terminals that incorporate combinations of such functions.
As used in this application, the term “circuitry” refers at least to each of the following:
This definition of “circuitry” applies to all uses of this term in this application, including in any claims. As a further example, as used in this application, the term “circuitry” would also cover an implementation of merely a processor (or multiple processors) or portion of a processor and its (or their) accompanying software and/or firmware. The term “circuitry” would also cover, for example and if applicable to the particular claim element, a baseband integrated circuit or applications processor integrated circuit for a mobile phone or a similar integrated circuit in a server, a cellular network device, or other network device.
It is to be understood that what is described above is what is presently considered the preferred embodiments of the present invention. However, it should be noted that the description of the preferred embodiments is given by way of example only and that various modifications may be made without departing from the scope of the invention as defined by the appended claims. That is, the above embodiments are to be understood as illustrative examples of the invention. Further embodiments of the invention are envisaged.
