Patent Application
20210197560
The present application is based on, and claims priority from JP Application Serial Number 2019-235447, filed Dec. 26, 2019, the disclosure of which is hereby incorporated by reference herein in its entirety.
The present disclosure relates to a head unit control device, a head unit, and a liquid ejection device.
JP-A-2016-049691 discloses a liquid ejection device such as an ink jet printer that ejects a liquid such as ink from each of a plurality of ejection portions included in a head unit to form an image on a medium, and has a determination section that executes a determination process for determining an ejection state of the ink from each ejection portion. In this type of liquid ejection device, for example, whenever a determination process for one ejection portion among a plurality of ejection portions is finished, a determination portion outputs determination information indicating a determination result for the ejection portion to a control portion controlling a head unit and the like.
Meanwhile, in a case where a transmission process of transmitting determination information corresponding to an ejection portion is executed whenever a determination process for one of a plurality of ejection portions is finished, there is concern that the time required for the transmission process may increase as the number of ejection portions increases.
In order to solve the above problem, according to an aspect of the present disclosure, there is provided a head unit control device controlling a head unit including a plurality of ejection portions that includes a first ejection portion and a second ejection portion and a determination portion that determines a liquid ejection state of the first ejection portion and determines a liquid ejection state of the second ejection portion, the head unit control device including a reception portion that receives, as one data set, determination result information including first determination information indicating a determination result of the liquid ejection state of the first ejection portion from the determination portion and second determination information indicating a determination result of the liquid ejection state of the second ejection portion from the determination portion, and ejection portion information including information indicating the number of the plurality of ejection portions included in the head unit, from the head unit; and an ejection control portion that controls the plurality of ejection portions based on the one data set received by the reception portion.
Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. However, in each drawing, the size and scale of each constituent are appropriately different from the actual ones. The embodiment described below is a preferred specific example of the present disclosure, so that various technically preferable limitations are attached thereto, but the scope of the present disclosure is not limited to these forms unless it is particularly stated that the present disclosure is limited in the following description.
First, a configuration of an ink jet printer 1 according to the present embodiment will be described with reference to
Printing data IMG indicating an image to be formed on the recording paper P by the ink jet printer 1 is supplied to the ink jet printer 1 from a host computer such as a personal computer or a digital camera. For example, the ink jet printer 1 executes a printing process of forming an image indicated by the printing data IMG supplied from the host computer on the recording paper P. The printing data IMG is an example of “image information”. The ink jet printer 1 may have any one of a copy function, a scanner function, a facsimile transmission function, and a facsimile reception function in addition to the printing function. In other words, the ink jet printer 1 may correspond to a so-called “multifunction peripheral”.
In the example illustrated in
In the present embodiment, as illustrated in
The control unit 2 is, for example, a computer such as a central processing unit (CPU) that controls each constituent of the ink jet printer 1. The control unit 2 may have one or more processors. For example, the control unit 2 functions as a printing control portion 22 and an information reception portion 24 by executing a control program stored in the storage unit 5. All or some of the elements realized by the control unit 2 executing the control program may be realized by hardware such as an electronic circuit including a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Alternatively, all or some of the functions of the control unit 2 may be realized by software and hardware in cooperation.
The printing control portion 22 generates signals for controlling an operation of each constituent of the ink jet printer 1, such as a printing signal SI and a waveform designation signal dCOM. Here, the waveform designation signal dCOM is a digital signal for defining a waveform of an analog drive signal COM for driving the ejection portion D. For example, the waveform designation signal dCOM is supplied from the printing control portion 22 to the drive signal generation unit 4. The printing signal SI is a digital signal for designating the type of operation of the ejection portion D. Specifically, the printing signal SI is a signal for designating the type of operation of the ejection portion D by designating whether or not the drive signal COM is supplied to the ejection portion D. The printing signal SI defines an ejection amount of ink ejected from each ejection portion D by designating whether or not the drive signal COM is supplied to the ejection portion D.
The information reception portion 24 receives, for example, the data set DS transmitted from the head unit HU to the control unit 2. The data set DS received by the information reception portion 24 may be supplied to, for example, the printing control portion 22 or the like, or may be stored in the storage unit 5. The data set DS will be described later. The printing control portion 22 is an example of an “ejection control portion”, and the information reception portion 24 is an example of a “reception portion”.
The drive signal generation unit 4 includes a DA conversion circuit and generates the drive signal COM having a waveform defined by the waveform designation signal dCOM. In the present embodiment, it is assumed that the drive signal COM includes a drive signal COMa and a drive signal COMb.
The storage unit 5 is configured to include a volatile memory such as a random access memory (RAM), and a nonvolatile memory such as a read only memory (ROM), an electrically erasable programmable read-only memory (EEPROM), or a programmable ROM (PROM). For example, the storage unit 5 stores various kinds of information such as the printing data IMG supplied from the host computer and the control program for the ink jet printer 1.
When an ejection state of ink in the ejection portion D becomes abnormal, the maintenance unit 6 performs a maintenance process for recovering the ejection state of the ink in the ejection portion D to a normal state. The ejection state includes a state in which ink is not ejected from the ejection portion D. The ejection state of the ink in the ejection portion D is determined by the determination circuit 32 which will be described later. In the following description, the ejection of ink ejected from the ejection portion D becomes abnormal, that is, a state in which the ejection portion D cannot eject the ink accurately may be referred to as abnormal ejection. For example, the abnormal ejection includes a state in which ink cannot be ejected from the ejection portion D, a state in which the ejection portion D ejects ink in an amount that is different from an ejection amount of ink defined by the drive signal COM, and a state in which the ejection portion D ejects ink at a speed that is different from an ink ejection speed defined by the drive signal COM.
The transport unit 7 has a carriage transport mechanism 71 reciprocating a carriage 120 illustrated in
As described above, each head unit HU included in the head module 3 has the switching circuit 30, the recording head HD, the determination circuit 32, and the transmission/reception circuit 34. The recording head HD includes 2×M ejection portions D. Here, the value M is “M 1”, M being a natural number. In the following description, “2×M” may be simply referred to as “2M”. In the following description, among the 2M ejection portions D provided in the recording head HD, the i-th ejection portion D may be referred to as an ejection portion D[i]. Here, the variable i is “1 S i S 2M”, M being a natural number. In the following description, when a constituent element of or a signal for the ink jet printer 1 corresponds to the ejection portion D[i] among the 2M ejection portions D, the reference numeral for representing the constituent element or the signal may be added with the subscript [i]. The 2M ejection portions D are examples of “a plurality of ejection portions”. One of two ejection portions D among the 2M ejection portions D is an example of a “first ejection portion”, and the other of the two ejection portions D is an example of a “second ejection portion”.
The switching circuit 30 switches whether or not to supply the drive signal COM output from the drive signal generation unit 4 to the ejection portion D[i] based on the printing signal SI. In the following description, among the drive signals COM, the drive signal COM supplied to the ejection portion D[i] may be referred to as a supply drive signal Vin[i]. The switching circuit 30 switches whether or not to supply a detection signal Vout[i] indicating a potential of an upper electrode Zu[i] of a piezoelectric element PZ[i] included in the ejection portion D[i] to the determination circuit 32 based on the printing signal SI. The piezoelectric element PZ[i] and the upper electrode Zu[i] will be described later with reference to
The determination circuit 32 generates determination information STT1[i] indicating a determination result of the ink ejection state in the ejection portion D[i] based on the detection signal Vout[i]. Specifically, the determination circuit 32 generates a remaining vibration signal based on the detection signal Vout[i]. The determination circuit 32 compares feature amounts such as a cycle and an amplitude of the remaining vibration signal based on the detection signal Vout[i] with reference feature amounts when an ejection state is normal, so as to determine an ink ejection state in the ejection portion D[i], and generates the determination information STT1[i] indicating the determination result. Hereinafter, the ejection portion D that is a target of an ejection state determined by the determination circuit 32 may be referred to as the determination target ejection portion D. The determination circuit 32 is an example of a “determination portion”.
Here, the remaining vibration signal based on the detection signal Vout[i] indicates a waveform of remaining vibration that is vibration remaining in the ejection portion D[i] after the ejection portion D[i] is driven by the supply drive signal Vin[i]. The number at the end of the reference sign of the determination information STT1 corresponds to the number at the end of the reference sign of the head unit HU1. Therefore, for example, the determination information STT indicating a determination result of an ink ejection state in the ejection portion D included in the head unit HU4 may also be referred to as determination information STT4. The determination information STT is an example of “determination result information”. The determination information STT for the ejection portion D corresponding to the “first ejection portion” among the 2M ejection portions D is an example of “first determination information”, and the determination information STT for the ejection portion D corresponding to the “second ejection portion” is an example of “second determination information”.
In the present embodiment, a method of using the remaining vibration signal is assumed as a method of determining an ink ejection state in the ejection portion D. However, the method of determining the ink ejection state in the ejection portion D is not limited to the method using the remaining vibration signal. For example, as a method of determining the ejection state of the ink in the ejection portion D, a method of detecting a temperature decrease occurring in the ejection portion D when the ink is ejected normally may be adopted. In this type of determination method, when a change point at which a temperature decrease rate changes after a certain time from the time at which a detected temperature reaches the maximum temperature appears, the ink ejection state is determined as being normal, and, when the change point does not appear, the ink ejection state is determined as being abnormal. For example, as the method of determining the ink ejection state in the ejection portion D, there may be the use of a method of ejecting charged ink from the ejection portion D toward a detection plate used to detect the ink ejection state and detecting a current change when the ink collides with the detection plate. For example, as the method of determining the ink ejection state in the ejection portion D, there may be the use of a method of ejecting charged ink from the ejection portion D toward an ink reception portion, and detecting the presence or absence of an induced current generated in a conductor portion when the ink passes a side part of the conductor portion disposed between the ejection portion D and the ink reception portion.
The transmission/reception circuit 34 combines, for example, a data set DS1 including the determination information STT1 output from the determination circuit 32 with data sets DS2, DS3, and DS4 supplied to a terminal TIa of the head unit HU1, and outputs the combined result to a terminal TOa of the head unit HU1. The data set DS2 is a data set DS including the determination information STT2 for the head unit HU2, the data set DS3 is a data set DS including the determination information STT3 for the head unit HU3, and the data set DS4 is a data set DS including the determination information STT4 for the head unit HU4.
The transmission/reception circuit 34 outputs, for example, the data sets DS1, DS2, DS3, and DS4 supplied to the terminal TIb of the head unit HU1 to the terminal TOb of the head unit HU1. The transmission/reception circuit 34 is an example of a “transmission portion”.
In the example illustrated in
The terminal TIa of the head unit HU2 is electrically coupled to the terminal TOa of the head unit HU3, and the terminal TOb of the head unit HU2 is electrically coupled to the terminal TIb of the head unit HU3. The terminal TIa of the head unit HU3 is electrically coupled to the terminal TOa of the head unit HU4, and the terminal TOb of the head unit HU3 is electrically coupled to the terminal TIb of the head unit HU4. In the example illustrated in
For example, in the head unit HU4, the transmission/reception circuit 34 transmits the data set DS4 including the determination information STT4 output from the determination circuit 32 to the terminal TIa of the head unit HU3. In the head unit HU3, the transmission/reception circuit 34 transmits the data set DS3 including the determination information STT3 output from the determination circuit 32 and the data set DS4 supplied to the terminal TIa, to the terminal TIa of the head unit HU2 in an order of the data sets DS3 and DS4.
In the head unit HU2, the transmission/reception circuit 34 transmits the data set DS2 including the determination information STT2 output from the determination circuit 32 and the data sets DS3 and DS4 supplied to the terminal TIa, to the terminal TIa of the head unit HU1 in an order of the data sets DS2, DS3, and DS4.
In the head unit HU1, the transmission/reception circuit 34 transmits the data set DS1 including the determination information STT1 output from the determination circuit 32 and the data sets DS2, DS3, and DS4 supplied to the terminal TIa, to the control unit 2 and the terminal TIb in an order of the data sets DS1, DS2, DS3, and DS4.
In the head unit HU1, the transmission/reception circuit 34 transmits the data sets DS1, DS2, DS3, and DS4 supplied to the terminal TIb, to the terminal TIb of the head unit HU2 in the order of the data sets being supplied to the terminal TIb. Similarly, in the head unit HU2, the transmission/reception circuit 34 transmits the data sets DS1, DS2, DS3, and DS4 supplied to the terminal TIb, to the terminal TIb of the head unit HU3 in the order of the data sets being supplied to the terminal TIb. In the head unit HU3, the transmission/reception circuit 34 transmits the data sets DS1, DS2, DS3, and DS4 supplied to the terminal TIb, to the terminal TIb of the head unit HU4 in the order of the data sets being supplied to the terminal TIb.
Consequently, the data set DS for each head unit HU is supplied to the other head units HU and the control unit 2. In other words, the determination information STT for each head unit HU is supplied to the other head units HU and the control unit 2.
Hereinafter, for convenience of description, the description will be made by using an X axis, a Y axis, and a Z axis which are orthogonal to each other illustrated in
As illustrated in
When the printing process is performed, the transport unit 7 reciprocates the carriage 120 in the +Y direction and the −Y direction, and transports the recording paper P in the +X direction, and thus changes a relative position of the recording paper P with respect to the head module 3. Consequently, the transport unit 7 enables the ink to land onto the entire recording paper P. For example, the transport unit 7 includes a carriage guide shaft 760 that reciprocatively supports the carriage 120 in the +Y direction and the −Y direction, and a timing belt 710 that is fixed to the carriage 120 and is driven by the carriage transport mechanism 71. Consequently, the transport unit 7 can reciprocate the head module 3 together with the carriage 120 in the +Y direction and the −Y direction along the carriage guide shaft 760. The transport unit 7 has a platen 750 that is provided in the −Z direction with respect to the carriage 120, and a transport roller 730 that is rotated in response to driving of the medium transport mechanism 72 to transport the recording paper P on the platen 750 in the +X direction.
The maintenance unit 6 includes a cap 610 that covers each head unit HU such that nozzles N of the ejection portions D are sealed, and a discharged ink reception portion 620 that receives discharged ink when the ink in the ejection portion D is discharged. The maintenance unit 6 has a wiper that wipes off a foreign substance such as paper powder adhering to the vicinity of the nozzle N of the ejection portion D, and a tube pump that sucks ink, bubbles, and the like in the ejection portion D, although not particularly illustrated. The nozzle N will be described later in
In the present embodiment, a case is assumed in which the carriage 120 stores four ink cartridges 122 that respectively correspond to ink with four colors such as cyan, magenta, yellow, and black.
Here, a description will be made of an outline of an operation of the printing control portion 22 when the printing process is executed. When the printing process is executed, first, the printing control portion 22 stores the printing data IMG supplied from the host computer into the storage unit 5. Next, the printing control portion 22 generates a signal such as the printing signal SI for controlling the head unit HU, and a signal such as the waveform designation signal dCOM for controlling the drive signal generation unit 4, and a signal for controlling the transport unit 7 based on various pieces of data such as the printing data IMG stored in the storage unit 5. The printing control portion 22 controls the transport unit 7 to change a relative position of the recording paper P with respect to the head module 3, and also controls the drive signal generation unit 4 and the switching circuit 30 such that the ejection portion D is driven, based on various signals such as the printing signal SI or various pieces of data stored in the storage unit 5. Therefore, the printing control portion 22 controls each constituent of the ink jet printer 1 to execute a printing process of forming an image corresponding to the printing data IMG on the recording paper P by adjusting the presence or absence of ink ejection from the ejection portion D, an ink ejection amount, an ink ejection timing, and the like.
A configuration of the ink jet printer 1 is not limited to the examples illustrated in
Each of the four recording heads HD is provided with a plurality of nozzle strings LN. Here, the nozzle string LN is a plurality of nozzles N provided to extend in a row in a predetermined direction. In the present embodiment, a case is assumed in which each nozzle string LN is configured by arranging M nozzles N to extend in a row along the X axis. Hereinafter, the eight nozzle strings LN provided in the head module 3 are also referred to as nozzle strings LNbk1, LNcy1, LNmg1, LNyl1, LNbk2, LNcy2, LNmg2, and LNyl2, respectively. Hereinafter, the nozzle N of the ejection portion D belonging to one nozzle string LN among the plurality of nozzle strings LN may be simply referred to as the ejection portion D belonging to one nozzle string LN. In other words, the ejection portion D having the nozzles N belonging to one nozzle string LN among the plurality of nozzle strings LN may be referred to as the ejection portion D belonging to one nozzle string LN.
Here, the nozzle string LNbk1 of the recording head HD1 and the nozzle string LNbk2 of the recording head HD4 are the nozzle strings LN in which the nozzles N of the ejection portions D ejecting black ink are arranged and are the nozzle strings LN that are paired with each other. The nozzle string LNcy1 of the recording head HD1 and the nozzle string LNcy2 of the recording head HD4 are the nozzle strings LN in which the nozzles N of the ejection portions D ejecting cyan ink are arranged and are the nozzle strings LN that are paired with each other. The nozzle string LNmg1 of the recording head HD2 and the nozzle string LNmg2 of the recording head HD3 are the nozzle strings LN in which the nozzles N of the ejection portions D ejecting magenta ink are arranged and are the nozzle strings LN that are paired with each other. The nozzle string LNyl1 of the recording head HD2 and the nozzle string LNy12 of the recording head HD3 are the nozzle strings LN in which the nozzles N of the ejection portions D ejecting yellow ink are arranged and are the nozzle strings LN that are paired with each other.
In the present embodiment, as will be described with reference to
The arrangement of the nozzles N in each recording head HD is not limited to the example illustrated in
In the example illustrated in
For example, in the complementary printing process illustrated in
In the complementary printing process, compared with the normal printing process illustrated in
In the present embodiment, complementary control for increasing an amount of ink ejected from the complementing ejection portion Dq in the complementary printing process may be executed by the printing control portion 22 or each head unit HU. For example, the printing control portion 22 may generate the printing signal SI based on the printing data IMG and change the printing signal SI based on the determination information STT. In other words, the printing control portion 22 may generate the printing signal SI based on the printing data IMG and the determination information STT. For example, the printing control portion 22 may stop the transmission of the printing signal SI to the head unit HU based on the determination information STT. In other words, the printing control portion 22 controls the plurality of ejection portions D based on the determination information STT included in the data set DS received by the information reception portion 24. The complementary control executed in each head unit HU will be described later with reference to
In the complementary printing process illustrated in
In the complementary printing process illustrated in
In the present embodiment, as described above, the nozzle string LN included in one of the two head units HU and the nozzle string LN included in the other of the two head units HU are paired with each other. Therefore, in the present embodiment, the determination information STT for each nozzle string LN is transmitted between the head units HU in order to execute the complementary control in each head unit HU.
The ejection portions D[1] to D[5] of the recording head HD1 belong to the nozzle string LNbk1, and the ejection portions D[6] to D[10] of the recording head HD1 belong to the nozzle string LNcy1. The ejection portions D[1] to D[5] of the recording head HD4 belong to the nozzle string LNbk2 paired with the nozzle string LNbk1, and the ejection portions D[6] to D[10] of the recording head HD4 belongs to the nozzle string LNcy2 paired with the nozzle string LNcy1.
Pieces of determination information STT1[1] to STT1[10] respectively indicating determination results of the ink ejection states in the ejection portions D[1] to D[10] of the recording head HD1 are stored in a first storage portion 340 of the head unit HU1. The data set DS1 including the determination information STT1[1] to STT1[10] is transmitted from the head unit HU1 to the head unit HU4.
The head unit HU4 stores the determination information STT1[1] to STT1[10] included in the data set DS1 received from the head unit HU1 into a second storage portion 345 of the head unit HU4. Since the determination information STT1[2] indicates “1”, the head unit HU4 specifies that the ejection portion D[2] of the recording head HD1 is in an abnormal ejection state. Therefore, as described in
Pieces of determination information STT4[1] to STT4[10] respectively indicating determination results of ink ejection states in the ejection portions D[1] to D[10] of the recording head HD4 are stored in the first storage portion 340 of the head unit HU4. The data set DS4 including the determination information STT4[1] to STT4[10] is transmitted from the head unit HU4 to the head unit HU1. The head unit HU1 stores the determination information STT4[1] to STT4[10] included in the data set DS4 received from the head unit HU4 into the second storage portion 345 of the head unit HU1.
In
In a first pattern illustrated in
A data configuration of the data set DS is not limited to the example illustrated in
As described in
The switching circuit 30 includes 2M switches Wa, 2M switches Wb, 2M switches Ws, and a coupling state designation circuit 300 that designates a coupling state of each switch W. As each switch W, for example, a transmission gate can be used.
The printing signal SI, a latch signal LAT, a change signal CH, a period designation signal Tsig, and a clock signal CL are supplied to the coupling state designation circuit 300 from the printing control portion 22. The determination information STT1[1] to STT1[2M] and the determination information STT4[1] to STT4[2M] for the head unit HU4 paired with the head unit HU1 are supplied to the coupling state designation circuit 300 from the transmission/reception circuit 34. The coupling state designation circuit 300 generates coupling state designation signals Qa[1] to Qa[2M], Qb[1] to Qb[2M], and Qs[1] to Qs[2M], and an inspection target designation signals Qt[1] to Qt[2M], based on at least some of the printing signal SI, the latch signal LAT, the change signal CH, the period designation signal Tsig, the clock signal CL, the determination information STT1[1] to STT1[2M], and the determination information STT4[1] to STT4[2M].
The coupling state designation signal Qa[i] is a signal for designating ON and OFF of the switch Wa[i]. The coupling state designation signal Qb[i] is a signal for designating ON and OFF of the switch Wb[i]. The coupling state designation signal Qs[i] is a signal for designating ON and OFF of the switch Ws[i]. The inspection target designation signal Qt[i] is a signal indicating whether or not the ejection portion D[i] is an inspection target related to an ejection state, and is supplied to the transmission/reception circuit 34.
The switch Wa[i] switches electrical coupling and decoupling between the wiring LHa and the upper electrode Zu[i] of the piezoelectric element PZ[i] included in the ejection portion D[i] based on the coupling state designation signal Qa[i]. Hereinafter, the upper electrode Zu[i] of the piezoelectric element PZ[i] included in the ejection portion D[i] may be referred to as the upper electrode Zu[i] of the ejection portion D[i]. For example, the switch Wa[i] is turned on when the coupling state designation signal Qa[i] has a high level, and thus electrically couples the wiring LHa to the upper electrode Zu[i] of the ejection portion D[i]. Consequently, the drive signal COMa supplied to the wiring LHa is supplied to the upper electrode Zu[i] of the ejection portion D[i] as the supply drive signal Vin[i]. The switch Wa[i] is turned off when the coupling state designation signal Qa[i] has a low level, and thus electrically decouples the wiring LHa from the upper electrode Zu[i] of the ejection portion D[i].
The switch Wb[i] switches electrical coupling and decoupling between the wiring LHb and the upper electrode Zu[i] of the ejection portion D[i] based on the coupling state designation signal Qb[i]. For example, the switch Wb[i] is turned on when the coupling state designation signal Qb[i] has a high level, and thus electrically couples the wiring LHb to the upper electrode Zu[i] of the ejection portion D[i]. Consequently, the drive signal COMb supplied to the wiring LHb is supplied to the upper electrode Zu[i] of the ejection portion D[i] as the supply drive signal Vin[i]. The switch Wb[i] is turned off when the coupling state designation signal Qb[i] has a low level, and thus electrically decouples the wiring LHb from the upper electrode Zu[i] of the ejection portion D[i].
The switch Ws[i] switches electrical coupling and decoupling between the wiring LHs and the upper electrode Zu[i] of the ejection portion D[i] based on the coupling state designation signal Qs[i]. For example, the switch Ws[i] is turned on when the coupling state designation signal Qs[i] has a high level, and thus electrically couples the wiring LHs to the upper electrode Zu[i] of the ejection portion D[i]. Consequently, the detection signal Vout[i] indicating a potential of the upper electrode Zu[i] of the ejection portion D[i] is supplied to the determination circuit 32 via the wiring LHs. The switch Ws[i] is turned off when the coupling state designation signal Qs[i] has a low level, and thus electrically decouples the wiring LHs from the upper electrode Zu[i] of the ejection portion D[i].
As described with reference to
The determination circuit 32 determines an ink ejection state in the ejection portion D[i] based on the remaining vibration signal obtained by shaping the detection signal Vout[i], and generates the determination information STT1[i] indicating the determination result. The determination circuit 32 supplies the determination information STT1[i] to the transmission/reception circuit 34.
As described in
The coupling state designation circuit 300 includes an input shift register 302, a complementing portion 304, a latch portion 306, and a designation signal generation portion 308. In
The input shift register 302 sequentially holds the individual designation signals Sdi[1] to Sdi[2M] serially supplied as the printing signal SI from the printing control portion 22 according to the clock signal CL. Consequently, the individual designation signals Sdi[1] to Sdi[2M] are held in the input shift register 302.
The complementing portion 304 generates the individual designation signal Sdo[1] to Sdo[2M] based on the individual designation signals Sdi[1] to Sdi[2M], the determination information STT1[1] to STT1[2M], and the determination information STT4[1] to STT4[2M]. The complementing portion 304 supplies the individual designation signals Sdo[1] to Sdo[2M] to the latch portion 306. For example, when all ejection states for the ejection portions D[1] to D[2M] of the head unit HU1 and the ejection portions D[1] to D[2M] of the head unit HU4 are normal, the individual designation signal Sdi[1] to Sdi[2M] are supplied from the complementing portion 304 to the latch portion 306 as individual designation signals Sdo[1] to Sdo[2M]. In other words, the complementing portion 304 adjusts ink ejection amounts in the plurality of ejection portions D based on the determination information STT1 and STT4.
The latch portion 306 latches the individual designation signals Sdo[1] to Sdo[2M] supplied from the complementing portion 304 at a timing at which the latch signal LAT rises. The designation signal generation portion 308 generates the coupling state designation signals Qa[i], Qb[i], and Qs[i] and the inspection target designation signal Qt[i] based on the individual designation signal Sdo[i], the latch signal LAT, the change signal CH, and the period designation signal Tsig.
The transmission/reception circuit 34 includes a first storage portion 340, a first switch portion 341, a first shift register 342, a second shift register 343, a second switch portion 344, and a second storage portion 345. In
The first storage portion 340 stores, for example, the determination information STT1[i] supplied from the determination circuit 32 based on the inspection target designation signal Qt[i]. For example, when ejection state inspection for the ejection portions D[1] to D[2M] of the head unit HU1 is finished, the first switch portion 341 supplies the determination information STT1[1] to STT1[2M] stored in the first storage portion 340 to the first shift register 342. In the example illustrated in
The first shift register 342 sequentially outputs the determination information STT1[1] to STT1[2M] according to the clock signal CL. Consequently, the data set DS1 including the determination information STT1[1] to STT1[2M] is supplied to the terminal TOa of the head unit HU1. The first shift register 342 sequentially outputs the data sets DS2 to DS4 serially supplied to the terminal TIa of the head unit HU1 according to the clock signal CL. In other words, the first shift register 342 serially supplies the data sets DS1 to DS4 to the terminal TOa of the head unit HU1 according to the clock signal CL.
The second shift register 343 serially supplies the data sets DS1 to DS4 serially supplied to the terminal TIb of the head unit HU1, to the terminal TOb of the head unit HU1 according to the clock signal CL.
For example, the second switch portion 344 supplies the determination information STT4[1] to STT4[2M] included in the data set DS4 of the head unit HU4 paired with the head unit HU1 to the second storage portion 345. In the example illustrated in
Configurations of the coupling state designation circuit 300 and the transmission/reception circuit 34 are not limited to the example illustrated in
The printing control portion 22 outputs the latch signal LAT having a pulse PlsL and the change signal CH having a pulse PlsC. Consequently, the printing control portion 22 defines the unit period Tu as a period from rising of the pulse PlsL to rising of the next pulse PlsL. The printing control portion 22 divides the unit period Tu into two control periods Tu1 and Tu2 with the pulse PlsC.
The printing signal SI includes, for example, 2M individual designation signals Sdi[1] to Sdi[2M] respectively corresponding to the 2M ejection portions D[1] to D[2M]. The individual designation signal Sdi[i] designates an aspect of driving of the ejection portion D[i] in each unit period Tu when the ink jet printer 1 executes the printing process. When the complementary printing process is executed, an aspect of driving of the ejection portion D[i] is designated by the individual designation signal Sdi[i] and the individual designation signal Sdo[i] that is generated based on the determination information STT.
The printing control portion 22 supplies the printing signal SI including the individual designation signals Sdi[1] to Sdi[2M] to the coupling state designation circuit 300 in synchronization with the clock signal CL before each unit period Tu in which the printing process is executed. The coupling state designation circuit 300 generates the coupling state designation signals Qa[i], Qb[i] and Qs[i], and the inspection target designation signal Qt[i] based on the individual designation signal Sdi[i] in the unit period Tu.
In the present embodiment, a case is assumed in which the ejection portion D[i] can form one of a large dot, a medium dot smaller than the large dot, and a small dot smaller than the medium dot in the unit period Tu. Hereinafter, an amount of ink corresponding to a large dot may be referred to as a large amount of ink, an amount of ink corresponding to a medium dot may be referred to as a medium amount of ink, and an amount of ink corresponding to a small dot may be referred to as a small amount of ink.
For example, the individual designation signal Sdi[i] designates one driving aspect among five driving aspects such as ejection of a large amount of ink, ejection of a medium amount of ink, ejection of a small amount of ink, non-ejection of ink, and driving that is a determination target when an ejection state is determined in each unit period Tu for the ejection portion D[i]. In the present embodiment, in an example, a case is assumed in which the individual designation signal Sd[i] is a 3-bit digital signal. An example of the relationship between the 3-bit digital signal of the individual designation signal Sd[i] and a designated content is illustrated in
As illustrated in
In the present embodiment, the waveform PX and the waveform PY are set such that a potential difference between the highest potential VHx and the lowest potential VLx of the waveform PX is larger than a potential difference between the highest potential VHy and the lowest potential VLy of the waveform PY. Specifically, when the ejection portion D[i] is driven by the drive signal COMa having the waveform PX, the waveform PX is set such that a medium amount of ink is ejected from the ejection portion D[i]. When the ejection portion D[i] is driven by the drive signal COMa having the waveform PY, the waveform PY is set such that a small amount of ink is ejected from the ejection portion D[i]. The potentials at the start and the end of the waveforms PX and PY are set to a reference potential V0.
When the individual designation signal Sd[i] designates the ejection portion D[i] to form a large dot, the coupling state designation circuit 300 sets the coupling state designation signal Qa[i] to a high level in the control periods Tu1 and Tu2, and sets the coupling state designation signals Qb[i] and Qs[i] to a low level in the unit period Tu. In this case, the ejection portion D[i] is driven by the drive signal COMa having the waveform PX in the control period Tu1 to eject a medium amount of ink, and is driven by the drive signal COMa having the waveform PY in the control period Tu2 to eject a small amount of ink. Consequently, the ejection portion D[i] ejects a large amount of ink in total in the unit period Tu, and thus a large dot is formed on the recording paper P.
When the individual designation signal Sd[i] designates the ejection portion D[i] to form a medium dot, the coupling state designation circuit 300 sets the coupling state designation signal Qa[i] to a high level in the control period Tu1 and to a low level in the control period Tu2, and sets the coupling state designation signals Qb[i] and Qs[i] to a low level in the unit period Tu. In this case, the ejection portion D[i] ejects a medium amount of ink in the unit period Tu, and thus a medium dot is formed on the recording paper P.
When the individual designation signal Sd[i] designates the ejection portion D[i] to form a small dot, the coupling state designation circuit 300 sets the coupling state designation signal Qa[i] to a low level in the control period Tu1 and to a high level in the control period Tu2, and sets the coupling state designation signals Qb[i] and Qs[i] to a low level in the unit period Tu. In this case, the ejection portion D[i] ejects a small amount of ink in the unit period Tu, and thus a small dot is formed on the recording paper P.
When the individual designation signal Sd[i] designates the ejection portion D[i] to perform non-ejection of ink, the coupling state designation circuit 300 sets the coupling state designation signals Qa[i], Qb[i], and Qs[i] to a low level in the unit period Tu. In this case, the ejection portion D[i] does not eject ink and thus does not form dots on the recording paper P in the unit period Tu.
The drive signal generation unit 4 outputs the drive signal COMb having a waveform PS. The waveform PS is a waveform of the drive signal COMb in the unit period Tu. In the present embodiment, the waveform PS is set such that a potential difference between the highest potential VHs and the lowest potential VLs of the waveform PS is smaller than a potential difference between the highest potential VHy and the lowest potential VLy of the waveform PY. Specifically, when the drive signal COMb having the waveform PS is supplied to the ejection portion D[i], the waveform PS is set to drive the ejection portion D[i] such that ink is not ejected from the ejection portion NU. Potentials at the start and the end of the waveform PS are set to the reference potential V0.
The printing control portion 22 outputs the period designation signal Tsig having a pulse PlsT1 and a pulse PlsT2. Consequently, the printing control portion 22 divides the unit period Tu into a control period TSS1 from the start of the pulse PlsL to the start of the pulse PlsT1, a control period TSS2 from the start of the pulse PlsT1 to the start of the pulse PlsT2, and a control period TSS3 from the start of the pulse PlsT2 to the start of the next pulse PlsL.
When the individual designation signal Sd[i] designates the ejection portion D[i] as the determination target ejection portion D, the coupling state designation circuit 300 sets the coupling state designation signal Qa[i] to a low level in the unit period Tu, sets the coupling state designation signal Qb[i] to a high level in the control periods TSS1 and TSS3 and to a low level in the control period TSS2, and sets the coupling state designation signal Qs[i] to a low level in the control periods TSS1 and TSS3 and to a high level in the control period TSS2.
In this case, the determination target ejection portion D is driven by the drive signal COMb having the waveform PS in the control period TSS1. Specifically, the piezoelectric element PZ included in the determination target ejection portion D is displaced by the drive signal COMb having the waveform PS in the control period TSS1. As a result, vibration occurs in the determination target ejection portion D. The vibration occurring in the control period TSS1 remains in the control period TSS2. In the control period TSS2, the upper electrode Zu of the piezoelectric element PZ included in the determination target ejection portion D changes a potential according to the remaining vibration occurring in the determination target ejection portion D. In other words, in the control period TSS2, the upper electrode Zu of the piezoelectric element PZ included in the determination target ejection portion D indicates a potential corresponding to an electromotive force of the piezoelectric element PZ caused by the remaining vibration occurring in the determination target ejection portion D. The potential of the upper electrode Zu may be detected as the detection signal Vout in the control period TSS2.
The individual designation signal Sdo[i] has a value among a value (1, 1, 0) for designating formation of a large dot, a value (1, 0, 0) for designating formation of a medium dot, a value (0, 1, 0) for designating formation of a small dot, a value (0, 0, 0) for designating non-ejection of ink, and a value (1, 1, 1) for designating driving of the ejection portion D that is a determination target. The designation signal generation portion 308 sets the coupling state designation signal Qa[i] to a high level in the control periods Tu1 and Tu2 when the individual designation signal Sdo[i] has the value (1, 1, 0), and sets the coupling state designation signal Qa[i] to a high level in the control period Tu1 when the individual designation signal Sdo[i] has the value (1, 0, 0). The designation signal generation portion 308 sets the coupling state designation signal Qa[i] to a high level in the control period Tu2 when the individual designation signal Sdo[i] has the value (0, 1, 0), and sets the coupling state designation signal Qb[s] to a high level in the control periods TSS1 and TSS3 and sets the coupling state designation signal Qs[i] to a high level in the control period TSS2 when the individual designation signal Sdo[i] has the value (1, 1, 1). The designation signal generation portion 308 sets each signal to a low level when the above conditions are not satisfied.
The input shift register 302 has, for example, 2M holding circuits FFsi coupled in cascade. As the holding circuit FFsi, for example, flip-flop circuits may be used.
Among the holding circuits FFsi[1] to FFsi[2M], the holding circuits FFsi[1] to FFsi[2M-1] sequentially transmit the printing signal SI to the holding circuit FFsi in the subsequent stage according to the clock signal CL. For example, the 3-bit individual designation signal Sdi is serially supplied as the printing signal SI from the printing control portion 22 to the first-stage holding circuit FFsi[1] in synchronization with the clock signal CL. The holding circuit FFsi[1] temporarily holds the 3-bit individual designation signal Sdi and sequentially transmits the individual designation signal Sdi to the holding circuit FFsi[2] in the subsequent stage according to the clock signal CL. Similarly, the holding circuits FFsi[2] to FFsi[2M−1] temporarily hold the 3-bit individual designation signal Sdi transmitted from the holding circuit FFsi in the previous stage, and sequentially transmit the individual designation signal Sdi to the holding circuit FFsi in the subsequent stage according to the clock signal CL. The individual designation signal Sdi is transmitted to the holding circuit FFsi[2M] in the final stage such that the holding circuit FFsi[i] temporarily holds the 3-bit individual designation signal Sdi[i].
The complementing portion 304 has 2M adder circuits ADD, 2M logical sum circuits OR, 2M switches AS, and 2M switches BS. The adder circuit ADD[i] adds a result of exclusive OR of the upper 2 bits of the individual designation signal Sdi[i] to the 3-bit individual designation signal Sdi[i] held in the holding circuit FFsi[i], and supplies a 3-bit signal indicating the addition result to the switch AS[i].
The switch AS[i] supplies one of the 3-bit individual designation signal Sdi[i] held in the holding circuit FFsi[i] and the 3-bit signal supplied from the adder circuit ADD[i] to the switch BS[i] based on the signal supplied from the logical sum circuit OR[i]. For example, the switch AS[i] supplies the 3-bit signal supplied from the adder circuit ADD[i] to the switch BS[i] when the signal supplied from the logical sum circuit OR[i] indicates “1”. The switch AS[i] supplies the 3-bit individual designation signal Sdi[i] to the switch BS[i] when the signal supplied from the logical sum circuit OR[i] indicates “0”.
The logical sum circuit OR[1] supplies a signal indicating a result of s logical sum of “0” and the determination information STT4[1] to the switch AS[1]. Each logical sum circuit OR[i] of the logical sum circuits OR[2] to OR[2M] supplies a signal indicating a result of a logical sum of the determination information STT4[i−1] and the determination information STT4[i] to the switch AS[i].
In other words, the signal supplied from the logical sum circuit OR[i] to the switch AS[i] corresponds to a complementary control signal for controlling whether or not an ink ejection amount in the ejection portion D[i] is increased from an ink ejection amount defined by the individual designation signal Sdi[i] based on the printing data IMG. For example, when the determination information STT4[i] indicates abnormal ejection, the signal supplied from the logical sum circuit OR[i] to the switch AS[i], that is, the complementary control signal indicates that an ink ejection amount in the ejection portion D[i] of the head unit HU1 is increased from an ink ejection amount defined by the individual designation signal Sdi[i].
When the individual designation signal Sdi[i] designates formation of a large dot, an ink ejection amount in the ejection portion D[i] of the head unit HU1 is not increased from an ink ejection amount defined by the individual designation signal Sdi[i]. In the example illustrated in
The switch BS[i] supplies one of the 3-bit signal supplied from the switch AS[i] and the signal indicating “0” to the latch circuit LTsd[i] included in the latch portion 306 as a 3-bit individual designation signal Sdo[i] based on the determination information STT1[i]
The latch portion 306 has 2M latch circuits LTsd. The latch circuit LTsd[i] latches the 3-bit individual designation signal Sdo[i] supplied from the switch BS[i] at a timing when the latch signal LAT rises. The latch circuit LTsd[i] supplies the latched 3-bit individual designation signal Sdo[i] to a decoder DC[i] and a logical product circuit AND[i] included in the designation signal generation portion 308.
The designation signal generation portion 308 has 2M decoders DCs and 2M logical product circuits AND. The decoder DC[i] generates the coupling state designation signals Qa[i] and Qb[i] And Qs[i] based on the 3-bit individual designation signal Sdo[i], the latch signal LAT, the change signal CH, and the period designation signal Tsig. The logical product circuit AND[i] generates the inspection target designation signal Qt[i] by calculating a logical product of the period designation signal Tsig and the 3-bit individual designation signal Sdo[i].
Here, a circuit configuration of the coupling state designation circuit 300 of each of the head units HU2 to HU4 is the same as that of the coupling state designation circuit 300 of the head unit HU1 except for the determination information STT supplied to the complementing portion 304. However, in the head units HU3 and HU4, “0” is supplied to the logical sum circuit OR[2M] instead of the logical sum circuit OR[1]. For example, in the head unit HU4, each logical sum circuit OR[i] of the logical sum circuits OR[1] to OR[2M−1] supplies a signal indicating a result of a logical sum of the determination information STT1[i] and the determination information STT1[i+1] to the switch AS[i], and the logical sum circuit OR[2M] supplies a signal indicating a result of a logical sum of “0” and the determination information STT1[2M] to the switch AS[2M].
A circuit configuration of the coupling state designation circuit 300 is not limited to the example illustrated in
The first storage portion 340 has 2M latch circuits LT1. The latch circuit LT1[i] latches the determination information STT1 as the determination information STT1[i] at the timing when the inspection target designation signal Qt[i] rises. The latch circuit LT1[i] supplies the latched determination information STT1[i] to the switch BS[i] of the coupling state designation circuit 300. The latch circuit LT1[i] supplies the latched determination information STT1[i] to the switch SW1[i] included in the first switch portion 341.
The first switch portion 341 has a first switch controller SCT1 and 2M switches SW1. The first switch controller SCT1 generates a switch control signal Lsig based on, for example, the inspection target designation signals Qt[1] to Qt[2M]. For example, the first switch controller SCT1 has 2M determination flags respectively corresponding to the inspection target designation signals Qt[1] to Qt[2M], and, whenever the inspection target designation signal Qt indicating “1” is supplied, the determination flag corresponding to the inspection target designation signal Qt is set to “1”. When all of the 2M determination flags are set to “1”, the first switch controller SCT1 sets the switch control signal Lsig to a high level, and sets the switch control signal Lsig to a low level after a predetermined time elapses from setting of the switch control signal Lsig to the high level. For example, the first switch controller SCT1 sets the switch control signal Lsig to a low level before the data set DS2 is supplied to the holding circuit FF1[1] described later. The first switch controller SCT1 resets the 2M determination flags to “0” when all of the 2M determination flags are set to “1”.
The switch SW1[i] is turned on when the switch control signal Lsig has a high level, and supplies the determination information STT1[i] supplied from the latch circuit LT1[i] to the holding circuit FF1 included in the first shift register 342. The switch SW1[i] is turned off when the switch control signal Lsig has a low level, and thus electrically decouples, for example, the latch circuit LT1[i] to the holding circuit FF1[i].
The first shift register 342 includes, for example, “2M+α” holding circuits FF1 coupled in cascade. “α” is, for example, the number of holding circuits FF1 required to hold the recording head information INFhd included in the data set DS. In
The holding circuit FF1[i] holds the determination information STT1[i] supplied from the switch SW1[i] before the data set DS2 is supplied to the holding circuit FF1[1]. The transmission/reception circuit 34 holds the recording head information INFhd1 in the holding circuit FF1a before the data set DS2 is supplied to the holding circuit FF1[1]. The holding circuit FF1[i] and the holding circuit FF1a sequentially transmit the held information to the holding circuit FF1 in the subsequent stage according to the clock signal CL. The holding circuit FF1a in the final stage sequentially transmits the information supplied from the previous-stage holding circuit FF1 in synchronization with the clock signal CL to the terminal TOa of the head unit HU1 according to the clock signal CL. Consequently, the data set DS1 is supplied to the terminal TOa of the head unit HU1.
Here, the first shift registers 342 of the other head units HU also operate similarly to the first shift register 342 of the head unit HU1. Therefore, the data sets DS2 to DS4 are serially supplied from the transmission/reception circuit 34 of the head unit HU2 to the holding circuit FF1[1] of the head unit HU1 in synchronization with the clock signal CL.
The holding circuit FF1[1] temporarily holds the data sets DS2 to DS4 supplied serially in synchronization with the clock signal CL, and sequentially transmits the data sets DS2 to DS4 to the holding circuit FF1[2] in the subsequent stage according to the clock signal CL. Similarly, the holding circuits FF1[2] to FF1[2M] and the holding circuit FF1a temporarily hold the information transmitted from the holding circuit FF1 in the previous stage and sequentially transmit the information to the holding circuit FF1 in the subsequent stage according to the clock signal CL. Consequently, the data sets DS2 to DS4 are supplied to the terminal TOa of the head unit HU1 after the data set DS1.
As described above, in the head unit HU1 according to the present embodiment, transmission of the determination information STT1 to the other head units HU is not executed whenever determination for one ejection portion D among the ejection portions D[1] to D[2M] is finished but is executed when determination for all of the ejection portions D[1] to D[2M] is finished.
Here, a predetermined process may be executed before and after a determination process such that a transmission process of transmitting the determination information STT1 to another head unit HU and the like and the determination process of determining an ink ejection state in the ejection portion D do not interfere with each other. In this case, the number of times of execution of the predetermined process increases as the number of times of execution of the transmission process increases. As the number of times of execution of the predetermined process increases, the processing time required to transmit the determination information STT1 for all the ejection portions D increases. In the present embodiment, compared with a case where the determination information STT1 is transmitted to another head unit HU whenever determination for one ejection portion D among the ejection portions D[1] to D[2M] is finished, the number of times of execution of the transmission process is can be reduced, and thus it is possible to reduce the time required for a series of processes for transmitting the determination information STT1 for all of the ejection portions D.
The second shift register 343 has, for example, “2M+α” holding circuits FF2 coupled in cascade. Here, “α” is, for example, the number of holding circuits FF2 required to hold the recording head information INFhd included in the data set DS. In
The data sets DS1 to DS4 that are supplied to the terminal TIb of the head unit HU1 in synchronization with the clock signal CL are serially supplied to the holding circuit FF2[1]. The holding circuit FF2[1] temporarily holds the data sets DS1 to DS4 serially supplied in synchronization with the clock signal CL, and sequentially transmits the data sets DS1 to DS4 to the holding circuit FF2[2] in the subsequent stage according to the clock signal CL. Similarly, the holding circuits FF2[2] to FF2[2M] and the holding circuit FF2a temporarily hold the information transmitted from the holding circuit FF2 in the previous stage, and sequentially transmit the information to the holding circuit FF2 in the subsequent stage according to the clock signal CL. The holding circuit FF2a in the final stage sequentially transmits the information supplied from the holding circuit FF2 in the previous stage in synchronization with the clock signal CL, to the terminal TOb of the head unit HU1 according to the clock signal CL. Consequently, the data sets DS1 to DS4 are supplied to the terminal TOa of the head unit HU1.
The second switch portion 344 has a second switch controller SCT2 and 2M switches SW2. The second switch controller SCT2 generates, for example, a switch control signal PSEL based on the recording head information INFhd4 included in the data set DS4. For example, the second switch controller SCT2 analyzes the recording head information INFhd included in the data set DS supplied to the holding circuit FF2[1], and determines whether or not the data set DS supplied to the holding circuit FF2[1] is the data set DS4 for the head unit HU4 paired with the head unit HU1.
When the data set DS4 is supplied to the holding circuit FF2[1], the second switch controller SCT2 specifies a timing at which the determination information STT4[1] to STT4[2M] are held in the holding circuits FF2[1] to FF2[2M] based on the recording head information INFhd4 included in the data set DS4. For example, the second switch controller SCT2 sets the switch control signal PSEL to a high level in accordance with a timing at which the determination information STT4[1] to STT4[2M] is transmitted from the holding circuits FF2[1] to FF2[2M] to the holding circuit FF2 in the subsequent stage. For example, the second switch controller SCT2 sets the switch control signal PSEL to the high level, and then sets the switch control signal PSEL to a low level according to the clock signal CL.
The switch SW2[i] is turned on when the switch control signal PSEL has a high level, and thus supplies the determination information STT4[i] supplied from the holding circuit FF2[i] to the latch circuit LT2[i] included in the second storage portion 345. The switch SW2[i] is turned off when the switch control signal PSEL has a low level, and thus electrically decouples, for example, the latch circuit LT2[i] from the holding circuit FF2[i].
The second storage portion 345 has 2M latch circuits LT2. The latch circuit LT2[i] latches the determination information STT4[i] supplied from the switch SW2[i] at a timing when the latch signal LAT rises. The latch circuit LT2[i] supplies the latched determination information STT4[i] to the complementing portion 304 of the coupling state designation circuit 300.
A circuit configuration of each of the transmission/reception circuits 34 of the head units HU2 to HU4 is the same as that of the transmission/reception circuit 34 of the head unit HU1.
A circuit configuration of the transmission/reception circuit 34 is not limited to the example illustrated in
For example, the second storage portion 345 may be omitted when the coupling state designation circuit 300 has a storage portion that stores logical sum results from logical sum circuits OR[1] to OR[2M].
As described above, in the present embodiment, the head unit HU includes the plurality of ejection portions D, the determination circuit 32 that determines an ink ejection state of each ejection portion D, and the transmission/reception circuit 34 that transmits the determination information STT indicating a determination result for each ejection portion D from the determination circuit 32 and the recording head information INF including information indicating the number of the plurality of ejection portions D to the control unit 2 as one data set DS. The control unit 2 includes the information reception portion 24 that receives the data set DS transmitted from the head unit HU, and the printing control portion 22 that controls the plurality of ejection portions D based on the data set DS received by the information reception portion 24.
In other words, in the present embodiment, the plurality of determination information STT corresponding to the plurality of ejection portions D and the recording head information INF including the information indicating the number of the plurality of ejection portions D are transmitted as one data set DS from the head unit HU to the control unit 2. Thus, in the present embodiment, compared with a case where the determination information STT is transmitted to another head unit HU whenever determination for one ejection portion D among the plurality of ejection portions D is finished, it is possible to suppress an increase in the time required for the series of processes for transmitting the determination information STT for all of the ejection portions D due to the increase in the number of the ejection portions D.
In the present embodiment, based on the plurality of pieces of determination information STT included in one data set DS, it is possible to determine whether or not an ink ejection state of each ejection portion D of the head unit HU corresponding to the data set DS is abnormal. In the present embodiment, when cause information indicating a cause of an abnormal ejection state is included in the determination information STT, the cause of the abnormal ejection state can be specified based on determination information included in the data set DS. For example, in the present embodiment, a cause of the abnormal ejection state can be specified based on the cause information included in the determination information STT and information for identifying a plurality of causes of the abnormal ejection state.
In the present embodiment, when the recording head information INF includes information indicating an arrangement of the plurality of ejection portions D, it is possible to easily specify the ejection portion D of which an ink ejection state is abnormal based on the recording head information INF and the determination information STT. In the present embodiment, the printing signal that defines an ejection amount of ink ejected from each ejection portion D can be changed according to an ejection state of each ejection portion D specified by the plurality of determination information STT included in the data set DS. In the present embodiment, transmission of the printing signal SI to the head unit HU can be stopped according to an ejection state of each ejection portion D specified by the plurality of determination information STT included in the data set DS.
In the present embodiment, the transmission/reception circuit 34 has the first shift register 342 that sequentially outputs a plurality of pieces of determination information STT. Therefore, each head unit HU serially outputs the plurality of pieces of determination information STT from the first shift register 342, and can thus transmit the plurality of pieces of determination information STT as one data set DS to the other head units HU and the control unit 2.
Specifically, the first shift register 342 has a plurality of latch circuits LT1 coupled in cascade. For example, the first shift register 342 outputs the plurality of pieces of determination information STT held in the plurality of latch circuits LT1 as one data set DS from the latch circuit LT1 in the final stage among the plurality of latch circuits LT1.
Therefore, in the present embodiment, the number of wirings for transmitting the plurality of pieces of determination information STT between the head units HU and the number of wirings for transmitting the plurality of pieces of determination information STT from the head unit HU to the control unit 2 can be reduced compared with a case of outputting the plurality of pieces of determination information STT in parallel.
Each of the above forms can be variously modified. Specific modification aspects will be exemplified below. Two or more aspects freely selected from the following exemplifications may be combined with each other as appropriate within the scope in which the aspects are not contradictory to each other. In the modification examples described below, an element having the same operation or function as that in the embodiment will be given the reference numeral used in the above description, and detailed description thereof will be omitted as appropriate.
In the above-described embodiment, a description has been made of an example of a case where the determination circuit 32 determines the determination target ejection portions D one by one, but the present disclosure is not limited to such an aspect. For example, the determination circuit 32 may include a first determination portion that determines an ink ejection state of one of the two different ejection portions D and a second determination portion that determines an ink ejection state of the other of the two ejection portions D. The second determination portion may be operated in parallel with the first determination portion.
For example, the first determination portion may determine an ink ejection state of the odd-numbered ejection portion D, and the second determination portion may determine an ink ejection state of the even-numbered ejection portion D. Alternatively, the first determination portion may determine ink ejection states of the ejection portions D[1] to D[M], and the second determination portion may determine ink ejection states of the ejection portions D[M+1] to D[2M].
When the determination circuit 32 includes the first determination portion and the second determination portion, for example, the wiring LHs illustrated in
The determination circuit 32 may have three or more determination portions. Also in Modification Example 1, it is possible to achieve the same effect as that of the above-described embodiment. In Modification Example 1, since the second determination portion can be operated in parallel with the first determination portion, determination for the plurality of ejection portions D can be efficiently performed.
In the embodiment and Modification Example 1 described above, a description has been made of an example of a case where the transmission/reception circuit 34 transmits the data set DS output from the first shift register 342 to the control unit 2 and the like, but the present disclosure is not limited to such an aspect. For example, as illustrated in
The first compression portion 348a compresses the data sets DS1 to DS4 output from the first shift register 342 to generate compressed data sets DSc1 to DSc4. For example, the first compression portion 348a may compress the data sets DS1 to DS4 through lossless compression. Specifically, the first compression portion 348a may compress the data sets DS1 to DS4 through run-length compression or a compression method such as Huffman coding.
The first differential transmission portion 349a generates differential data signals DScd1 to DScd4 by converting the single-end compressed data sets DSc1 to DSc4 supplied from the first compression portion 348a into differential signals. The first differential transmission portion 349a supplies the differential data signals DScd1 to DScd4 to the terminal TOa of the head unit HU1. For example, the first differential transmission portion 349a transmits the differential data signals DScd1 to DScd4 that are low voltage differential signals to the terminal TOa of the head unit HU1. Specifically, the first differential transmission portion 349a transmits the differential data signals DScd1 to DScd4 based on the low voltage differential signaling (LVDS) standard.
The first differential reception portion 346a receives the differential data signals DScd2 to DScd4 supplied to the terminal TIa of the head unit HU1. For example, the first differential reception portion 346a receives the differential data signals DScd2 to DScd4 based on the LVDS standard. The first differential reception portion 346a converts the differential data signals DScd2 to DScd4 into single-end compressed data sets DSc2 to DSc4.
The first decoding portion 347a restores the data sets DS2 to DS4 by decoding the single-end compressed data sets DSc2 to DSc4 supplied from the first differential reception portion 346a. The first decoding portion 347a supplies the data sets DS2 to DS4 restored from the compressed data sets DSc2 to DSc4 to the first shift register 342.
The second differential reception portion 346b is similar to the first differential reception portion 346a, the second decoding portion 347b is similar to the first decoding portion 347a, and the second compression portion 348b is similar to the first compression portion 348a. The second differential transmission portion 349b is similar to the first differential transmission portion 349a. Thus, detailed description of the second differential reception portion 346b, the second decoding portion 347b, the second compression portion 348b, and the second differential transmission portion 349b is omitted.
The second differential reception portion 346b receives the differential data signals DScd1 to DScd4 supplied to the terminal TIb of the head unit HU1, and converts the differential data signals DScd1 to DScd4 into single-end compressed data sets DSc1 to DSc4.
The second decoding portion 347b restores the data sets DS1 to DS4 by decoding the single-end compressed data sets DSc1 to DSc4 supplied from the second differential reception portion 346b. The second decoding portion 347b supplies the data sets DS1 to DS4 restored from the compressed data sets DSc1 to DSc4 to the second shift register 343.
The second compression portion 348b compresses the data sets DS1 to DS4 output from the second shift register 343 to generate compressed data sets DSc1 to DSc4. The second compression portion 348b is another example of the “encoding portion”.
The second differential transmission portion 349b generates the differential data signals DScd1 to DScd4 by converting the single-end compressed data sets DSc1 to DSc4 supplied from the second compression portion 348b into differential signals. The second differential transmission portion 349b supplies the differential data signals DScd1 to DScd4 to the terminal TOb of the head unit HU1. The second differential transmission portion 349b is another example of the “differential transmission circuit”.
A configuration of the transmission/reception circuit 35 according to Modification Example 2 is not limited to the example illustrated in
Alternatively, among the first decoding portion 347a, the first compression portion 348a, the second decoding portion 347b, and the second compression portion 348b, only the first decoding portion 347a may be omitted. In this case, the first compression portion 348a compresses the data set DS1 to generate the compressed data set DSc1. The first compression portion 348a does not perform a compression process on the compressed data sets DSc2 to DSc4 supplied from the first differential reception portion 346a via the first shift register 342. In other words, the compressed data sets DSc2 to DSc4 are supplied to the first differential transmission portion 349a from the first differential reception portion 346a via the first shift register 342.
The first compression portion 348a may compress only the determination information STT of the recording head information INFhd and the determination information STT included in the data set DS. In this case, the second decoding portion 347b may be included in the second switch portion 344, and thus the second compression portion 348b may be omitted. For example, when the compressed data set DSc4 is supplied to the second shift register 343, the second decoding portion 347b of the head unit HU1 stores the data set DS4 restored from the compressed data set DSc4 into the second storage portion 345. In this case, the compressed data sets DSc1 to DSc4 are supplied to the second differential transmission portion 349b from the second differential reception portion 346b via the second shift register 343.
Also in Modification Example 2, it is possible to achieve the same effects as those of the above-described embodiment and Modification Example 1. In Modification Example 2, since the data set DS is compressed, it is possible to reduce an amount of the data set DS transmitted between the head units HU or between the head unit HU and the control unit 2. Since the data set DS is compressed in a lossless manner, when the compressed data set DSc is decoded, the same information as the data set DS before compression can be obtained. Consequently, it is possible to accurately transmit the determination information STT indicating the ejection portion D in an abnormal ejection state.
When the compressed data set DSc is transmitted as the differential data signal DScd, it is possible to improve the resistance to noise compared with a case where the single-end compressed data set DSc is transmitted. Particularly, when the differential data signal DScd is transmitted based on the LVDS standard, the differential data signal DScd can be stably transmitted.
A description has been made of an example of a case where the determination information STT is information indicating whether or not an ink ejection state of the ejection portion D is abnormal in the embodiment, Modification Example 1, and Modification Example 2 described above, but the present disclosure is not limited to thereto. For example, as illustrated in
When in ink ejection state of the ejection portion D is normal, a normal printing process is executed. When an ink ejection state of the ejection portion D is normal, a complementary printing process and a maintenance process are executed. When the ejection portion D fails, the complementary printing process is executed. When the ejection portion D fails, the printing control portion 22 may stop transmission of the printing signal SI to the head unit HU based on the determination information STT.
In the example illustrated in
Specifically, the information for identifying the plurality of causes is, for example, information indicating that the cause of abnormal ejection indicated by (STTa, STTb, STTc, STTd, STTe)=(1, 0, 1, 0, 0) is inclusion of bubbles in the determination information STT illustrated in
In the embodiment and the modification examples from the Modification Example 1 to Modification Example 3, a description has been made of an example of a case where the plurality of nozzles N belonging to the nozzle string LN are arranged in one row, but the present disclosure is not limited to such an aspect. For example, the plurality of nozzles N belonging to the nozzle string LN may be arranged in two rows as illustrated in
In the example illustrated in
Arrangement information regarding a value “03” and arrangement information regarding a value “04” indicate that the plurality of nozzles N belonging to the nozzle string LN are arranged in two rows. The arrangement information regarding the value “03” indicates that the nozzle numbers are sequentially assigned from the nozzles N belonging to the row located in the −Y direction of the two rows. The arrangement information regarding the value “04” indicates that the nozzle numbers are alternately assigned to the nozzles N belonging to the row located in the −Y direction and the nozzles N belonging to the row located in the +Y direction from the nozzles N located in the +X direction.
Arrangement information regarding a value “05” and arrangement information regarding a value “06” indicate that the plurality of nozzles N belonging to the nozzle string LN are arranged in zigzag. The zigzag arrangement indicates, for example, that positions in the +Y direction of the even-numbered nozzles N and the odd-numbered nozzles N from the +X direction in
Also in Modification Example 4, it is possible to achieve the same effects as those of the embodiment and the modification examples of the Modification Examples 1 to 3 described above.
In the embodiment and the modification examples from Modification Example 1 to Modification Example 4 described above, a description has been made of an example of a case where the data set DS4 for the head unit HU4 is supplied to the head unit HU1 via the head units HU3 and HU2, but the present disclosure is not limited to such an aspect. For example, as illustrated in
In the example illustrated in
The terminal TOa of the head unit HU1 is electrically coupled to the terminal TIb of the head unit HU4 and the control unit 2. The terminal TOa of the head unit HU2 is electrically coupled to the terminal TIa of the head unit HU1 and the terminal TIb of the head unit HU3.
The terminal TOa of the head unit HU3 is electrically coupled to the terminals TIa and TIb of the head unit HU2. The terminal TOa of the head unit HU4 is electrically coupled to the terminal TIa of the head unit HU3 and the terminal TIb of the head unit HU1. Next, a description will be made of a flow of each data set DS when the head units HU1, HU2, HU3, and HU4 are coupled as illustrated in
The flow of the data sets DS1 to DS4 supplied to the control unit 2 is the same as that in the ink jet printer 1 illustrated in
The data set DS1 is supplied from the terminal TOa of the head unit HU1 to the terminal TIb of the head unit HU4 without passing through the head units HU2 and HU3. The data set DS2 is supplied from the terminal TOa of the head unit HU2 to the terminal TIb of the head unit HU3 without passing through the head unit HU1. The data set DS3 is supplied from the terminal TOa of the head unit HU3 to the terminal TIb of the head unit HU2 without passing through the head unit HU1. The data set DS4 is supplied from the terminal TOa of the head unit HU4 to the terminal TIb of the head unit HU1 without passing through the head units HU3 and HU2.
In the example illustrated in
In the embodiment and the modification examples from Modification Example 1 to Modification Example 5 described above, a description has been made of an example of a case where, when determination for all of the 2M ejection portions D included in the head unit HU is finished, the determination information STT is transmitted to another head unit HU, but the present disclosure is not limited to such an aspect. For example, the transmission of the determination information STT to another head unit HU or the like may be executed when determination for two or more ejection portions D among the ejection portions D[1] to D[2M] is finished. Specifically, for example, the transmission of the determination information STT to another head unit HU or the like may be executed when determination for M ejection portions D among the ejection portions D[1] to D[2M] is finished.
Also in Modification Example 6, the plurality of pieces of determination information STT are transmitted to another head unit HU or the like as one data set DS. Therefore, also in Modification Example 6, it is possible to achieve the same effects as those of the embodiment and the modification examples from Modification Example 1 to Modification Example 5 described above.
In the embodiment and the modification examples from Modification Example 1 to Modification Example 6 described above, a description has been made of an example of a case where the head module 3 has a plurality of head units HU, but the present disclosure is not limited to such an aspect. For example, the number of head units HU included in the head module 3 may be one. Also in this case, the plurality of pieces of determination information STT are transmitted to the control unit 2 as one data set DS. Therefore, also in Modification Example 7, compared with the case where the determination information STT is transmitted to the control unit 2 whenever determination for one ejection portion D among the plurality of ejection portions D is finished, it is possible to suppress an increase in the time required for the series of processes for transmitting the determination information STT for all of the ejection portions D due to the increase in the number of the ejection portions D.
In the embodiment and the modification examples from Modification Example 1 to Modification Example 7 described above, a description has been made of an example of a case where each head unit HU has the complementing portion 304, but the present disclosure is not limited to such an aspect. For example, the complementing portion 304, the second shift register 343, the second switch portion 344, and the second storage portion 345 may be omitted. In this case, the first storage portion 340 may be omitted. When the first storage portion 340 is omitted, the supply of the clock signal CL to the first shift register 342 may be stopped, for example, until the determination information STT1[1] to STT1[2M] is stored therein.
Also in Modification Example 8, a plurality of pieces of determination information STT are transmitted to the control unit 2 as one data set DS. Thus, also in Modification Example 8, compared with a case where the determination information STT is transmitted to the control unit 2 whenever determination for one ejection portion D among the plurality of ejection portions D is finished, it is possible to suppress an increase in the time required for the series of processes for transmitting the determination information STT for all of the ejection portions D due to the increase in the number of the ejection portions D.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2019-235447 | Dec 2019 | JP | national |
