Heating apparatus which interrupts energization in overheated state

BACKGROUND OF THE INVENTION
(i) Field of the Invention
The present invention relates to a heating apparatus comprising a safety mechanism for interrupting energization to a heating member in an overheated state and, more particularly, to a heating apparatus suitably used as a fixing device for heating and fixing a non-fixed image on a recording medium.
(ii) Related Background Art
In a heating fixing apparatus, in order to prevent the apparatus from being damaged by an overrunning heater due to a defective temperature detection element or temperature control circuit, energization to the heater is interrupted in an overheated state. As a safety mechanism for interrupting energization to the heater in an overheated state, a temperature fuse or a thermoswitch is employed. As a countermeasure against the defective temperature fuse or thermoswitch, when an abnormal current flows through the heater, current supply to the heater is cut off.
FIG. 9 shows a circuit breaker of the heating apparatus described in Japanese Laid-Open Patent Application No. 63-49911. The circuit breaker comprises a breaking means 101 for breaking a current flowing through a heater 100, and a detection means 102 for detecting an abnormal current flowing through the heater 100 when the heater is inactive, and is controlled to break a current flowing through the heater 100 when the abnormal current is detected by the detection means 102. However, since the circuit for detecting an abnormal current, and breaking a current flowing through the heater is constituted by a large number of elements, even if one of the large number of elements malfunctions, the breaking means 101 cannot be operated in an abnormal state, and a large current is undesirably kept flowing through the heater 100.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a heating apparatus which can assure safety in an overheated state.
It is another object of the present invention to provide a heating apparatus which can switch a switching element for interrupting energization to a heating member by an energization means under a plurality of abnormal conditions.
It is still another object of the present invention to provide a heating apparatus comprising a heating member, an energization means for energizing the heating member, a temperature detection member for detecting a temperature of the heating member, a temperature control means for controlling energization to the heating member by the energization means, so that the temperature detected by the temperature detection means is maintained at a predetermined temperature, an abnormal current detection means for detecting an abnormal current flowing through the heating member, breaking means for, when the abnormal current detection means detects an abnormal current, interrupting energization by the energization means, an energization stop means for, when the temperature detection member detects an abnormal temperature higher than the predetermined temperature, operating the breaking means to interrupt energization.
It is still another object of the present invention to provide a heating apparatus comprising a heating member, an energization means for energizing the heating member, a temperature detection member for detecting a temperature of the heating member, a first switching element for turning on/off energization by the energization means on the basis of the temperature detected by the temperature detection member, an abnormal current detection means for detecting an abnormal current flowing through the heating member, a second switching element, arranged independently of the first switching element, for, when the abnormal current detection means detects an abnormal current, turning off energization by the energization means, and an energization stop means for, when the temperature detection member detects an abnormal temperature, operating the second switching element to turn off energization. Other objects of the present invention will become apparent from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of a heating apparatus according to an embodiment of the present invention;
FIG. 2 is a circuit diagram for explaining a detection section of a comparator shown in FIG. 1;
FIGS. 3(a) to 3(d) are timing charts for explaining the operation of the circuit shown in FIG. 2;
FIGS. 4(a) to 4(g) are timing charts for explaining some operations of the circuit shown in FIG. 1;
FIGS. 5(a) to 5(g) are timing charts for explaining some operations of the circuit shown in FIG. 1;
FIGS. 6(a) to 6(i) are timing charts for explaining some operations of the circuit shown in FIG. 1;
FIG. 7 is a circuit diagram showing a circuit breaker according to the second embodiment of the present invention;
FIG. 8 is a circuit diagram showing a circuit breaker according to the third embodiment of the present invention;
FIG. 9 is a circuit diagram showing a conventional circuit breaker; and
FIG. 10 is a sectional view of the heating apparatus according to the embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
An embodiment of the present invention will be described hereinafter.
FIG. 10 is a sectional view of a heating apparatus (fixing apparatus for fixing a toner image on a recording medium) according to an embodiment of the present invention. A heating roller 31 has a mold release layer 34 on a core metal 33. The heating roller includes a heater H1.
A thermistor TH detects the surface temperature of the heating roller. Energization to the heater H1 is controlled, so that a temperature detected by the thermistor is maintained at a predetermined fixing temperature.
A compression roller 32 forms a nip with the heating roller. The roller 32 comprises a rubber layer 37 of silicone rubber formed on a shaft 36. The fixing apparatus also has an entrance guide 35 and a peeling pawl 30.
A recording medium P, which supports a non-fixed toner image T, is fixed by a heat and a pressure at the nip when it is clamped and conveyed by the heating roller 31 and the compression roller 32.
FIG. 1 shows the circuit arrangement of this embodiment.
A terminal 2 is connected to the make terminal of a contact rl1 of a relay RL1 as a breaking means through primary terminals 15 and 16. The common 10 terminal of the contact rl1 is connected to the A1 terminal of a triac TR as a bidirectional thyristor for switching a heater H1 through a thermal protector TP1 and the heater H1 for the fixing apparatus. A spark killer SQ1 for preventing a spark upon opening/closing the contact rl1 is connected between the make and common terminals of the contact rl1.
A terminal 1 is connected to the A2 terminal of the triac TR through a coil L1. The terminal 1 is also connected to the A1 terminal of the triac TR through a spark killer SQ2. A resistor R17 is connected between the A2 terminal and the gate G of the triac TR. The gate G of the triac TR is connected to an output terminal 13 of a solid-state relay SSR1 incorporating a zero-crossing detector 10. The A1 terminal of the triac TR is connected to an output terminal 14 of the solid-state relay SSR1 through a resistor R16. A commercial AC power supply V.sub.0 (not shown) is applied across the terminals 1 and 2.
In FIG. 1, an abnormal current detection means A detects an abnormal current flowing through the heater H1. The abnormal current detection means A has the following arrangement. That is, one secondary terminal 17 of a current transformer T1 is connected to an inverting input terminal 19 of a comparator CP1, and a non-inverting input terminal 24 of a comparator CP2, which comparators constitute the abnormal current detection means. A resistor R1 is connected between secondary terminals 17 and 18 of the current transformer T1. The other secondary terminal 18 of the transformer T1 is connected to a terminal 4 through resistors R3 and R2, and is also connected to a reference potential (to be referred to as "GND" hereinafter) through resistors R4 and R5. The node between the resistors R3 and R2 is connected to a non-inverting input terminal 20 of the comparator CP1, and the resistor R3 is connected in parallel with a capacitor C1. The node between the resistors R4 and R5 is connected to an inverting input terminal 25 of the comparator CP2, and the resistor R4 is connected in parallel with a capacitor C3. Furthermore, the secondary terminal 18 of the current transformer T1 is connected to the cathode of a Zener diode ZD2, and is also connected to +24 V through a resistor R9. The anode of the Zener diode ZD2 is connected to the GND, and the Zener diode ZD2 is connected in parallel with a capacitor C5.
An output terminal 21 of the comparator CP1 is connected to an output terminal 26 of the comparator CP2. The node between these terminals is connected to the base of an NPN transistor Q1, and is also connected to the terminal 4 through a resistor R6. A positive power supply input terminal 22 of the comparator CP1 is connected to +24 V, and a negative power supply input terminal 23 thereof is connected to the GND. A capacitor C2 is connected between the positive and negative power supply input terminals 22 and 23.
The emitter of the NPN transistor Q1 is connected to the GND. The collector of the transistor Q1 is connected to the terminal 4 through a resistor R7, and is also connected to the base of an NPN transistor Q2 through a resistor R8.
The base of the NPN transistor Q2 is connected to the GND through a capacitor C4, and is also connected to the anode of a diode D4. The emitter of the transistor Q2 is connected to the cathode of a Zener diode ZD1. The anode of the Zener diode ZD1 is connected to the GND. The collector of the NPN transistor Q2 is connected to the base of a PNP transistor Q3 through a resistor R10.
The emitter of the PNP transistor Q3 is connected to +24 V. The base of the transistor Q3 is connected to +24 V through a resistor R11, and is also connected to the cathode of a diode D1 and the collector of an NPN transistor Q4 through a resistor R12. The collector of the PNP transistor Q3 is connected to the GND through resistors R13 and R14. The node between the resistors R13 and R14 is connected to the GND through a capacitor C6. The emitter of the NPN transistor Q4 is connected to the GND.
The anode of the diode D1 is connected to +24 V through a resistor R15, and is also connected to the anode of a diode D2. The cathode of the diode D2 is connected to the base of an NPN transistor Q5. The emitter of the NPN transistor Q5 is connected to the GND. The collector of the NPN transistor Q5 is connected to the anode of a diode D3 and one coil of the relay RL1. The other coil of the relay RL1 is connected to the cathode of the diode D3, and the node therebetween is connected to the collector of a PNP transistor Q7 through a fuse resistor R.sub.F as a fuse element. The emitter of the PNP transistor Q7 is connected to +24 V, and the base thereof is connected to the collector of an NPN transistor Q8 through a resistor R21. The emitter of the NPN transistor Q8 is connected to the GND. The base of the NPN transistor Q8 is connected to the GND through a resistor R22, and is also connected to a P.sub.B port of a central control element CPU as a breaking control means through a resistor R23.
A P.sub.A port of the central control element CPU is connected to the base of an NPN transistor Q6 through a resistor R19. The base of the NPN transistor Q6 is further connected to the GND through a resistor R20, and the emitter thereof is connected to the GND. The collector of the NPN transistor Q6 is connected to the cathode of the diode D4, and is also connected to an input terminal 12 of the solid-state relay SSR1. An input terminal 11 of the solid-state relay SSR1 is connected to +24 V through a resistor R18.
A P.sub.C port of the central control element CPU is connected to the base of an NPN transistor Q9 through a resistor R25, and the base thereof is further connected to the GND through a resistor R24. The emitter of the NPN transistor Q9 is connected to the GND, and the collector thereof is connected to +24 V through a fan motor FM. A P.sub.D port of the central control element CPU is connected to +5 V through a resistor R26, and is also connected to the GND through a thermistor TH as a temperature detection means arranged near the heater.
The detection levels of the two comparators CP1 and CP2 will be described below with reference to FIG. 2 and FIGS. 3(a) to 3(d).
The reference voltages of the comparators CP1 and CP2 are respectively set at the positive (non-inverting) side and the negative (inverting) side, and reference voltage values V.sub.IN1 and V.sub.IN2 are respectively given by:
V.sub.IN1 =(R.sub.3 .multidot.V.sub.0 +R.sub.2 .multidot.V.sub.ZD2)/(R.sub.2 +R.sub.3)
V.sub.IN2 =(R.sub.5 .multidot.V.sub.ZD2)/(R.sub.4 +R.sub.5)
V.sub.ZD2, V.sub.IN1, and V.sub.IN2 satisfy:
V.sub.IN2 <V.sub.ZD2 <V.sub.IN1
The comparators CP1 and CP2 have open-collector outputs, and operate so that outputs V.sub.CP1 and V.sub.CP2 (if a comparison input (inverting side for CP1, non-inverting side for CP2) is represented by V.sub.IN0) are open when the following relations are satisfied:
V.sub.IN0 <V.sub.IN1, V.sub.IN2 <V.sub.IN0
and, these outputs become 0 V when the following relations are satisfied:
V.sub.IN1 <V.sub.IN0, V.sub.IN0 <V.sub.IN2
When the output terminals 21 and 26 of the comparators CP1 and CP2 are connected as indicated by a dotted line in FIG. 2, a voltage V.sub.CP0 at the node is open only when the following relation is satisfied:
V.sub.IN2 <V.sub.IN0 <V.sub.IN1
FIGS. 3(b), 3(c), and 3(d) respectively show the voltage waveforms of V.sub.CP1 (sole), V.sub.CP2 (sole), and V.sub.CP0 when a sine wave shown in FIG. 3(a) is input to V.sub.IN0.
The operation of the circuit shown in FIG. 1 will be described below.
When the power switch of the apparatus is turned on, since the surface temperature of the heating roller is lower than the fixing temperature, the central control element CPU sets the P.sub.b port at "H" level to enable the NPN transistor Q8 through the resistor R23, and to enable the PNP transistor Q7. At the same time, the central control element sets the P.sub.C port at "H" level to enable the NPN transistor Q9, thereby rotating the fan motor FM for cooling the interior of the apparatus.
In a normal state, when the temperature detected by the thermistor TH is higher than the fixing temperature, and the P.sub.A port of the central control element CPU is at "L" level, the transistor Q6 is disabled. For this reason, no current flows through a light-emitting diode D10 (connected between the input terminals 11 and 12) of the solid-state relay SSR1, and the solid-state relay SSR1 is disabled. Thus, no gate current flows through the triac TR, and the triac TR is disabled. As a result, even when the commercial AC power supply is applied across the terminals 1 and 2, no current flows through the primary side of the current transformer T1.
When no current flows through the primary side of the current transformer T1, no voltage is induced at the secondary side of the current transformer T1, and as described above, the voltage V.sub.IN0 to the inverting input terminal 19 of the comparator CP1 and the non-inverting input terminal 24 of the comparator CP2 satisfies:
V.sub.IN2 <V.sub.IN0 =V.sub.ZD2 <V.sub.IN1
In this case, since the outputs from both the comparators CP1 and CP2 are open, a base current flows through the NPN transistor Q1 through the resistor R6, and the NPN transistor Q1 is enabled. When the NPN transistor Q1 is enabled, since the base voltage of the NPN transistor Q2 has a value near 0 V, the NPN transistor Q2 is disabled. When the NPN transistor Q2 is disabled, since no base current flows through the PNP transistor Q3 and the NPN transistor Q4, the PNP transistor Q3 and the NPN transistor Q4 are disabled, and a base current flows through the NPN transistor Q5 through the resistor R15 and the diode D2, thereby enabling the NPN transistor Q5. When the NPN transistor Q5 is enabled, a current flows through the relay RL1. As described above, since the PNP transistor Q7 is enabled, the relay RL1 is enabled, and the make terminal of the contact rl1 of the relay RL1 is switched to a dotted line side in FIG. 1.
As described above, when the central control element CPU sets the P.sub.A port at "L" level, the triac TR is in an OFF state. For this reason, even when the contact rl1 of the relay RL1 is switched to the dotted line side, no current flows through the primary side of the current transformer T1, and the above-mentioned state continues.
When energization to the heater H1 is turned off during constant temperature control of the heating roller, and the temperature detected by the thermistor TH becomes lower than the fixing temperature, and when the central control element CPU sets the P.sub.A port at "H" level, a base current flows through the NPN transistor Q6 through the resistor R19, and the NPN transistor Q6 is enabled. When the NPN transistor Q6 is enabled, since the base of the NPN transistor Q2 is connected to the GND through the diode D4 and the collector and emitter of the NPN transistor Q6, the NPN transistor Q2 is disabled, and as described above, the PNP transistor Q3 and the NPN transistor Q4 are disabled. Then, the NPN transistor Q5 is enabled, and the relay RL1 maintains an ON state. On the other hand, when the NPN transistor Q6 is enabled, since a current flows through the light-emitting diode D10 of the solid-state relay SSR1 through the resistor R18, the solid-state relay SSR1 is enabled, and a gate current flows through the triac TR. The triac TR is enabled since the gate current flows. As a result, a main current loop of the terminal 2, the primary side of the current transformer T1, the contact rl1 of the relay RL1, the thermal protector TP1, the heater H1, the triac TR, the coil L1, and the terminal 1 is formed, and a current flows through the heater H1.
In this manner, when the P.sub.A port of the central control element CPU is switched between "L" and "H" levels according to the temperature detected by the thermistor TH, the surface temperature of the heating roller can be maintained at the predetermined fixing temperature.
The circuit operation of constant temperature control in a normal state has been described. An operation in an abnormal state will be described below with reference to the timing charts shown in FIGS. 4(a) to 5(g).
When a semiconductor such as a bidirectional thyristor is used in switching of a heater, the semiconductor often fails in a short mode.
FIGS. 4(a) to 4(g) are timing charts when the triac TR fails to cause a bidirectional conduction state, and FIGS. 5(a) to 5(g) are timing charts when the triac TR fails to cause a one-directional conduction state.
In a state wherein the central control element CPU sets the P.sub.A port at "L" level, when the triac TR fails to cause a bidirectional conduction state, V.sub.IN0 as the inverting input terminal voltage of the comparator CP1 and the non-inverting input terminal voltage of the comparator CP2 becomes as shown in FIG. 4(b ). As described above, only when the following relation is satisfied, the NPN transistor Q1 is enabled, and operates, as shown in FIG. 4(c):
V.sub.IN2 <V.sub.IN0 <V.sub.IN1
On the other hand, since the NPN transistor Q6 is disabled, no current flows the collector-emitter path of the NPN transistor Q6 through the diode D4. Therefore, when the NPN transistor Q1 is disabled, the capacitor C4 is charged through the resistors R7 and R8; when the NPN transistor Q1 is enabled, the capacitor C4 is discharged through the resistor R8 and the NPN transistor Q1. FIG. 4(d) shows this state. As shown in FIG. 4(d), the voltage of the capacitor C4 is gradually increased due to the repetitive ON/OFF states of the NPN transistor Q1. When the voltage of the capacitor C4 reaches a voltage near a sum voltage (to be referred to as V.sub.Q20N hereinafter) of the Zener voltage of the Zener diode ZD1 and the base-emitter voltage of the NPN transistor Q2, a base current flows through the NPN transistor Q2, and the NPN transistor Q2 is enabled.
When the NPN transistor Q2 is enabled, a base current flows through the PNP-transistor Q3 through the resistor R10 and the NPN transistor Q2, and the PNP transistor Q3 is enabled. When the PNP transistor Q3 is enabled, a base current flows through the NPN transistor Q4 through the PNP transistor Q3 and the resistor R13, and the NPN transistor Q4 is enabled. When the NPN transistor Q4 is enabled, since a base current flows through the PNP transistor Q3 through the resistor R12 and the NPN transistor Q4, a circuit constituted by the PNP transistor Q3 and the NPN transistor Q4 operates as a self holding circuit, and maintains an ON state even when the NPN transistor Q2 is disabled. On the other hand, when the NPN transistor Q4 is enabled, since the base current of the NPN transistor Q5 is broken, the NPN transistor Q5 is disabled, and the relay RL1 is disabled. As a result, the contact rl1 of the relay RL1 is opened to a solid line position shown in FIG. 1, and a current to the heater H1 is broken.
As shown in FIGS. 5(a) to 5(g), when the triac TR fails to cause a one-directional conduction state, substantially the same circuit operations as those in the bidirectional conduction breakdown are performed, except that a time required until the voltage of the capacitor C4 reaches V.sub.Q2ON, i.e., a time required until the NPN transistor Q2 is enabled, becomes longer than that in the bidirectional conduction breakdown.
FIGS. 6(a) to 6(e) show variations of control waveforms when a one-directional conduction state occurs, and FIGS. 6(f) to 6(i) show output waveforms of the transistor Q1 when the comparator CP1 is solely used.
As described above, since the circuit constituted by the PNP transistor Q3 and the NPN transistor Q4 is the self holding circuit, no current flows through the primary side of the current transformer T1, and the following relation is satisfied:
V.sub.IN0 =V.sub.ZD2
For this reason, even when the NPN transistor Q1 is enabled, and the NPN transistor Q2 is disabled, the circuit maintains the ON state.
The circuit operations until the relay RL1 is interrupted when the triac TR is short-circuited have been described. As described above, a large number of elements are operated from when the triac TR is short-circuited until the relay RL1 is interrupted. When one of the large number of elements malfunctions, the relay RL1 can no longer perform an interrupt operation.
For this reason, the apparatus of this embodiment comprises an energization stop means for, even when elements to be operated from when an abnormal current is detected until the relay RL1 is operated malfunction, operating the relay RL1 to open the contact rl1.
When the relay RL1 does not operate due to a malfunction of an element even when an abnormal current flows through the heater, since the current is kept flowed through the heater H1, a temperature near the heater H1 increases. When the temperature near the heater H1 is increased, a resistance R.sub.TH of the thermistor TH arranged near the heater H1 is decreased, and a voltage V.sub.PD input to the P.sub.D port of the central control element CPU is decreased. The voltage V.sub.PD input to the P.sub.D port of the central control element CPU is given by:
V.sub.PD =(5.times.R.sub.TH)/(R26+R.sub.TH) [V]
The temperature dependency of the resistance of the thermistor TH is generally given by:
R=R.sub.0 e.times.p{B(1/T-1/T.sub.0)}
R.sub.0 : resistance of thermistor at T.sub.0 [K]
R: T [K]
B: thermistor constant
Therefore, the voltage V.sub.PD input to the P.sub.D port and the thermistor detection temperature have a one-to-one correspondence therebetween. When the temperature detected by the thermistor TH reaches a temperature T.sub.1 [K]which causes damages to parts near the heater H1, the voltage V.sub.PD input to the P.sub.D port of the central control element CPU is then given by: ##EQU1## The central control element CPU sets the P.sub.B port at "L" level when the voltage V.sub.PD input to its P.sub.D port becomes equal to or lower than V.sub.PD1, thereby disabling the NPN transistor Q8 and the PNP transistor Q7. Thus, the central control element CPU cuts off power supply to the relay RL1, i.e., disables the relay RL1. Furthermore, the central control element CPU sets its P.sub.C port at "L" level to disable the NPN transistor Q9. Thus, the central control element CPU cuts off power supply to the fan motor FM, and stops rotation of the fan motor FM.
As described above, the relay RL1, which disables the heater H1 when it is detected that an abnormal current flows through the heater H1, is interrupted when the thermistor TH detects that a temperature near the heater has reached a predetermined temperature T.sub.1. Thus, even when a circuit for detecting an abnormal current malfunctions, the relay RL1 can be disabled, thus improving safety. Furthermore, when smoke or fire occurs inside the apparatus in an abnormal state, if the fan is rotated, fresh air is constantly supplied into the apparatus to maintain the smoke or fire. However, since the rotation of the fan motor FM is stopped in an abnormal state, fresh air is not supplied into the apparatus, and smoke or fire can be kept from being maintained or growing.
FIG. 7 is a circuit diagram showing the second embodiment of the present invention.
In this embodiment, in addition to the first embodiment, even when an element CPU overruns, a relay RL1 can be operated by another circuit to open its contact rl1, and energization can be stopped.
In this embodiment, a comparator CP3, and resistors R27 and R28 are added to the first embodiment, and other arrangements are the same as those in the first embodiment.
As described in the first embodiment, when a temperature near a heater H1 is increased due to an abnormal current, and reaches T.sub.1 [K], and when an input voltage to a P.sub.D port of a central control element CPU becomes equal to or lower than V.sub.PD1, a P.sub.B port is set at "L" level to disable transistors Q8 and Q7, thereby cutting off power supply to the relay RL1, i.e., disabling the relay RL1. At the same time, since a voltage input to an input terminal 27 of a comparator CP3, which voltage is determined by resistive division of resistors R27 and R28, is set to be V.sub.PD1, the output from the comparator CP3 goes to "L" level, and disables the transistors Q8 and Q7.
Even when the central control element CPU overruns, the relay RL1 can be disabled by another circuit, thus further improving safety.
FIG. 8 is a circuit diagram showing the third embodiment of the present invention.
In addition to the first embodiment, an apparatus of this embodiment comprises means for preventing recovery to an energization possible state when a relay RL1 opens its contact rl1 to interrupt energization.
The arrangement of this embodiment is substantially the same as that of the first embodiment, except that the collector of a transistor Q8 is connected to one terminal of a fuse resistor R.sub.F and a coil of a relay RL1, and the other terminal of the fuse resistor R.sub.F is connected to +24 V.
Like in the first embodiment, when an input voltage to a P.sub.D port of a central control element CPU becomes equal to or lower than V.sub.PD1, the central control element CPU sets the P.sub.D port at "H" level to enable a transistor Q8, so that an overcurrent flows through the fuse resistor R.sub.F to disconnect the fuse resistor R.sub.F by melting. The central control element CPU functions as both a breaking control means, and an overcurrent application means.
As described in the first embodiment, when a temperature near the heater H1 reaches a dangerous temperature, the circuit or the apparatus is abnormal. For this reason, in this embodiment, by disconnecting the fuse resistor connected in series with the coil of the relay RL1 by melting so as to cut off power supply to the relay RL1, energization can never be recovered, thus further improving safety.
The embodiments of the present invention have been described. However, the present invention is not limited to these embodiments, and various changes and modifications may be made within the spirit and scope of the invention.

Number	Name	Date
4065802	Mizukawa et al.	Dec 1977
4751371	Clinton	Jun 1988
5162038	Wilker	Nov 1992
5175413	Holling et al.	Dec 1992

Heating apparatus which interrupts energization in overheated state

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