Claims
- 1. A semiconductor structure comprising:
a substrate; an aperture layer comprised of at least one faster-oxidizing layer adjacent to at least one slower-oxidizing layer.
- 2. The semiconductor structure of claim 1, wherein the substrate is composed of indium phosphide.
- 3. The semiconductor structure of claim 1 wherein the aperture layer is at least partially oxidized and the oxidation extends into the semiconductor structure.
- 4. The semiconductor structure of claim 3, wherein an aperture is formed in the aperture layer.
- 5. The semiconductor structure of claim 4, wherein the aperture is an oxide aperture.
- 6. The semiconductor structure of claim 4, wherein the aperture is an air aperture.
- 7. The semiconductor structure of claim 6, wherein the air aperture is formed by selectively etching out the oxide.
- 8. The semiconductor structure of claim 1, wherein an air aperture is selectively etched from semiconductor material of the aperture layer.
- 9. The semiconductor structure of claim 4, wherein the aperture is tapered.
- 10. The semiconductor structure of claim 1, wherein the faster-oxidizing layer contains aluminum arsenide.
- 11. The semiconductor structure of claim 1, wherein the faster-oxidizing layer includes aluminum indium arsenide.
- 12. The semiconductor structure of claim 1, wherein the faster-oxidizing layer is formed of a plurality of faster-oxidizing layers separated by strain reducing layers.
- 13. The semiconductor structure of claim 1, wherein the faster-oxidizing layer is formed of a plurality of faster-oxidizing layers separated by strain reducing layers.
- 14. The semiconductor structure of claim 13, wherein the faster-oxidizing layers and the strain reducing layers have opposing strains.
- 15. The semiconductor structure of claim 13, wherein the faster-oxidizing layers contain aluminum arsenide and the strain reducing layers contain aluminum indium arsenide.
- 16. The semiconductor structure of claim 1, wherein each faster-oxidizing layer is sandwiched between two slower-oxidizing layers to form a symmetrically-tapered aperture.
- 17. The semiconductor structure of claim 1, wherein each slower-oxidizing layer is sandwiched between two faster-oxidizing layers to form an symmetrically-untapered aperture.
- 18. A semiconductor laser incorporating the semiconductor structure of claim 1.
- 19. A detector incorporating the semiconductor structure of claim 1.
- 20. The semiconductor laser of claim 18 wherein the semiconductor laser is a VCSEL having a wavelength of between approximately 1 and 2 micrometers.
- 21. The semiconductor laser of claim 20 wherein the aperture layer is formed in a DBR of the VCSEL.
- 22. A method for forming a aperture in a semiconductor comprising the steps of:
depositing at least one faster-oxidizing layer adjacent to at least one slower-oxidizing layer on a substrate; and forming the aperture to a desired shape by more quickly aperturing the at least one faster-oxidizing layer than the at least one slower-oxidizing layer.
- 23. The method of claim 22, further comprising the step of oxidizing the faster-oxidizing layers and slower-oxidizing layer.
- 24. The method of claim 23, further comprising the step of selectively etching out the oxide to form an air aperture.
- 25. The method of claim 22, further comprising the step of selectively etching out the semiconductor from the faster-oxidizing layer and slower-oxidizing layer to form an air aperture.
- 26. The method of claim 22, wherein the desired shape is an asymmetric taper.
- 27. The method of claim 22, wherein the desired shape is a symmetric taper.
- 28. The method of claim 22, wherein the desired shape is untapered.
- 29. A semiconductor structure formed in a DBR of a VCSEL comprising:
alternating layers containing AlInAs and AlAs sandwiched between layers containing AlGaInAs; a buffer layer; an InP substrate wherein the buffer layer is sandwiched between the InP substrate and the alternating layers; and an aperture formed in the alternating layers to form an aperture in the DBR of the VCSEL.
Parent Case Info
[0001] The present application claims priority to U.S. Provisional Application serial No. 60/233,013, filed Sep. 15, 2000, which is hereby incorporated by reference in its entirety into the present disclosure.
Government Interests
[0002] This invention was made with the support of the United States Government under Grant No. MDA972-98-1-0001, awarded by the Department of Defense (DARPA). The Government has certain rights in this invention under 35 U.S.C. §202.
Provisional Applications (1)
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Number |
Date |
Country |
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60233013 |
Sep 2000 |
US |