Claims
- 1. A heterogeneous programmable gate array comprising:an unstructured logic sub-array of identical unstructured logic elements in a first contiguous area of said programmable gate array; an unstructured input/output interconnect structure to deliver unstructured-to-unstructured input/output signals only to elements of said unstructured logic sub-array; a structured logic sub-array of identical structured logic elements in a second contiguous area of said programmable gate array, said elements of said structured logic sub-array being complementary to said elements of said unstructured logic sub-array; a bussed input/output interconnect structure to deliver structured-to-structured input/output signals only to elements of said structured logic sub-array; a control signal bus coupled between said unstructured logic sub-array and said structured logic sub-array to deliver unstructured source signals therebetween; and a bussed signal bus connected between said unstructured logic sub-array and said structured logic sub-array to deliver structured source signals therebetween.
- 2. The heterogeneous programmable gate array of claim 1, wherein said unstructured logic sub-array implements a state machine.
- 3. The heterogeneous programmable gate array of claim 1, wherein said unstructured logic sub-array implements a decoder.
- 4. The heterogeneous programmable gate array of claim 1, wherein said unstructured logic sub-array is characterized by routing resources that are dense, short, low fan-out, and high skew.
- 5. The heterogeneous programmable gate array of claim 1, wherein said structured logic sub-array implements an arithmetic function.
- 6. The heterogeneous programmable gate array of claim 1, wherein said structured logic sub-array implements a storage register.
- 7. The heterogeneous programmable gate array of claim 1, wherein said structured logic sub-array implements random access memory.
- 8. The heterogeneous programmable gate array of claim 1, wherein said structured logic sub-array is characterized by routing resources that are sparse, long, high fan-out, and low skew.
- 9. The heterogeneous programmable gate array of claim 1, wherein said gate array includes approximately one-tenth to four-tenths unstructured logic sub-array circuitry and approximately nine-tenths to six-tenths structured logic sub-array circuitry.
Parent Case Info
This application claims priority to the provisional application bearing serial No. 60/133,145 filed on May 7, 1999.
US Referenced Citations (22)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0 910 027 |
Apr 1999 |
EP |
WO 9821725 |
May 1998 |
WO |
WO 9956394 |
Nov 1999 |
WO |
Provisional Applications (1)
|
Number |
Date |
Country |
|
60/133145 |
May 1999 |
US |