The present invention is generally directed to hard disk drives (HDDs), and more particularly to HDD PreAmps.
A conventional one-channel PreAmp 10 for a hard disk drive (HDD) is illustrated as a block diagram in
The present invention achieves technical advantages as a Preamp reduction scheme enabled to use different functional blocks inside the Preamp only during their own “active” modes. When a block is “inactive”, its I/O's will be put into High-impedance (Hi-Z) state so that all of the other “inactive” blocks do not affect operation of the one “active” block.
Table 1 shows four typical PreAmp operating modes controlled by the serial-port bits MODE0 and MODE1, and a RWN pin:
In a conventional design, such as shown at 10 in
It is also noted that I/O RDX and RDY can be swapped in their pairing with I/O WDX and WDY. The same goes for I/O SCLK and SDATA.
To make this embodiment of the invention work, three things are done:
1) Restrict the SERIAL PORT operation to “sleep” and “standby” modes only.
2) To exit from “read” or “write” modes, the user can exercise a Register Reset action. When the SERIAL PORT register contents are reset, the PreAmp 20 will automatically arrive at the “sleep” mode.
One method of triggering a Register Reset action is to force a VEE negative-voltage-to-zero-voltage transition. An implementation of such a scheme is illustrated at 30 in
3) The value of the RWN I/O is stored during the “standby” mode, as a signal called sRWN. To activate the “abhV” mode both sRWN and BHV signals should be high to enable both the READER and GAIN blocks. Thus, the RWN signal ceases its control of the ABHV function. As a result, the RWN/ABHV I/O becomes free, and it is made available to output the GAIN output result.
To explain further, the output of the GAIN block, called ABHV (short for Analog Buffer Head Voltage), is just an amplified version of the Read Head signal. The ABHV signal can be made available only when the READER block is also enabled. Thus, the ABHV signal cannot multiplex with the RDX or RDY I/O.
Effectively, there are at least two methods of enabling the READER block depending on the state of the BHV serial-port bit. A mode-control logic schematic is illustrated at 40 in
The distinction between RWN and sRWN is made because there is a critical speed requirement to switch from the “write” mode to the “read” mode for normal HDD operation. A RWN change of state from “0” to “1” through the I/O does not impair the speedy write-to-read transition. However, this will not be the case should a write-to-read operation be triggered via a slow serial-port operation of changing sRWN value from “0” to “1”. Since the ABHV function is a slow test mode used in HDD assembly, the sRWN signal can be used comfortably as described.
To provide SERIAL PORT programming in “read” mode, this embodiment of the invention can be re-configured to only multiplex I/O WDX with SCLK, and I/O WDY with SDATA. By providing separate I/O's for RDX and RDY, both the READER and SERIAL PORT blocks are now fully functional. The penalty is the requirement of having two extra I/O's—going up from 6 to 8.
The present invention advantageously utilizes only one IC chip to operate, provides simplicity, and hence lower cost and speedy operation.
Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.