The disclosure relates to techniques for fabricating semiconductor devices and, more particularly, to non-volatile memory (NVM) devices, such as oxide-nitride-oxide (ONO) devices, one form of which is nitride read only memory (NROM), or other microelectronic cells or structures.
The Field Effect Transistor
The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals.
The terminals of a field effect transistor (FET) are commonly named source, gate and drain. In the FET a small amount of voltage is applied to the gate in order to control current flowing between the source and drain. In FETs the main current appears in a narrow conducting channel formed near (usually primarily under) the gate. This channel connects electrons from the source terminal to the drain terminal. The channel conductivity can be altered by varying the voltage applied to the gate terminal, enlarging or constricting the channel and thereby controlling the current flowing between the source and the drain.
Generally, when there is no voltage on the gate, there is no electrical conduction (connection) between the source and the drain. As voltage (of the correct polarity) is applied to the gate, there is a “field effect” in the channel between the source and the drain, and current can flow between the source and the drain, and can be controlled by the voltage applied to the gate. In this manner, a small signal (gate voltage) can control a relatively large signal (current flow between the source and the drain).
The Floating Gate Transistor
A floating gate transistor is generally a transistor structure, broadly based on the FET, as described hereinabove. As illustrated in
The floating gate is disposed over tunnel oxide (comparable to the gate oxide of the FET). The floating gate is a conductor, the tunnel oxide is an insulator (dielectric material). Another layer of oxide (interpoly oxide, also a dielectric material) separates the floating gate from the control gate.
Since the floating gate is a conductor, and is surrounded by dielectric material, it can store a charge. Electrons can move around freely within the conductive material of the floating gate (which comports with the basic definition of a “conductor”).
Since the floating gate can store a charge, it can exert a field effect on the channel region between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove. Mechanisms for storing charges on the floating gate structure, as well as removing charges from the floating gate are described hereinbelow.
Generally, if a charge is stored on the floating gate, this represents a binary “1”. If no charge is stored on the floating gate, this represents a binary “0”. (These designations are arbitrary, and can be reversed so that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how a floating gate memory cell operates. The other half is how to determine whether there is a charge stored on the floating gate—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the source, drain and gate terminals, and determining how conductive the channel is. Some modes of operation for a floating gate memory cell are described hereinbelow.
Normally, the floating gate non-volatile memory (NVM) cell has only a single “charge-storing area”—namely, the conductive floating gate (FG) structure, and can therefore only store a single bit of information (binary “1” or binary “0”). More recently, using a technology referred to as “multi-level cell” (MLC), two or more bits can be stored in and read from the floating gate cell.
The NROM Memory Cell
Another type of memory cell, called a “nitride, read only memory” (NROM) cell, has a charge-storage structure which is different from that of the floating gate memory cell and which permits charges to be stored in two separate charge-storage areas. Generally, the two separate charge storage areas are located within a non-conductive layer disposed between the gate and the underlying substrate, such as a layer of nitride formed in an oxide-nitride-oxide (ONO) stack underneath the gate. The non-conductive layer acts as a charge-trapping medium. Generally, electrical charges will stay where they are put in the charge-trapping medium, rather than being free to move around as in the example of the conductive floating gate of the floating gate memory cell. A first bit of binary information (binary “1” or binary “0”) can be stored in a first portion (such as the left-hand side) of the charge-trapping medium, and a second bit of binary information (binary “1” or binary “0”) can be stored in a second portion (such as the right-hand side) of the charge-trapping medium. An alternative viewpoint is that different charge concentrations can be considered for each bit of storage. Using MLC technology, at least two bits can be stored in and read from each of the two portions (charge storage areas) of the charge-trapping medium (for a total of 4 bits), similarly 3 bits or more than 4 bits may be identified.
Other types of NVM cells may have ONO structures, such as SONOS (Silicon Oxide Nitride Oxide Semiconductor) and TANOS (Tantalum Nitride Oxide Semiconductor) devices, where either or both layers of oxide may include or embody silicon or alternate oxides (such as Aluminium Oxide) yet all of these are explicitly contemplated herein.
The ONO structure is a stack (or “sandwich”) of bottom (lower) oxide 322, a charge-trapping material such as nitride 324, and a top (upper) oxide 326. The ONO structure may have an overall thickness of approximately 10-25 nm, such as 18 nm, as follows:
the bottom oxide layer 322 may be from 3 to 6 nm, for example 4 nm thick;
the middle nitride layer 324 may be from 3 to 8 nm, for example 4 nm thick; and
the top oxide layer 326 may be from 5 to 15 nm, for example 10 nm thick.
The NROM memory cell has two spaced apart diffusions 314 and 316 (which can function as source and drain, as discussed hereinbelow), and a channel region 320 defined in the substrate between the two diffusion regions 314 and 316, and a gate 328 disposed above the ONO stack (322, 324, 326).
In
The charge-trapping material 324 is non-conductive, and therefore, although electrical charges can be stored in the charge-trapping material, they are not free to move around, they will generally stay where they are stored. Nitride is a suitable charge-trapping material. Charge trapping materials other than nitride may also be suitable for use as the charge-trapping medium. One such material is silicon dioxide with buried polysilicon islands. A layer (324) of silicon dioxide with polysilicon islands would be sandwiched between the two layers of oxide (322) and (326). Alternatively, the charge-trapping layer 324 may be constructed by implanting an impurity, such as arsenic, into a layer of silicon dioxide deposited on top of the bottom oxide 322.
The memory cell 300 is generally capable of storing at least two bits of data—at least one bit(s) in a first storage area of the nitride layer 324 represented by the dashed circle 323, and at least one bit(s) in a second storage area of the nitride layer 324 represented by the dashed circle 321. Thus, the NROM memory cell can be considered to comprise two “half cells”, each half cell capable of storing at least one bit(s). It should be understood that a half cell is not a physically separate structure from another half cell in the same memory cell. The term “half cell”, as it may be used herein, is used herein only to refer to the “left” or “right” bit storage area of the ONO stack (nitride layer). The storage areas 321, 323 may variously be referred to as “charge storage areas”, “charge trapping areas”, and the like, throughout this document. (The two charge storage areas may also be referred to as the right and left “bits”.)
Each of the storage areas 321, 323 in the charge-trapping material 324 can exert a field effect on the channel region 320 between the source and the drain, in a manner similar to how a normal FET works, as described hereinabove (
Generally, if a charge is stored in a given storage area of the charge-trapping material, this represents a binary “1”, and if no charge is stored in a given storage area of the charge-trapping material, this represents a binary “0”. (Again, these designations are arbitrary, and can be reversed to that the charged state represents binary “0” and the discharged state represents binary “1”.) That represents the programming “half” of how an NROM memory cell operates. The other half is how to determine whether there is a charge stored in a given storage area of the charge-trapping material—in other words, to “read” the memory cell. Generally, this is done by applying appropriate voltages to the diffusion regions (functioning as source and drain) and gate terminals, and determining how conductive the channel is.
Generally, one feature of NROM cells is that rather than performing “symmetrical” programming and reading, NROM cells are beneficially programmed and read “asymmetrically”, which means that programming and reading occur in opposite directions. The arrows labeled in
“Reading” an NROM Cell
Reading an NROM memory cell may involve applying voltages to the terminals of the memory cell comparable to those used to read a floating gate memory cell, but reading may be performed in a direction opposite to that of programming. Generally, rather than performing “symmetrical” programming and reading (as is the case with most SONOS and the floating gate memory cell, described hereinabove), the NROM memory cell is usually programmed and read “asymmetrically”, meaning that programming and reading occur in opposite directions. This is illustrated by the arrows in
Memory Array Architecture, Generally
Memory arrays are well known, and comprise a plurality (many, including many millions) of memory cells organized (including physically arranged) in rows (usually represented in drawings as going across the page, horizontally, from left-to-right) and columns (usually represented in drawings as going up and down the page, from top-to-bottom).
As discussed hereinabove, each memory cell comprises a first diffusion (functioning as source or drain), a second diffusion (functioning as drain or source) and a gate, each of which has to receive voltage in order for the cell to be operated, as discussed hereinabove. Generally, the first diffusions (usually designated “source”) of a plurality of memory cells are connected to a first bit line which may be designated “BL(n)”, and second diffusions (usually designated “drain”) of the plurality of memory cells are connected to a second bit line which may be designated “BL(n+1)”. Typically, the gates of a plurality of memory cells are connected to common word lines (WL).
The bit lines may be “buried bit line” diffusions in the substrate, and may serve as the source/drain diffusions for the memory cells. The wordlines may be polysilicon structures and may serve as the gate elements for the memory cells.
Notice, for example that the gates of the memory cells “e” and “f” (to the right of “e”) are both connected to the same word line WL(n). (The gate of the memory cell “d” to the left of “e” is also connected to the same word line WL(n).) Notice also that the right hand terminal (diffusion) of memory cell “e” is connected to the same bit line BL(n+1) as the left-hand terminal (diffusion) of the neighboring memory cell “f”. In this example, the memory cells “e” and “f” have two of their three terminals connected together.
The situation of neighboring memory cells sharing the same connection—the gates of neighboring memory cells being connected to the same word line, the source (for example, right hand diffusion) of one cell being connected to the drain (for example left hand diffusion) of the neighboring cell—is even more dramatically evident in what is called “virtual ground architecture” wherein two neighboring cells actually share the same diffusion. In virtual ground array architectures, the drain of one memory cell may actually be the same diffusion which is acting as the source for its neighboring cell. Examples of virtual ground array architecture may be found in U.S. Pat. Nos. 5,650,959; 6,130,452; and 6,175,519, incorporated in their entirety by reference herein.
The memory array 500 comprises a plurality (three shown) of bit lines 502 extending generally parallel to one another, in “columns” of the array. The bit lines 502 may be buried bit line diffusions formed within the substrate. Note that the bit lines 502 are spaced a distance “d” from one another.
The memory array 500 further comprises a plurality (five shown) of word lines 504 extending generally parallel to one another, in “rows” of the array. The wordlines 504 are typically polysilicon lines formed on the surface of the substrate including, on underlying structures previously formed on the surface of the substrate. For example, a charge storage layer, such as an ONO layer (not shown in
Memory cells 506 may be formed between two adjacent bit lines 502, under a wordline 504, and are shown with dashed lines (including a portion of the substrate under the bit lines themselves). A given bit line 502 may server as the source (or drain) of a given memory cell and as the drain, (or source) of an adjacent memory cell, as described hereinabove—the source/drain designation depending upon the operation (such as program or read) that the memory cell is performing at a given time.
When using diffusion bit lines (as contrasted with metal bit lines), it is necessary to provide contacts to the bit lines. In a typical situation, there may be a contact at every 16 (or 32) cells along a bit line. Therefore, the wordlines 504 are grouped into sections, such as section 504a and section 504b, which are separated from one another, as illustrated, leaving an expanse of area 510 between the two sections 504a and 504b. This area 510 is referred to as the “contact area”, because that is where connections (contacts) are made to the bit lines 502.
Anti-punchthrough (APT) implants may be implanted in areas between two adjacent wordlines 504.
Dual Polysilicon Process
The following patents and patent applications describe a dual polysilicon process (DPP) for the NROM cell:
US 2004/0157393 to Hwang describes a manufacturing process for a non-volatile memory cell of the SONOS type which attempts to reduce or minimize the undesirable effects of small dimension components.
U.S. Pat. No. 6,686,242 B2 to Willer et al. describes an NROM cell that they claim can be implemented within a 4F2 area.
U.S. Ser. No. 11/247,733, assigned to the common assignees of the present invention, describes a further process for manufacturing NROM cells.
In the DPP process, a first polysilicon layer is deposited in columns between which the bit lines 502 are implanted. Bitline oxides (not shown in
One method of silicidation is to silicide the second polysilicon layer after its deposition, but prior to patterning of the word lines. Tungsten silicide is typically used for this purpose. The resulting silicided polysilicon is then etched to be the wordlines 504.
Self-aligned silicidation, known as “salicide”, is an alternative method for silicidation of wordlines. In this process, word lines are first patterned, after which the second polysilicon layer is etched, to generate the word lines, and oxide spacers (sidewall spacers) are then created on the array. After that has been completed, the array is silicided. The silicidation self-aligns to the second polysilicon wordlines. For the salicide process, copper silicide or nickel silicide are typically used, rather than tungsten silicide.
Note that, in the wordline areas, oxide spacers are not typically formed. Instead, the oxide for the sidewall spacers completely fills the gap between word lines.
During salicidation of the polysilicon, any exposed silicon will be salicided as well. (This holds true for any blanket process performed on the substrate. Anything which is exposed will be affected by the process.) Salicidation of exposed silicon can be a particular problem in the area of the bit line contacts. If the area between the bit lines is not protected, such with an STI (Silicon Trench Isolation) or another dielectric layer (barrier), salicidation of this layer will create a leakage path.
Additional Background Information
Commonly-owned patents disclose structure and operation of NROM and related ONO memory cells. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,768,192 and 6,011,725, 6,649,972 and 6,552,387.
Commonly-owned patents disclose architectural aspects of an NROM and related ONO array, (some of which have application to other types of NVM array) such as segmentation of the array to handle disruption in its operation, and symmetric architecture and non-symmetric architecture for specific products, as well as the use of NROM and other NVM array(s) related to a virtual ground array. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,963,465, 6,285,574 and 6,633,496.
Commonly-owned patents also disclose additional aspects at the architecture level, including peripheral circuits that may be used to control an NROM array or the like. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,233,180, and 6,448,750.
Commonly-owned patents also disclose several methods of operation of NROM and similar arrays, such as algorithms related to programming, erasing, and/or reading such arrays. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,215,148, 6,292,394 and 6,477,084.
Commonly-owned patents also disclose manufacturing processes, such as the process of forming a thin nitride layer that traps hot electrons as they are injected into the nitride layer. Some examples may be found in commonly-owned U.S. Pat. Nos. 5,966,603, 6,030,871, 6,133,095 and 6,583,007.
Commonly-owned patents also disclose algorithms and methods of operation for each segment or technological application, such as: fast programming methodologies in all flash memory segments, with particular focus on the data flash segment, smart programming algorithms in the code flash and EEPROM segments, and a single device containing a combination of data flash, code flash and/or EEPROM. Some examples may be found in commonly-owned U.S. Pat. Nos. 6,954,393 and 6,967,896.
A more complete description of NROM and similar ONO cells and devices, as well as processes for their development may be found at “Non Volatile Memory Technology”, 2005 published by Saifun Semiconductor and materials presented at and through http://siliconnexus.com, both incorporated by reference herein in their entirety.
Further description of NROM and related technologies are presented in the following publications, all of which are incorporated by reference herein in their entirety:
“Design Considerations in Scaled SONOS Nonvolatile Memory Devices” presented at and through:
http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/presentations/bu_white_sonos_lehigh_univ.pdf,
“SONOS Nonvolatile Semiconductor Memories for Space and Military Applications” presented at and through:
http://klabs.org/richcontent/MemoryContent/nvmt_symp/nvmts—2000/papers/adams_d.p df,
“Philips Research—Technologies—Embedded Nonvolatile Memories” presented at and through:
http://research.philips.com/technologies/ics/nvmemories/index.html, and
“Semiconductor Memory: Non-Volatile Memory (NVM)” presented at and through:
http://ece.nus.edu.sg/stfpage/elezhucx/myweb/NVM.pdf
Glossary
Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline to which the disclosure most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks (®).
The disclosure generally relates to establishing a geometry for an element of a semiconductor device so that in a subsequent processing step (process 1), another portion of the semiconductor device will not be adversely affected by a further subsequent processing step (process 2).
For example, and without limitation, the semiconductor device may be an NROM memory cell of a memory chip having an array area and a periphery area, the element of concern may be a bitline oxide structure in the array area, and the geometry may be the height to spacing ratio (T:D) of the bitline oxides (hereinafter referred to as “aspect ratio”), as compared with a comparable height:spacing ratio (Tg:Dg) of CMOS gate electrodes in a periphery area of the die.
Furthering this example, the subsequent processing step (process 1) may be CMOS spacer formation on sidewalls of the CMOS gate electrodes, which may involve depositing, then etching spacer material (such as oxide) which will be deposited both on the CMOS gate electrodes and the memory cell bitline oxides.
Furthering this example, the “other portion” referred to (and desired not to be adversely affected in a subsequent processing step) may be underlying silicon (and/or ONO) between bitline oxides, which can be protected from being damaged by a salicidation step (process 2) by spacer material remaining over the silicon during CMOS spacer formation (process 1). Generally, it is important to preserve/protect the integrity of the silicon and/or ONO between bitline oxides to prevent bit line-to-bit line (BL-BL) leakage which may otherwise result from silicon between the bit lines being exposed to the salicidation step (process 2). Generally, the bitlines themselves are diffusions beneath the bitline oxides—commonly referred to as “buried bitlines”.
In this example, since the bitline oxides are subjected to the same steps of depositing spacer material and etching which are used to form sidewall spacers on the CMOS gate electrodes for purposes of this disclosure, the bitline oxides and the CMOS gate electrodes may be considered to be related or corresponding structures.
Exemplary (prior art) bitline oxides of the prior art may have a height (T) of 50 nm and be spaced a distance (D) of 150 nm apart from one another, and exemplary CMOS gate electrodes may have a height (Tg) of 140 nm and be spaced a distance of (Dg) 400 nm apart from one another. Note, in this example, that T:D=50/150=1:3, Tg:Dg=140/400=1:2.85, or approximately 1:3, and that T:D (1:3) is only slightly (approximately 5%) larger than Tg:Dg.
In this example of prior art, because the aspect ratio (T:D) of the bitline oxides is only slightly greater than the aspect ratio (Tg:Dg) of the gate electrodes, there is a danger that there will not be any residual sidewall spacer material between bitline oxides which would otherwise protect silicon between the bitline oxides from damage (lowering of bitline-to-bitline resistance) during a subsequent salicidation step. For example, even if T:D is set to be 5% greater than Tg:Dg, with process variations, selected areas of the die between bitline oxides could become exposed.
According to the disclosure, generally, the bitline oxides are formed with a minimum height to spacing ratio (T:D) so that spacer material between the bit lines will not be completely etched away during CMOS spacer formation. The spacer material remaining over silicon (and/or over an ONO layer on the silicon) is referred to in the parent case as “protective element” because it protects the underlying silicon from damage in a subsequent wordline salicidation step.
Generally, T:D is set to be approximately 25% greater than Tg:Dg, to ensure that there will always be some sidewall material remaining between the bitline oxides after CMOS sidewall spacer etch, hence the underlying silicon will be protected by residual sidewall material in a subsequent salicidation step.
Hence, according to the disclosure, T:D may be at least 10% greater than Tg:Dg, including approximately 10% greater, at least 15% greater, approximately 15% greater, at least 20% greater, approximately 20% greater, at least 25% greater, and approximately 25% greater, including such numbers as approximately 30% greater, approximately 35% greater, and so forth, including very large numbers such as 200% greater (although that may not be practical, for other reasons).
Thus, the disclosure may be viewed as any of:
Reference will be made in detail to embodiments of the disclosure, examples of which may be illustrated in the accompanying drawing figures (FIGs). The figures are intended to be illustrative, not limiting. Although the disclosure is generally described in the context of these embodiments, it should be understood that it is not intended to limit the disclosure to these particular embodiments.
Certain elements in selected ones of the figures may be illustrated not-to-scale, for illustrative clarity. The cross-sectional views, if any, presented herein may be in the form of “slices”, or “near-sighted” cross-sectional views, omitting certain background lines which would otherwise be visible in a true cross-sectional view, for illustrative clarity. In some cases, hidden lines may be drawn as dashed lines (this is conventional), but in other cases they may be drawn as solid lines.
If shading or cross-hatching is used, it is intended to be of use in distinguishing one element from another (such as a cross-hatched element from a neighboring un-shaded element. It should be understood that it is not intended to limit the disclosure due to shading or cross-hatching in the drawing figures.
Elements of the figures may (or may not) be numbered as follows. The most significant digits (hundreds) of the reference number correspond to the figure number. For example, elements of
Throughout the descriptions set forth in this disclosure, lowercase numbers or letters may be used, instead of subscripts. For example Vg could be written Vg. Generally, lowercase is preferred to maintain uniform font size.) Regarding the use of subscripts (in the drawings, as well as throughout the text of this document), sometimes a character (letter or numeral) is written as a subscript—smaller, and lower than the character (typically a letter) preceding it, such as “Vs” (source voltage) or “H2O” (water). For consistency of font size, such acronyms may be written in regular font, without subscripting, using uppercase and lowercase—for example “Vs” and “H20”.
This application is related to U.S. Ser. No. 11/516,617, filed 7 Sep. 2006 (which may be referred to herein as the “parent case”), which claims priority from U.S. Provisional No. 60/714,852 filed 8 Sep. 2005 (which may be referred to herein as the “provisional”).
Where applicable, descriptions involving NROM are intended specifically to include related oxide-nitride technologies, including SONOS (Silicon-Oxide-Nitride-Oxide-Silicon), MNOS (Metal-Nitride-Oxide-Silicon), MONOS (Metal-Oxide-Nitride-Oxide-Silicon) and the like used for NVM devices.
Generally, for purposes of describing this disclosure, a memory chip comprises two areas—an array area comprising bit lines, wordlines and memory cells, and a periphery area comprising CMOS devices and circuits for operating the memory array.
In one aspect, the disclosure is generally directed to a technique for preventing silicon in the array area from becoming exposed when etching CMOS sidewall spacers in the periphery area.
In another aspect, the disclosure is generally directed to the overall silicidation (salicidation) process (for reducing wordline resistance), and by preventing silicon in the array area from becoming exposed, thereby preventing undesirable side effects of salicidation in the areas between wordlines, and bit line to bit line leakage due to salicidation.
As will become evident, these objects may be achieved by creating “high aspect ratio” bitline oxides in the memory array. Generally, a high aspect ratio bitline oxide has a height:spacing ratio (T:G) which is at least approximately 0.25 times greater than a height:spacing (Tg:Dg) of CMOS gate electrodes in a peripheral area of the chip.
This high aspect ratio for the bitline oxides may be adequate to ensure that during an etchback process such as CMOS sidewall formation, sidewall fill material between bit line oxides does not etch to silicon (or to an ONO layer on the silicon). Rather, residue (portions) of the sidewall material remain, as “protective elements” (so-called in the parent case), covering the silicon between the bitline oxides, which allows for a subsequent process, such as salicidation to be performed without undue concerns about adversely affecting the properties of underlying silicon, such as bitline-to-bitline leakage.
Therefore, as used and described herein,
sidewall formation is an example of etchback processes which in some areas of the chip are intended to etch to silicon and which in other areas of the chip it is desired that they do not etch to the silicon, and
silicidation (including salicidation) is an example of processes which can improve qualities of some structures (such as reducing wordline resistance) and which can adversely affect qualities of other features (such as bit line to bit line leakage).
For example, a non-volatile memory device, such as an NROM memory cell, includes a plurality of word line areas each separated from its neighbor by a contact area, an oxide-nitride-oxide (ONO) layer within the word line areas and at least partially within the contact areas and “protective elements” generated when spacers are formed in the periphery area, to protect silicon under the ONO layer in the contact areas.
The protective elements are remnants of the sidewall fill material that are not etched back to silicon because of the high aspect ratio of the bitline oxides.
Moreover, in accordance with an embodiment of the disclosure, the protective elements are formed of one of the following: oxide, nitride and oxide-nitride-oxide. (Spacers may be made up entirely of oxide or entirely of nitride or an oxide-nitride-oxide stack.)
According to an aspect of the disclosure, the spacers are 50-150 nm thick.
According to an aspect of the disclosure, the word line areas comprise salicided or silicided word lines. The salicided word lines may be salicided with cobalt or nickel, and the silicided word lines may be silicided with tungsten silicide.
According to an aspect of the disclosure, a non-volatile memory device comprises a plurality of word line areas each separated from its neighbor by a contact area and bitline oxides having a high aspect ratio.
According to an aspect of the disclosure, the non-volatile memory device comprises protective elements (the remnants of sidewall material) disposed at least between the bitline oxides in the contact area.
A DPP Memory Array
Two wordlines 604 (compare 504) are shown, separated by a contact area 610 (compare 510) from another wordline 604b.
Two bit lines 602 (compare 502) are shown. The bit lines 602 are buried bit line diffusions.
A charge storage layer 620 is shown, and may be an ONO layer comprising a bottom oxide layer 622 (compare 322), a nitride layer 624 (compare 324), and a top oxide layer 626 (compare 326).
Bitline oxide structures 630 are shown. Each bitline oxide structure 630 is above a corresponding one of the bit lines 602. The structure may, or may not, incorporate the nitride layer 624 and the bottom oxide layer 622.
Oxide spacers 607 may be formed within the contact region 610 during the CMOS oxide spacer process, on the sides of the word lines bordering the contact region 610. And, oxide spacers 609 may also be formed within the contact region 610 on both sides of the bitline oxides 630. Generally, these spacer-like structures 607 and 609 are simply artifacts of the CMOS spacer formation, and they may protect the cell sidewall along the wordline.
Originally, an ONO layer 620, comprising a bottom oxide layer 622 (compare 322), a nitride layer 624 (compare 324) and a top oxide layer 626 (compare 326) extends across the silicon. After CMOS sidewall etch, the top oxide 626 may be consumed, resulting in only an “ON layer” 620′ (oxide 622, nitride 624) in the contact region 610. The ON layer 620′ is shown as being exposed (not covered by anything) within much of the contact region 610, notably, where it is not covered by bitline oxides 630 or oxide spacers 609 on the sidewalls of the bitline oxides 630.
The word line etch process may stop on the top oxide of the ONO layer 620 while the CMOS spacer etch process may remove the top oxide 626 and a part of the nitride layer 624.
The etching of the spacers and the word lines (1st and 2nd polysilicon layers) may etch into the ONO layer 620, which otherwise could have protected the underlying silicon.
If the ON layer 620′ is damaged, then the silicon 601 underneath the ON layer 620 in the contact region 610 may become exposed, and susceptible to salicidation.
As suggested above, the process step which produces spacers 607 and 609 may be the same step which generates spacers in the complementary metal oxide semiconductor (CMOS) periphery (not shown) of the memory array.
The height (thickness) of a gate 741 including a thin gate oxide (not numbered) under the gate 741 is labeled “Tg”, and a distance between adjacent gates 741 is labeled “Dg”.
Exemplary CMOS gate electrodes 741 may have a height (Tg) of 140 nm and be spaced a distance of (Dg) 400 nm apart from one another, in which case a ratio of height:spacing Tg:Dg=140/400=1:2.85, or approximately 1:3.
A problem arises because whereas bitline-to-bitline spacing “D” (
Herein lies the underlying cause of the problem being addressed by the present disclosure—namely, that during CMOS spacer formation and etching, wherein it is desired that the etch proceed all the way to silicon, spacer material which is also deposited in the array area also becomes etched, and may etch all the way to silicon, creating leakage problems as discussed above, particularly if there is a subsequent salicidation step performed. Certainly, one way to address the problem could be to mask off the array area before performing CMOS spacer etch. However, such an additional step would not be efficient. Therefore, the present disclosure provides a technique for avoiding etching to silicon in the array area during the CMOS spacer etch step, leaving CMOS spacer material in the array area, so that subsequent process steps are benign with regard to the underlying silicon.
The liner material may for example be oxide or nitride or a combination of both, and is significantly thick, typically on the order of the thickness of bitline oxides 630 (
The CMOS liner material 740 is also deposited in the array area, over the wordlines and the bitlines, and is also etched in the array area during CMOS sidewall spacer etchback step. In the CMOS area, exposing underlying silicon during sidewall formation is not considered to be a problem. Rather, it is a desired result so that the sidewall spacers 742 are distinct, and can later perform their function of aligning source and drain diffusions away from the gate electrode 741.
According to the disclosure, the bitline oxides (830) have sufficient height (and height to spacing ratio, taking into account the aspect ratio of the CMOS gate electrodes 741) to ensure that during etching of the spacer material 740, underlying silicon is not exposed between adjacent bitline oxides (830).
Directing attention to
However, in the contact area 610, there are no word lines and, as shown in
As discussed above, the liner (spacer) material 740 covers (is disposed over) the entire chip, which includes both the periphery (CMOS) area and the memory array (Array) area. As can be seen in
Generally, the closer the elements being blanket coated are to each other, the smaller the dips (743) in the coating material will be. Also, if the elements are very tall, the dips may not extend all the way down to the silicon.
As noted in the parent case, if, for example, the contact area 610 (
Generally, the bitlines oxides 830 are formed atop an ON layer 820′ (compare 620′) on a silicon substrate 801 (compare 701, 601). Bitline diffusions 802 (compare 602) are shown. CMOS sidewall spacer material 840 (compare 740) is shown, and dips 843 (compare 743) between adjacent bitline oxides 830.
According to the disclosure, generally, a ratio of height (T) to separation (D) for bitlines is increased (established to be at least a minimum amount) so that during a step such as CMOS sidewall etch, material such as CMOS sidewall material is not completely removed, exposing underlying silicon (and/or ONO layer(s)). In a situation where the separation (D) cannot be reduced (the denominator of the fraction is fixed), the ratio may be increased by increasing the height (T) of the bitline oxide (the numerator of the fraction is increased). Of course, if the separation (D) between bitlines can be decreased, this may serve the same objective of increasing the ratio of T:D (T divided by D).
This object may be achieved by increasing the height (thickness) of bitline oxides. For example, conventionally, bitline oxides have a thickness of approximately 50 nm.
In the prior art, such as shown in
For example, the height of bitline oxides 830 (
More importantly, the ratio T:D may be at least 10% greater than Tg:Dg, including approximately 10% greater, at least 15% greater, approximately 15% greater, at least 20% greater, approximately 20% greater, at least 25% greater, and approximately 25% greater, including such numbers as approximately 30% greater, approximately 35% greater, and so forth, including very large numbers such as 200% greater (although that may not be practical, for other reasons).
Generally, at least 25% (including approximately 25%) is considered to be a good number to ensure that the bitline oxides have a sufficiently high aspect ratio to ensure that there will be residual liner material between bitline oxides after CMOS sidewall etch so that silicon between the bitline oxides can be protected during subsequent wordline salicidation. Or, at least 25%. However, a ratio that is very large, such as 200% may cause keyhole formation between the wordlines and negate the desired impact. Tg:Dg ratios in periphery may range as high as 0.4 or higher (depending on the CMOS spacer width requirements), so T:D should be approximately 0.5 or higher.
According to the disclosure, bitline oxides with thickness T and spacing D between adjacent bitlines (particularly in the contact area, where they are exposed), should have a T:D ratio that is at least 25% greater than the maximum Tg:Dg ratio in the CMOS periphery (that is, the ratio of the maximum height of the CMOS gate Tg (the height of the polysilicon+gate oxide) to the minimum distance Dg between the gates sitting atop the silicon substrate).
Since the dips 843 (compare 743) are initially relatively small and are etched slower than the flat surfaces of the sidewall material 840, the dips 843 change little or expand only slightly as they propogate downward, during the etch. (In
As characterized in the parent case, generally, as long as the dips 843 begin with a depth (d) substantially smaller (≦90% of T) than the height (T) of the bitline oxides 830, the CMOS spacer etch step will not etch them down to ONO layer 28B, leaving a layer of protection 46 over ONO layer 28B. Generally, the amount of spacer material on top of the bitline oxide and on top of the CMOS poly gates is the same (a result of the same process step). Hence the etchback of these will also be similar. The 90% number is selected because typically there is a 10% overetch of the spacer oxide. This does not hurt the CMOS poly gate since the oxide etch has a good selectivity to silicon. However, there is no such advantage for the bitline oxide.
Typically, the thickness of the spacer material (referred to in the parent case as “liner”) is determined by the standard processes of the CMOS periphery. According to the present disclosure, the ratio of the height (T) of the bitline oxides to the distance D between bit lines depends on the liner thickness and on any process steps that may partially liner material between the bitline oxides.
It should be understood that the technique(s) described hereinabove is not limited to implementation with the salicide process. Protecting silicon in the contact area is important irrespective of the cause of the damage. Thus, increasing the height of the bit lines may be useful as a general protection for the silicon in contact areas.
While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and sub-combinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced be interpreted to include all such modifications, permutations, additions and sub-combinations.
This application is a continuation-in-part of U.S. Ser. No. 11/516,617, filed 7 Sep. 2006, which claims priority from U.S. Provisional No. 60/714,852 filed 8 Sep. 2005. The disclosures of all these applications, including all appendixes thereof, are incorporated herein by reference.
Number | Date | Country | |
---|---|---|---|
60714852 | Sep 2005 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 11516617 | Sep 2006 | US |
Child | 11882787 | Aug 2007 | US |