Patent Application
20250117673
Infrastructure usage for artificial intelligence (AI) has expanded from model serving and inference to AI data management, organization, and retrieval. For example, vector databases are used to store and organize AI embeddings in-memory for similarity search queries. Vector databases are typically architected to hold all data in-memory, as large language models (LLMs) require similarity search to be performed on embeddings in real time in Retrieval Augmented Generation (RAG) setups.
Embodiments described herein are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements, and in which:
RAG is a technique in AI inference that combines the strengths of information retrieval and language generation models to enhance response accuracy and relevance. RAG improves AI model inference capability by enabling the retrieval of relevant documents or knowledge sources and then using that content to generate generated inference results. The data to be referenced is converted into AI model embeddings, which are numerical representations in the form of large vectors. These embeddings are then stored in a vector database to allow for document retrieval. The vector database is searchable via a query to enable the retrieval of the matching database record that closest matches the query. The vector database can be sharded and divided across multiple database nodes. A vector database is a data storage and retrieval system used to manage vector data associated with AI model embeddings. The vectors are mathematical representations of data in a high-dimensional space, where the dimensions correspond to a feature of the data, where the feature is an individual measurable property or characteristic of the data.
One of the emerging challenges with vector database implementations is maintaining the availability of the nodes of the vector database, which contain information that is used by the inference pipeline of the associated AI model. If a node becomes unavailable, the model will not have access to data that that is used to operate the RAG setup. Described herein is a mechanism to maintain high availability for sharded vector databases and/or virtual machines via programmable network interface devices, such as infrastructure processing units (IPUs), data processing units (DPUs), embedded or edge processing units (EPU), and/or smart network interface controllers (smart NICs).
Programmable network interface devices are uniquely positioned as a distinct failure domain with close access to the network. Such devices can be configured to manage replicas, provide a unified front-end, track heartbeats, load balance, mitigate node failures, and manage recovery and migration as needed. In one embodiment, high availability is furthered by enabling the state of a programmable network interface device to be replicated dynamically and/or in real-time to a standby device that is configured to become immediately active in the event of the planned or unplanned deactivation of the active device.
In the following description, numerous specific details are set forth to provide a more thorough understanding. However, it will be apparent to one of skill in the art that the embodiments described herein may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring the details of the present embodiments.
The processing subsystem 101, for example, includes one or more parallel processor(s) 112 coupled to memory hub 105 via a communication link 113, such as a bus or fabric. The communication link 113 may be one of any number of standards-based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. The one or more parallel processor(s) 112 may form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor. For example, the one or more parallel processor(s) 112 form a graphics processing subsystem that can output pixels to one of the one or more display device(s) 110A coupled via the I/O hub 107. The one or more parallel processor(s) 112 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 110B.
Within the I/O subsystem 111, a system storage unit 114 can connect to the I/O hub 107 to provide a storage mechanism for the computing system 100. An I/O switch 116 can be used to provide an interface mechanism to enable connections between the I/O hub 107 and other components, such as a network adapter 118 and/or wireless network adapter 119 that may be integrated into the platform, and various other devices that can be added via one or more add-in device(s) 120. The add-in device(s) 120 may also include, for example, one or more external graphics processor devices, graphics cards, and/or compute accelerators. The network adapter 118 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.
The computing system 100 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to the I/O hub 107. Communication paths interconnecting the various components in
The one or more parallel processor(s) 112 may incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). Alternatively or additionally, the one or more parallel processor(s) 112 can incorporate circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. Components of the computing system 100 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processor(s) 112, memory hub 105, processor(s) 102, and I/O hub 107 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 can be integrated into a single package to form a system in package (SIP) configuration. In one embodiment at least a portion of the components of the computing system 100 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.
In some configurations, the computing system 100 includes one or more accelerator device(s) 130 coupled with the memory hub 105, in addition to the processor(s) 102 and the one or more parallel processor(s) 112. The accelerator device(s) 130 are configured to perform domain specific acceleration of workloads to handle tasks that are computationally intensive or require high throughput. The accelerator device(s) 130 can reduce the burden placed on the processor(s) 102 and/or parallel processor(s) 112 of the computing system 100. The accelerator device(s) 130 can include but are not limited to smart network interface cards, data processing units, cryptographic accelerators, storage accelerators, artificial intelligence (AI) accelerators, neural processing units (NPUs), storage accelerators, and/or video transcoding accelerators.
It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, may be modified as desired. For instance, system memory 104 can be connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with system memory 104 via the memory hub 105 and the processor(s) 102. In other alternative topologies, the parallel processor(s) 112 are connected to the I/O hub 107 or directly to one of the one or more processor(s) 102, rather than to the memory hub 105. In other embodiments, the I/O hub 107 and memory hub 105 may be integrated into a single chip. It is also possible that two or more sets of processor(s) 102 are attached via multiple sockets, which can couple with two or more instances of the parallel processor(s) 112.
Some of the particular components shown herein are optional and may not be included in all implementations of the computing system 100. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may use different terminology for components similar to those illustrated in
The system 200 may include workload clusters 218A-218B. The workload clusters 218A-218B can include a rack 248 that houses multiple servers (e.g., server 246). The rack 248 and the servers of the workload clusters 218A-218B may conform to the rack unit (“U”) standard, in which one rack unit conforms to a 19 inch wide rack frame and a full-sized industry standard rack accommodates 42 units (42U) of equipment. One unit (1U) of equipment (e.g., a 1U server) may be 1.75 inches high and approximately 36 inches deep. In various configurations, compute resources such as processors, memory, storage, accelerators, and switches may fit into some multiple of rack units within a rack 248.
A server 246 may host a standalone operating system configured to provide server functions, or the servers may be virtualized. A virtualized server may be under the control of a virtual machine manager (VMM), hypervisor, and/or orchestrator, and may host one or more virtual machines, virtual servers, or virtual appliances. The workload clusters 218A-218B may be collocated in a single datacenter, or may be located in different geographic datacenters. Depending on the contractual agreements, some servers may be specifically dedicated to certain enterprise clients or tenants while other servers may be shared.
The various devices in a datacenter may be interconnected via a switching fabric 270, which may include one or more high speed routing and/or switching devices. The switching fabric 270 may provide north-south traffic 202 (e.g., traffic to and from the wide area network (WAN), such as the internet), and east-west traffic 204 (e.g., traffic across the datacenter). Historically, north-south traffic 202 accounted for the bulk of network traffic, but as web services become more complex and distributed, the volume of east-west traffic 204 has risen. In many datacenters, east-west traffic 204 now accounts for the majority of traffic. Furthermore, as the capability of a server 246 increases, traffic volume may further increase. For example, a server 246 may provide multiple processor slots, with a slot accommodating a processor having four to eight cores, along with sufficient memory for the cores. Thus, a server may host a number of VMs that may be a source of traffic generation.
To accommodate the large volume of traffic in a datacenter, a highly capable implementation of the switching fabric 270 may be provided. The illustrated implementation of the switching fabric 270 is an example of a flat network in which a server 246 may have a direct connection to a top-of-rack switch (ToR switch 220A-220B) (e.g., a “star” configuration). ToR switch 220A can connect with workload cluster 218A, while ToR switch 220B can connect with workload cluster 218B. A ToR switch 220A-220B may couple to a core switch 260. This two-tier flat network architecture is shown only as an illustrative example and other architectures may be used, such as three-tier star or leaf-spine (also called “fat tree” topologies) based on the “Clos” architecture, hub-and-spoke topologies, mesh topologies, ring topologies, or 3-D mesh topologies, by way of nonlimiting example.
The switching fabric 270 may be provided by any suitable interconnect using any suitable interconnect protocol. For example, a server 246 may include a fabric interface (FI) of some type, a network interface card (NIC), or other host interface. The host interface itself may couple to one or more processors via an interconnect or bus, such as PCI, PCIe, or similar, and in some cases, this interconnect bus may be considered to be part of the switching fabric 270. The switching fabric may also use PCIe physical interconnects to implement more advanced protocols, such as compute express link (CXL).
The interconnect technology may be provided by a single interconnect or a hybrid interconnect, such as where PCIe provides on-chip communication, 1 Gb or 10 Gb copper Ethernet provides relatively short connections to a ToR switch 220A-220B, and optical cabling provides relatively longer connections to core switch 260. Interconnect technologies include, by way of nonlimiting example, Ultra Path Interconnect (UPI), FibreChannel, Ethernet, FibreChannel over Ethernet (FCoE), InfiniBand, PCIe, NVLink, or fiber optics, to name just a few. Some of these will be more suitable for certain deployments or functions than others, and selecting an appropriate fabric for the instant application is an exercise of ordinary skill.
In one embodiment, the switching elements of the switching fabric 270 are configured to implement switching techniques to improve the performance of the network in high usage scenarios. Exemplary advanced switching techniques include but are not limited to adaptive routing, adaptive fault recovery, and adaptive and/or telemetry-based congestion control.
Adaptive routing enables a ToR 220A-220B switch and/or core switch 260 to select the output port to which traffic is switched based on the load on the selected port, assuming unconstrained port selection is enabled. An adaptive routing table can configure the forwarding tables of switches of the switching fabric 270 to select between multiple ports between switches when multiple connections are present between a given set of switches in an adaptive routing group. Adaptive fault recovery (e.g., self-healing) enables the automatic selection of an alternate port if the ported selected by the forwarding table port is in a failed or inactive state, which enables rapid recovery in the event of a switch-to-switch port failure. A notification can be sent to neighboring switches when adaptive routing or adaptive fault recovery becomes active in a given switch. Adaptive congestion control configures a switch to send a notification to neighboring switches when port congestion on that switch exceeds a configured threshold, which may cause those neighboring switches to adaptively switch to uncongested ports on that switch or switches associated with an alternate route to the destination.
Telemetry-based congestion control uses dynamic and/or real-time monitoring of telemetry from network devices, such as switches within the switching fabric 270, to detect when congestion will begin to impact the performance of the switching fabric 270 and proactively adjust the switching tables within the network devices to prevent or mitigate the impending congestion. A ToR 220A-220B switch and/or core switch 260 can implement a built-in telemetry-based congestion control algorithm or can provide an application programming interface (API) though which a programmable telemetry-based congestion control algorithm can be implemented. A continuous feedback loop may be implemented in which the telemetry-based congestion control system continuously monitors the network and adjusts the traffic flow dynamically based on ongoing telemetry data.
In a datacenter network, a network flow (e.g., flow) represents the directed, ordered sequence of packets transmitted from a source node to a destination node, typically across a series of network devices such as routers, switches, and load balancers. A flow can be identified by a unique 5-tuple (source IP, source port, destination IP, destination port, and protocol). Flows may be managed using network flow tables that optimize traffic paths and ensure Quality of Service (QOS). Learning and adaptation can be implemented by the telemetry-based congestion control system in which the system can adapt to changing network conditions and improve its congestion control strategies based on historical data and trends.
Note however that while high-end fabrics are provided herein by way of illustration, more generally, the switching fabric 270 may include any suitable interconnect or bus for the particular application, including legacy interconnects used to implement a local area network (LANs), synchronous optical networks (SONET), asynchronous transfer mode (ATM) networks, wireless networks such as Wi-Fi and Bluetooth, fourth generation (4G) wireless, fifth generation (5G) wireless, digital subscriber line (DSL) interconnects, multimedia over coax alliance (MoCA) interconnects, or similar wired or wireless networks. It is also expressly anticipated that in the future, new network technologies will arise to supplement or replace some of those listed here, and any such future network topologies and technologies can be or form a part of the switching fabric 270.
The datacenter 300 includes a number of logic elements forming a plurality of nodes, where a node may be provided by a physical server, a group of servers, or other hardware. A server may also host one or more virtual machines, as appropriate to its application. A fabric 370 is provided to interconnect various aspects of datacenter 300. The fabric 370 may be provided by any suitable interconnect technology, including but not limited to InfiniBand, Ethernet, PCIe, or CXL. The fabric 370 of the datacenter 300 may be a version of and/or include elements of the switching fabric 270 of the system 200 of
The server nodes of the datacenter 300 can include but are not limited to a memory server node 304, a heterogenous compute server node 306, a CPU server node 308, and a storage server node 310. The heterogenous compute server node 306 and a CPU server node 308 can perform independent operations for different tenants or cooperatively perform operations for a single tenant. The heterogenous compute server node 306 and a CPU server node 308 can also host virtual machines that provide virtual server functionality to tenants of the datacenter.
The server nodes can connect with the fabric 370 via a fabric interface 372. The specific type of fabric interface 372 that is used depends at least in part on the technology or protocol that is used to implement the fabric 370. For example, where the fabric 370 is an Ethernet fabric, the fabric interface 372 may be an Ethernet network interface controller. Where the fabric 370 is a PCIe-based fabric, the fabric interfaces may be PCIe-based interconnects. Where the fabric 370 is an InfiniBand fabric, the fabric interface 372 of the heterogenous compute server node 306 and a CPU server node 308 may be a host channel adapter (HCA), while the fabric interface 372 of the memory server node 304 and storage server node 310 may be a target channel adapter (TCA). TCA functionality may be an implementation-specific subset of HCA functionality. The various fabric interfaces may be implemented as intellectual property (IP) blocks that can be inserted into an integrated circuit as a modular unit, as can other circuitry within the datacenter 300.
The heterogenous compute server node 306 includes multiple CPU sockets that can house a CPU 319, which may be, but is not limited to an Intel® Xeon™ processor including a plurality of cores. The CPU 319 may also be, for example, a multi-core datacenter class ARM® CPU, such as an NVIDIA® Grace™ CPU. The heterogenous compute server node 306 includes memory devices 318 to store data for runtime execution and storage devices 316 to enable the persistent storage of data within non-volatile memory devices. The heterogenous compute server node 306 is enabled to perform heterogenous processing via the presence of GPUs (e.g., GPU 317), which can be used, for example, to perform high-performance compute (HPC), media server, cloud gaming server, and/or machine learning compute operations. In one configuration, the GPUs may be interconnected and CPUs of the heterogenous compute server node 306 via interconnect technologies such as PCIe, CXL, or NVLink.
The CPU server node 308 includes a plurality of CPUs (e.g., CPU 319), memory (e.g., memory devices 318) and storage (storage devices 316) to execute applications and other program code that provide server functionality, such as web servers or other types of functionality that is remotely accessible by clients of the CPU server node 308. The CPU server node 308 can also execute program code that provides services or micro-services that enable complex enterprise functionality. The fabric 370 will be provisioned with sufficient throughput to enable the CPU server node 308 to be simultaneously accessed by a large number of clients, while also retaining sufficient throughput for use by the heterogenous compute server node 306 and to enable the use of the memory server node 304 and the storage server node 310 by the heterogenous compute server node 306 and the CPU server node 308. Furthermore, in one configuration, the CPU server node 308 may rely primarily on distributed services provided by the memory server node 304 and the storage server node 310, as the memory and storage of the CPU server node 308 may not be sufficient for all of the operations intended to be performed by the CPU server node 308. Instead, a large pool of high-speed or specialized memory may be dynamically provisioned between a number of nodes, so that the nodes have access to a large pool of resources, but those resources do not sit idle when that particular node does not need them. A distributed architecture of this type is possible due to the high speeds and low latencies provided by the fabric 370 of contemporary datacenters and may be advantageous because there is no need to over-provision resources for the server nodes.
The memory server node 304 can include memory nodes 305 having memory technologies that are suitable for the storage of data used during the execution of program code by the heterogenous compute server node 306 and the CPU server node 308. The memory nodes 305 can include volatile memory modules, such as DRAM modules, and/or non-volatile memory technologies that can operate similar to DRAM speeds, such that those modules have sufficient throughput and latency performance metrics to be used as a tier of system memory at execution runtime. The memory server node 304 can be linked with the heterogenous compute server node 306 and/or CPU server node 308 via technologies such as CXL.mem, which enables memory access from a host to a device. In such configuration, a CPU 319 of the heterogenous compute server node 306, a CPU server node 308 can link to the memory server node 304 and access the memory nodes 305 of the memory server node 304 in a similar manner as, for example, the CPU 319 of the heterogenous compute server node 306 can access device memory of a GPU within the heterogenous compute server node 306. For example, the memory server node 304 may provide remote direct memory access (RDMA) to the memory nodes 305, in which, for example, the CPU server node 308 may access memory resources on the memory server node 304 via the fabric 370 using DMA operations, in a similar manner as how the CPU would access its own onboard memory.
The memory server node 304 can be used by the heterogenous compute server node 306 and CPU server node 308 to expand the runtime memory that is available during memory-intensive activities such as the training of machine learning models. A tiered memory system can be enabled in which model data can be swapped into and out of the memory devices 318 of the heterogenous compute server node 306 to memory of the memory server node 304 at higher performance and/or lower latency than local storage (e.g., storage devices 316). During workload execution setup, the entire working set of data may be loaded into one or more of the memory nodes 305 of the memory server node 304 and loaded into the memory devices 318 of the heterogenous compute server node 306 as needed during execution of a heterogenous workload.
The storage server node 310 provides storage functionality to the heterogenous compute server node 306, the CPU server node 308, and potentially the memory server node 304. The storage server node 310 may provide a networked bunch of disks (JBOD), program flash memory (PFM), redundant array of independent disks (RAID), redundant array of independent nodes (RAIN), network attached storage (NAS), or other nonvolatile memory solutions. In one configuration, the storage server node 310 can couple with the heterogenous compute server node 306, the CPU server node 308, and/or the memory server node 304 such as NVMe-OF, which enables the NVME protocol to be implemented over the fabric 370. In such configurations, the fabric interface 372 of those servers may be smart interfaces that include hardware to accelerate NVMe-oF operations.
The accelerators 330 within the datacenter 300 can provide various accelerated functions, including hardware or coprocessor acceleration for functions such as packet processing, encryption, decryption, compression, decompression, network security, or other accelerated functions in the datacenter. In some examples, accelerators 330 may include deep learning accelerators, such as neural processing units (NPU), that can receive offload of matrix multiply operations of other neural network operations from the heterogenous compute server node 306 or the CPU server node 308. In some configurations, the accelerators 330 may reside in a dedicated accelerator server or distributed throughout the various server nodes of the datacenter 300. For example, an NPU may be directly attached to one or more CPU cores within the heterogenous compute server node 306 or the CPU server node 308. In some configurations, the accelerators 330 can include or be included within smart network controllers, infrastructure processing units (IPUs), or data processing units, which combine network controller functionality with accelerator, processor, or coprocessor functionality. The accelerators 330 can also include edge processing units (EPU) to perform real-time inference operations at the edge of the network.
In one configuration, the datacenter 300 can include gateways 340A-340B from the fabric 370 to other fabrics, fabric architectures, or interconnect technologies. For example, where the fabric 370 is an InfiniBand fabric, the gateways 340A-340B may be gateways to an Ethernet fabric. Where the fabric 370 is an Ethernet fabric, the gateways 340A-340B may include routers to route data to other portions of the datacenter 300 or to a larger network, such as the Internet. For example, a first gateway 340A may connect to a different network or subnet within the datacenter 300, while a second gateway 340B may be a router to the Internet.
The orchestrator 360 manages the provisioning, configuration, and operation of network resources within the datacenter 300. The orchestrator 360 may include hardware or software that executes on a dedicated orchestration server. The orchestrator 360 may also be embodied within software that executes, for example, on the CPU server node 308 that configures software defined networking (SDN) functionality of components within the datacenter 300. In various configurations, the orchestrator 360 can enable automated provisioning and configuration of components of the datacenter 300 by performing network resource allocation and template-based deployment. Template-based deployment is a method for provisioning and managing IT resources using predefined templates, where the templates may be based on standard templates required by the government, service provider, financial, standard or customer. The template may also dictate service level agreements (SLA) or service level obligations (SLO). The orchestrator 360 can also perform functionality including but not limited to load balancing and traffic engineering, network segmentation, security automation, real-time telemetry monitoring, and adaptive switching management, including telemetry-based adaptive switching. In some configurations, the orchestrator 360 can also provide multi-tenancy and virtualization support by enabling virtual network management, including the creation and deletion of virtual LANs (VLANs) and virtual private networks (VPNs), and tenant isolation for multi-tenant datacenters.
In various network configurations, the forwarding element is deployed as a non-edge forwarding element in the interior of the network to forward data messages from a source device to a destination device. In network configurations, the forwarding element 400 is deployed as an edge forwarding element at the edge of the network to connect to compute devices (e.g., standalone or host computers) that serve as sources and destinations of the data messages. As a non-edge forwarding element, the forwarding element 400 forwards data messages between forwarding elements in the network, such as through an intervening network fabric. As an edge forwarding element, the forwarding element 400 forwards data messages to and from edge compute devices to other edge forwarding elements and/or to non-edge forwarding elements.
The forwarding element 400 includes circuitry to implement a data plane 402 that performs the forwarding operations of the forwarding element 400 to forward data messages received by the forwarding element to other devices. The forwarding element 400 also includes circuitry to implement a control plane 404 that configures the data plane circuit. Additionally, the forwarding element 400 includes physical ports 406 that receive data messages from, and transmit data messages to, devices outside of the forwarding element 400. The data plane 402 includes ports 408 that receive data messages from the physical ports 406 for processing. The data messages are processed and forwarded to another port on the data plane 402, which is connected to another physical port of the forwarding element 400. In addition to being associated with physical ports of the forwarding element 400, some of the ports 408 on the data plane 402 may be associated with other modules of the data plane 402.
The data plane includes programmable packet processor circuits that provide several programmable message-processing stages that can be configured to perform the data-plane forwarding operations of the forwarding element 400 to process and forward data messages to their destinations. These message-processing stages perform these forwarding operations by processing data tuples (e.g., message headers) associated with data messages received by the data plane 402 in order to determine how to forward the messages. The message-processing stages include match-action units (MAUs) that try to match data tuples (e.g., header vectors) of messages with table records that specify action to perform on the data tuples. In some embodiments, table records are populated by the control plane 404 and are not known when configuring the data plane to execute a program provided by a network user. The programmable message-processing circuits are grouped into multiple message-processing pipelines. The message-processing pipelines can be ingress or egress pipelines before or after the forwarding element's traffic management stage that directs messages from the ingress pipelines to egress pipelines.
The specifics of the hardware of the data plane 402 depends on the communication protocol implemented via the forwarding element 400. Ethernet switches use application specific integrated circuits (ASICs) designed to handle Ethernet frames and the TCP/IP protocol stack. These ASICs are optimized for a broad range of traffic types, including unicast, multicast, and broadcast. Ethernet switch ASICs are generally designed to balance cost, power consumption, and performance, although high-end Ethernet switches may support more advanced features such as deep packet inspection and advanced QoS (Quality of Service). InfiniBand switches use specialized ASICs designed for ultra-low latency and high throughput. These ASICs enable features such as optimized for handling the InfiniBand protocol and provide support for RDMA and other features that require precise timing and high-speed data processing, although high-end Ethernet switches may support RoCE (RDMA over Converged Ethernet), which offers similar benefits to InfiniBand but with higher latency compared to native InfiniBand RDMA.
The forwarding element 400 may also be configured as an NVLink switch (e.g., NVSwitch), which is used to interconnect multiple graphics processors via the NVLink connection protocol. When configured as an NVLink switch, the forwarding element 400 can provide GPU servers with increased GPU to GPU bandwidth relative to GPU servers interconnected via InfiniBand. An NVLink switch can reduce network traffic hotspots that may occur when interconnected GPU-equipped servers execute operations such as distributed neural network training.
In general, where the data plane 402, in concert with a program executed on the data plane 402 (e.g., a program written in the P4 language), performs message or packet forwarding operations for incoming data, the control plane 404 determines how messages or packets should be forwarded. The behavior of a program executed on the data plane 402 is determined in part by the control plane 404, which populates match-action tables with specific forwarding rules. The forwarding rules that are used by the program executed on the data plane 402 are independent of the data plane program itself. In one configuration, the control plane can couple with a management port 410 that enables administrator configuration of the forwarding element 400. The data connection that is established via the management port 410 is separate from the data connections for ingress and egress data ports. In one configuration, the management ports 410 may connect with a management plane 405, which facilitates administrative access to the device, enables the analysis of device state and health, and enables device reconfiguration. The management plane 405 may be a portion of the control plane 404 or in direct communication with the control plane 404. In one implementation, there is no direct access for the administrator to components of the control plane 404. Instead, information is gathered by the management plane 405 and the changes to the control plane 404 are carried out by the management plane 405.
The switches 432A-432E include a data plane 402, a control plane 404, a management plane 405, and physical ports 406, as in the forwarding element 400 of
An adaptive routing (AR) event may be detected by one of the switches along a route that becomes compromised, for example, when the switch when it attempts to output packets on a designated output port. For example, an exemplary data from the source node 422 to the destination node 442 can traverse links through switches of the network. An AR event may be detected by switch 432D for link 429B, for example, in response to congestion or a link fault associated with link 429B. Upon detecting the AR event, switch 432D, as the detecting switch, generates an adaptive routing notification (ARN), which has an identifier that distinguishes an ARN packet from other packet types. In various embodiments, the ARN includes parameters such as an identifier for the detecting switch, the type of AR event, and the source and destination address of the flow that triggered the AR event, and/or any other suitable parameters. The detecting switch sends the ARN backwards along the route to the preceding switches. The ARN may include a request for notified switches to modify the route to avoid traversal of the detected switch. A notified switch can then evaluate whether its routes may be modified to bypass the detecting switch. Otherwise, the switch forwards the ARN to the previous preceding switch along the route. In this scenario, switch 432B is not able to avoid switch 432D and will relay the ARN to switch 432A. Switch 432A can determine to adapt the route to the destination node 442 by using link 427A to switch 432C. Switch 432C can reach switch 432E via link 429A, allowing packets from the source node 422 to reach the destination node 442 while bypassing the AR event related to link 429B.
In various configurations, the network 420 can also adapt to congestion scenarios via programmable data planes within the switches 432A-432E that are able to execute data plane programs to implement in-network congestion control algorithms (CCAs) for TCP over Ethernet-based fabrics. Using in-band network telemetry (INT), programmable data planes within the switches 432A-432E can become aware when a port or link along a route is becoming congested and preemptively seek to route packets over alternate paths. For example, switch 432A can load balance traffic to the destination node 442 between link 427A and link 427B based on the level of congestion seen on the routes downstream from those links.
The local memory 456 includes multiple queues, including an outer receive queue 462, an outer transmit queue 463, an inner receive queue 464, and an inner transmit queue 465. The outer queues are used for data that is received at a given multi-port IB interface that is to be forwarded back out the same multi-port IB interface. The inner queues are used for data that is forwarded out a different multi-port IB interface than used to receive the data. Other types of queue configurations may be implemented in local memory 456. For example, different queues may be present to support multiple traffic classes, either on an individual port basis, shared port basis, or a combination thereof. The multi-port IB interfaces 460A-460D includes power management circuitry 455, which can adjust a power state of circuitry within the respective multi-port IB interface. Additionally power management logic that performs similar operations may be implemented as part of core switch logic.
The multi-port IB interfaces 460A-460D include packet processing and switching logic 458, which is generally used to perform aspects of packet processing and/or switching operations that are performed at the local multi-port level rather than across the IB switch as a whole. Depending on the implementation, the packet processing and switching logic 458 can be configured to perform a subset of the operations of the packet processing and switching logic 478 within the core switch logic 480, or can be configured with the full functionality of the packet processing and switching logic 478 within the core switch logic 480. The processing functionality of the packet processing and switching logic 458 may vary, depending on the complexity of the operations and/or speed the operations are to be performed. For example, the packet processing and switching logic 458 can include processors ranging from microcontrollers to multi-core processors. A variety of types or architectures of multi-core processors may also be used. Additionally, a portion of the packet processing operations may be implemented by embedded hardware logic.
The core switch logic 480 includes a crossbar 482, memory 470, a subnet management agent (SMA 476), and packet processing and switching logic 478. The crossbar 482 is a non-blocking low latency crossbar that interconnects the multi-port IB interfaces 460A-460D and connects with the memory 470. The memory 470 includes receive queues 472 and transmit queues 474. In one embodiment, packets to be switched between the multi-port IB interfaces 460A-460D can be received by the crossbar 482, stored in one of the receive queues 472, processed by the packet processing and switching logic 478, and stored in a transmit queues 474 for transmission to the outbound multi-port IB interface. In implementations that do not use the multi-port IB interfaces 460A-460D, the core switch logic 480 and crossbar 482 switches packets directly between I/O buffers with the receive queues 472 and transmit queues 474 within the memory 470.
The packet processing and switching logic 478 includes programmable functionality and can execute data plane programs via a variety of types or architectures of multi-core processors. The packet processing and switching logic 478 is representative of the applicable circuitry and logic for implementing switching operations, as well as packet processing operations beyond which may be performed at the ports themselves. Processing elements of the packet processing and switching logic 478 executes software and/or firmware instructions configured to implement packet processing and switch operations. Such software and/or firmware may be stored in non-volatile storage on the switch itself. The software may also be downloaded or updated over a network in conjunction with initializing operations of the InfiniBand switch 450.
The SMA 476 is configurable to manage, monitor, and control functionality of the InfiniBand switch 450. The SMA 476 is also an agent of and in communication of the subnet manager (SM) for the subnet associated with the InfiniBand switch 450. The SM is the entity that discovers the devices within the subnet and performs a periodic sweep of the subnet to detect changes to the subnet's topology. One SMA within a subnet can be elected the primary SMA for the subnet and act as the SM. Other SMAs within the subnet will then communicate with that SMA. Alternatively, the SMA 476 can operate with other SMAs in the subnet to act as a distributed SM. In some embodiments, SMA 476 includes or executes on standalone circuitry and logic, such as a microcontroller, single core processor, or multi-core processor. In other embodiments, SMA 476 is implemented via software and/or firmware instructions executed on a processor core or other processing element that is part of a processor or other processing element used to implement packet processing and switching logic 478.
Embodiments are not specifically limited to implementations including multi-port IB interfaces 460A-460D. In one embodiment, ports are associated with their own receive and transmit buffers, with the crossbar 482 being configured to interconnect those buffers with receive queues 472 and transmit queues 474 in the memory 470. Packet processing and switching is then primarily performed by the packet processing and switching logic 478 of the core switch logic 480.
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In various configurations, the network interface device 500 is configurable to interface with networks including but not limited to Ethernet, including Ultra Ethernet. However, the network interface device 500 may also be configured as an InfiniBand or NVLink interface via the modification of various components. For example, the transceiver 502 can be capable of receiving and transmitting packets in conformance with the InfiniBand, Ethernet, or NVLink protocols. Other protocols may also be used. The transceiver 502 can receive and transmit packets from and to a network via a network medium. The transceiver 502 can include PHY circuitry 514 and media access control circuitry (MAC circuitry 516). PHY circuitry 514 can include encoding and decoding circuitry to encode and decode data packets according to applicable physical layer specifications or standards. MAC circuitry 516 can be configured to assemble data to be transmitted into packets, that include destination and source addresses along with network control information and error detection hash values.
The SoC/SIP 545 can include processors that may be any a combination of a CPU processor, graphics processing unit (GPU), field programmable gate array (FPGA), application specific integrated circuit (ASIC), or other programmable hardware device that allow programming of network interface device 500. For example, a smart network interface can provide packet processing capabilities in the network interface using processors 505. Configuration of operation of processors 505, including programmable data plane processors, can be programmed using Programming Protocol-independent Packet Processors (P4), C, Python, Broadcom Network Programming Language (NPL), x86, or ARM compatible executable binaries or other executable binaries.
The packet allocator 524 can provide distribution of received packets for processing by multiple CPUs or cores using timeslot allocation. An interrupt coalesce circuit 522 can perform interrupt moderation in which the interrupt coalesce circuit 522 waits for multiple packets to arrive, or for a time-out to expire, before generating an interrupt to host system to process received packet(s). Receive Segment Coalescing (RSC) can be performed by the network interface device 500 in which portions of incoming packets are combined into segments of a packet. The network interface device 500 can then provide this coalesced packet to an application. A DMA engine 526 can copy a packet header, packet payload, and/or descriptor directly from host memory to the network interface or vice versa, instead of copying the packet to an intermediate buffer at the host and then using another copy operation from the intermediate buffer to the destination buffer. The memory 510 can be any type of volatile or non-volatile memory device and can store any queue or instructions used to program the network interface device 500. The transmit queue 507 can include data or references to data for transmission by network interface. The receive queue 508 can include data or references to data that was received by network interface from a network. The descriptor queues 520 can include descriptors that reference data or packets in transmit queue 507 or receive queue 508. The bus interface 512 can provide an interface with host device. For example, the bus interface 512 can be compatible with PCI Express, although other interconnection standards may be used.
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While the illustrated implementation of the network interface device 550 is shown as having a PCIe interface 558, other implementations can use other interfaces. For example, the network interface device 550 may use an Open Compute Project (OCP) mezzanine connector. Additionally, the PCIe interface 558 may also be configured with a multi-host solution that enables multiple compute or storage hosts to couple with the network interface device 550. The PCIe interface 558 may also support technology that enables direct PCIe access to multiple CPU sockets, which eliminates the need for network traffic to traverse the inter-processor bus of a multi-socket server motherboard for a server that includes the network interface device 550.
The network interface device 550 implements endpoint elements of the InfiniBand architecture, which is based around queue pairs and RDMA. InfiniBand off-loads traffic control from software through the use of execution queues (e.g., work queues), which are initiated by a software client and managed in hardware. Communication endpoints includes a queue pair (QP) having a send queue and a receive queue. A QP is a memory-based abstraction where communication is achieved between memory-to-memory transfers between applications or between applications and devices. Communication to QPs occurs through virtual lanes of the network ports 552A-552B, which enable multiple independent data flows to share the same link, with separate buffering and flow control for respective flows.
Communication occurs via channel I/O, in which a virtual channel directly connects two applications that exist in separate address spaces. The hardware transport engine 560 includes hardware logic to perform transport level operations via the QP for an endpoint. The RDMA engine 562 leverages the hardware transport engine 560 to perform RDMA operations between endpoints. The RDMA engine 562 implements RDMA operations in hardware and enables an application to read and write the memory of a remote system without OS kernel intervention or unnecessary data copies by allowing one endpoint of a communication channel to place information directly into the memory of another endpoint. The virtual endpoint logic 564 manages the operation of a virtual endpoint for channel I/O, which is a virtual instance of a QP that will be used by an application. The virtual endpoint logic 564 maps the QPs into the virtual address space of an application associated with a virtual endpoint.
Congestion control logic 563 performs operations to mitigate the occurrence of congestion on a channel. In various implementations, the congestion control logic 563 can perform flow control over a channel to limit congestion at the destination of a data transfer. The congestion control logic 563 can perform link level flow control to manage congestion at source congestion at virtual links of the network ports 552A-552B. In some implementations, the congestion control logic can perform operations to limit congestion at intermediate points (e.g., IB switches) along a channel.
Offload engines 566 enable the offload of network tasks that may otherwise be performed in software to the network interface device 550. The offload engines 566 can support offload of operations including but not limited to offload of receive side scaling from a device driver or stateless network operations, for example, for TCP implementations over InfiniBand, such as TCP/UDP/IP stateless offload or VXLAN offload. The offload engines 566 can also implement operations of a interrupt coalesce circuit 522 of the network interface device 500 of
The QoS logic 568 can perform QoS operations, including QoS functionality that is inherent within the basic service delivery mechanism of InfiniBand. The QoS logic 568 can also implement enhanced InfiniBand QoS, such as fine grained end-to-end QoS. The QoS logic 568 can implement queuing services and management for prioritizing flows and guaranteeing service levels or bandwidth according to flow priority. For example, the QoS logic 568 can configure virtual lane arbitration for virtual lanes of the network ports 552A-552B according to flow priority. The QoS logic 568 can also operate in concert with the congestion control logic 563.
The GSA/SMA logic 569 implements general services agent (GSA) operations to manage the network interface device 550 and the InfiniBand fabric, as well as performing subnet management agent operations. The GSA operations include device-specific management tasks, such as querying device attributes, configuring device settings, and controlling device behavior. The GSA/SMA logic 569 can also implement SMA operations, including a subset of the operations performed by the SMA 476 of the InfiniBand switch 450 of
The management interface 570 provides support for a hardware interface to perform out-of-band management of the network interface device 550, such as an interconnect to a board management controller (BMC) or a hardware debug interface.
In one embodiment, access to remote storage containing model data can be accelerated by the programmable network interface 600. For example, the programmable network interface 600 can be configured to present remote storage devices as local storage devices to the host system. The programmable network interface 600 can also accelerate RDMA operations performed between GPUs of the host system with GPUs of remote systems. In one embodiment, the programmable network interface 600 can enable storage functionality such as, but not limited to NVME-OF. The programmable network interface 600 can also accelerate encryption, data integrity, compression, and other operations for remote storage on behalf of the host system, allowing remote storage to approach the latencies of storage devices that are directly attached to the host system.
The programmable network interface 600 can also perform resource allocation and management on behalf of the host system. Storage security operations can be offloaded to the programmable network interface 600 and performed in concert with the allocation and management of remote storage resources. Network-based operations to manage access to the remote storage that would otherwise by performed by a processor of the host system can instead be performed by the programmable network interface 600.
In one embodiment, network and/or data security operations can be offloaded from the host system to the programmable network interface 600. Data center security policies for a data center node can be handled by the programmable network interface 600 instead of the processors of the host system. For example, the programmable network interface 600 can detect and mitigate against an attempted network-based attack (e.g., DDoS) on the host system, preventing the attack from compromising the availability of the host system.
The programmable network interface 600 can include a system on a chip (SoC/SIP 620) that executes an operating system via multiple processor cores 622. The processor cores 622 can include general-purpose processor (e.g., CPU) cores. In one embodiment the processor cores 622 can also include one or more GPU cores. The SoC/SIP 620 can execute instructions stored in a memory device 640. A storage device 650 can store local operating system data. The storage device 650 and memory device 640 can also be used to cache remote data for the host system. Network ports 660A-660B enable a connection to a network or fabric and facilitate network access for the SoC/SIP 620 and, via the host interface 670, for the host system. In one configuration, a first network port 660A can connect to a first forwarding element, while a second network port 660B can connect to a second forwarding element. Alternatively, both network ports 660A-660B can be connected to a single forwarding element using a link aggregation protocol (LAG). The programmable network interface 600 can also include an I/O interface 675, such as a USB interface. The I/O interface 675 can be used to couple external devices to the programmable network interface 600 or as a debug interface. The programmable network interface 600 also includes a management interface 630 that enables software on the host device to manage and configure the programmable network interface 600 and/or SoC/SIP 620. In one embodiment the programmable network interface 600 may also include one or more accelerators or GPUs 645 to accept offload of parallel compute tasks from the SoC/SIP 620, host system, or remote systems coupled via the network ports 660A-660B. For example, the programmable network interface 600 can be configured with a graphics processor and participate in general-purpose or graphics compute operations in a datacenter environment.
One or more aspects may be implemented by representative code stored on a machine-readable medium which represents and/or defines logic within an integrated circuit such as a processor. For example, the machine-readable medium may include instructions which represent various logic within the processor. When read by a machine, the instructions may cause the machine to fabricate the logic to perform the techniques described herein. Such representations, known as “IP cores,” are reusable units of logic for an integrated circuit that may be stored on a tangible, machine-readable medium as a hardware model that describes the structure of the integrated circuit. The hardware model may be supplied to various customers or manufacturing facilities, which load the hardware model on fabrication machines that manufacture the integrated circuit. The integrated circuit may be fabricated such that the circuit performs operations described in association with any of the embodiments described herein.
The RTL design 715 or equivalent may be further synthesized by the design facility into a hardware model 720, which may be in a hardware description language (HDL), or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design can be stored for delivery to a fabrication facility 765 using non-volatile memory 740 (e.g., hard disk, flash memory, or any non-volatile storage medium). The fabrication facility 765 may be a 3rd party fabrication facility. Alternatively, the IP core design may be transmitted (e.g., via the Internet) over a wired connection 750 or wireless connection 760. The fabrication facility 765 may then fabricate an integrated circuit that is based at least in part on the IP core design. The fabricated integrated circuit can be configured to perform operations in accordance with at least one embodiment described herein.
AI deployments continue to grow and scale as models get larger with increasing numbers of parameters. As the amount of real-time data increases with usages like smart cars, smart sensors, etc., the amount of data that needs to be accommodated in RAG and RAG-like setups will significantly increase. This increase in the amount of data puts significant pressure on the infrastructure to manage the large amounts of data, including sharding and replication.
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Techniques known in the art manage the data and data infrastructure of the system 800 shown in
Techniques described herein may help address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device (e.g., IPU, DPU, EPU, Smart NIC) as described herein. Programmable network interface devices are uniquely positioned as a distinct failure domains that can execute independently of host processors of a node. A programmable network interface device of a node can continue to function through a software or hardware failure of host processor on that node and may continue to function while the host environment is reset or recovered. Programmable network interface devices are closely coupled with the network and can be configured to manage replicas, provide a unified front-end, track heartbeats, load balance, mitigate node failures, and manage recovery and migration as circumstances dictate.
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The system 900 implements mechanisms via the IPU 906 of the head nodes 902A-902F to manage high availability and data replication of distributed AI software, such as sharded vector database. The IPU 906 within the head nodes 902A-902F is positioned with close access to the network 908, accelerators (e.g., GPU array 904), and host cores within the head nodes. In one configuration, the head nodes 902A-902F include multiple host cores, with multiple host cores connected to the IPU 906 within a head node. The head nodes 902A-
Functionality of the IPU 906 within head node 902E is shown in detail. The illustrated functionality can be implemented in whole or in part by the IPU 906 within any or all of the head nodes 902A-902F, depending on the functionality tasked to those nodes. The IPU 906 can provide a unified front-end service of an inference engine by orchestrating critical operational tasks. The IPU 906 is configurable to manages replicas, track heartbeats, predict host node failures, and manage recovery and migration via P4 programmable data plane circuitry. The IPU 906 manages database shards, replicas of AI models, and vector database replicas across the infrastructure, facilitating high availability and fault tolerance. The IPU 906 monitors the health of system components by tracking heartbeats and telemetry, enabling the IPU 906 to detect and respond to anomalies. The IPU 906 implements logic to load balance capabilities, optimize distribution of inference requests, prevent bottlenecks, and facilitates efficient resource utilization. In the event of the failure of a node, the IPU 906 attempts to proactively mitigate the impact of that failure by initiating failover procedures to maintain uninterrupted service. The IPU 906 also oversees the recovery and migration processes to enable AI services to adapt to changes in the infrastructure without compromising performance or data integrity. This orchestration by the IPU 906 enables robust, scalable AI deployments. For failed nodes, after the migration, the failing node can be examined and based on the results, the node can be placed back into service, repurposed to lower priority tasks, or scheduled for maintenance or replacement.
Vector database acceleration and high availability logic is implemented via hardware and/or firmware, a programmable data plane, and/or software executed via processor cores within the IPU 906. In one embodiment, the logic includes replica and redundancy execution tracker 910, a failure predictor 912, a per-GPU domain execution tracker 914, heartbeat logic 916, migration logic 918, recovery logic 920, and error correction logic 922.
The replica and redundancy execution tracker 910 tracks the location of replicas across a deployment with the goal of maintaining sufficient rack, data center, or geographic level redundancy for those replicas. The replica and redundancy execution tracker 910 can track, for replicas, a replica ID/address, a sibling replica ID/address, a replica network node, the heartbeat outcome for the replica, a last failure time and recovery, and the current probability of failure for the replica.
The failure predictor 912 tracks a set of telemetry metrics to maintain a running failure predictor. The failure predictor 912 tracks network and device telemetry including but not limited to a number of correctable errors corrected by a memory controller of a node, temperature metrics for a node, or other hardware metrics that may indicate an impending device failure. The failure predictor 912 can also track network telemetry to determine whether a potential node failure may occur due to the failure of the IPU 906 of the node. When the value of the failure predictor exceeds a threshold, policy-based corrective, mitigation, or migration actions can be taken. The policy actions may include creating an additional replica to ensure probabilistic coverage or migrating data of the node to a different domain.
The per-GPU domain execution tracker 914 tracks load on GPUs and other relevant accelerator devices (e.g., NPUs, AI accelerators, etc.) in a head node. These metrics are a relevant factor for consideration when determining which shards to use for a given task. For example, inference requests can be routed to different accelerator devices on a node based on the current load distribution across the accelerator devices. In one embodiment, the IPU 906 is configured to route inference requests to remote accelerators or remote accelerator nodes. The per-GPU domain execution tracker 914 enables the IPU 906 to route the inference requests to remote accelerators or remote accelerator nodes based on the load distribution across the remote accelerators or remote accelerator nodes.
The heartbeat logic 916 within an IPU associated with a database shard exchanges heartbeats with other IPUs that are attached to replicas of a given shard. The heartbeat logic 916 can generate a heartbeat message or ping and transmit that message to the relevant IPUs and monitor the return status for those messages. The heartbeat logic 916 within the various IPUs can exchange the determined heartbeat status data. This heartbeat exchange provides regular confirmation that the other nodes are up and reachable with reasonable delays. In one embodiment, the heartbeat logic 916 is implemented via a programmable data plane of the IPU 906.
The migration logic 918 is activated when the failure of a node is imminent based on a computed probability or in the event of an actual failure condition in which data of the node is still accessible. The migration logic 918 can facilitate migration without downtime by initiating a copy operation to a new node while tracking changes that occur during the copy. When the copy is completed, a transaction handover to the new node can occur.
The recovery logic 920 is activated to perform node recovery. If a node resets, recovers from a failure, or when a new node comes online, previous state for the node may be recoverable from the IPU of the node. The node is recovered using state information stored on the IPU of the node, along with updates from the other IPUs hosting shards for the task being processed.
The error correction logic 922 is activated when the IPU detects errors. Those errors can be corrected via application level programmed logic on the IPU. For example, shard-level checksums can be stored, exchanged, and propagated to account for and correct network or other errors.
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Endpoint H1 may include a segment of a vector database and endpoint H2 may include a replica of that segment. The forwarding elements 954A-954C may include but are not limited to a switch, a switch chip, a router, or a bridge. The structure of the system 950 is exemplary and not limiting as to any particular embodiments described herein. In one embodiment, the system 950 is a subsystem of the system 900 of
During operation, endpoint H1 can transmit a data packet 953A addressed to the second endpoint H2 to FE1954A. FE1954A is an INT source, which inserts an INT header and adds metadata related to its own element ID (e.g., switch ID) and forwarding delay before forwarding a data packet 953B to FE2954B, which is an INT transit element. FE2954B appends its own INT metadata and forwards a data packet 953C to FE3954C. FE3954C is an INT sink, which appends its own INT metadata and then makes a copy of the data packet 953D with all the collected INT metadata and forwards this data packet 953D to a failure predictor 912 for analysis. As the INT sink, FE3954C also removes the INT header and metadata to recover the original instance of the data packet 953A. FE3954C then forwards the data packet 953A to the second endpoint H2 (host 952B).
The data packet 953D that is forwarded to the failure predictor 912 includes an INT metadata stack 955 that includes the forward element IDs and latency for hops along the path between endpoints. The INT metadata stack 955 includes information that can be used by the failure predictor 912 to monitor the health and performance of the network within the system 950 in real time.
The programmable network interface device 1000 includes a network subsystem 1010 that enables network interface functionality and a compute complex 1030 that enables program execution capability. The network subsystem 1010 includes host interface SerDes 1011 (serializer/deserializer) circuitry configurable for coupling with a host interconnect (e.g., PCIe). The network subsystem 1010 also includes a network interface SerDes 1028 circuitry and network media access control (MAC) circuitry configurable for coupling with a physical interface of a network.
The host interface SerDes 1011 couples with circuitry to provide virtual functions (VFs 1012) and physical functions (PFs 1013) for Single Root I/O Virtualization (SR-IOV) and Scalable I/O Virtualization (SIOV). Multiple instances of the PFs 1013 enable concurrent use of the programmable network interface device 1000 by multiple host processors and/or multiple physical hosts, which can virtualize the programmable network interface device 1000 via the VFs 1012 associated with the respective instances of the PFs 1013.
The programmable network interface device 1000 includes RDMA circuitry 1014 to accelerate RDMA operations and NVME circuitry 1016 to provide an NVME device interface for NVME-OF devices. LAN circuitry 1018 accelerates local area network functionality and couples with a packet processing pipeline 1020, which in one embodiment is a P4 programmable pipeline. Inline cryptographic circuitry 1022 enables wire-speed packet encryption and decryption, for example, for Internet Protocol Security (IPsec) protocols and/or VPN functionality, and traffic shaper 1024 circuitry enables traffic shaping via transmit scheduling.
The compute complex 1030 includes a processor core array 1032 that can execute infrastructure software directly on the programmable network interface device 1000, enabling such functionality to be offloaded from host processors. The processor core array 1032 couples with a system cache 1033 that is backed by multiple channels of memory. A lookaside cryptographic and compression engine 1036 provides cryptographic and compression acceleration functionality to the processor core array 1032 and to host processors. Additionally, management complex circuitry 1038 includes a dedicated management processor or microcontroller that provides secure boot and life cycle management functionality and enables the remote management of the programmable network interface device 1000.
In one embodiment, the management processor within the management complex circuitry 1038 can configure the execution of vector database accelerator logic 1040 via one or more processor cores of the processor core array 1032. The vector database accelerator logic 1040 is configurable to execute program code to provide at least a portion of the functionality of the system 900 of
In one embodiment, the system 1100 can replicate software and data of the system 900 of
In one embodiment, the active IPU 1000A and the standby IPU 1000B respectively include flexible pipeline receive circuitry (RX 1110) and flexible pipeline receive transmission circuitry (TX 1120). The RX 1110 circuitry includes elastic network interface (ENI) direction and lookup logic 1111, overlay routing logic 1112, ACL policy lookup logic 1114. The RX 1110 circuitry also include connection tracking and TCP state machine logic 1116 and high availability logic 1118, with manage a flow table 1125A of the active IPU 1000A. The high availability logic 1118 is configured to replicate updates to the flow table 1125A of the active IPU 1000A to the standby flow table 1125B of the standby IPU 1000B. In response to an update to the flow table 1125A, the high availability logic 1118 can transmit an update data packet 1102 via underlay routing circuitry 1121 of the TX 1120 circuitry. The update data packet 1102 is processed by the RX 1110 circuitry of the standby IPU 1000B and recognized as an HA packet. The standby IPU 1000B uses data of the update data packet 1102 to update the standby flow table 1125B. HA logic of the standby IPU 1000B can end an acknowledgement data packet 1104 back to the active IPU 1000A to acknowledge the update.
In one embodiment, a control plane configuration API is provided to enable scope and role definition for active and standby devices. This APU enables the active IPU 1000A to declare and configure itself as active and to specify a standby IPU 1000B to which migration and flow data will be replicated. When a standby IPU 1000B is defined for an active IPU 1000A, state, configuration data, and the flow table 1125A of the active IPU 1000A is applied to the standby IPU 1000B, causing the standby IPU 1000B to become a replica of the active IPU 1000A. Configuration and flow update events that occur on the active IPU 1000A (e.g., flow add, flow delete) are translated into network messages and transmitted in-band to the standby IPU 1000B. In one embodiment, message are transmitted using a reserved layer 4 (e.g., transport layer) UDP port. In one embodiment, the messages include a header or identifier that signifies that the message includes flow events that are replicated from the active IPU 1000A. In one embodiment, flow events between the active IPU 1000A and the standby IPU 1000B are transmitted over a pre-determined VLAN. In such embodiment, the messages have a VLAN tag of the pre-determined VLAN.
In one embodiment, aspects of the system 1100 may be included within a software for open networking in the cloud (SONiC) disaggregated APIs for SONiC hosts (DASH) implementation to facilitate high availability for cloud applications. In one embodiment, the active IPU 1000A resides in a first host, the standby IPU 1000B resides in a second host, and network traffic between the active IPU 1000A and the standby IPU 1000B traverses at least one forwarding element. For example, the system 1100 may reside within the system 950 of
The infrastructure management circuitry can monitor a status of a first node associated with a database shard of a vector database (1204). The infrastructure management circuitry can additionally monitor status of respective replicas of a plurality of replicas of the first node and/or a second node via heartbeat data and/or telemetry data. The heartbeat data indicates a network availability of the respective replicas and the telemetry data includes in-band network telemetry generated via forwarding elements between the network interface and the node. The telemetry data can also include hardware metrics associated with the node, including hardware metrics that indicate a probability of failure associated with the nodes. The infrastructure management circuitry can determine a failure probability associated with the first node (1206). The infrastructure management circuitry can configure a query for data of the first node to be serviced via a replica of the first node in response to a determination that the failure probability exceeds a threshold (1208).
Techniques described herein address the above challenges that arise when using host executed software to manage vector databases by providing a vector database accelerator and shard management offload logic that is implemented within hardware and by software executed on device processors and programmable data planes of a programmable network interface device.
One embodiment provides a device comprising a network interface, packet processing circuitry coupled with the network interface, a host interface coupled with the packet processing circuitry and the network interface, the host interface including circuitry to enable access to a physical function, and infrastructure management circuitry coupled with the network interface and the host interface and accessible via the physical function. The infrastructure management circuitry is configured to facilitate data access for a neural network inference engine having a distributed data model including a plurality of distributed data shards via dynamic and/or real-time management of a node associated with the neural network inference engine, the node including a database shard of a vector database.
In one embodiment, the infrastructure management circuitry monitors node status using heartbeat or telemetry data, calculates a failure probability for the node based on this status, and, if the failure probability exceeds a threshold, configures data queries to be served through a data replica. Additionally, in cases where a failure probability is determined to be high, the circuitry can initiate live data migration to create this data replica. The heartbeat data provides insight into the network availability of the node, while telemetry data includes in-band network telemetry from forwarding elements between the network interface and the node, as well as hardware metrics associated with the node. In one embodiment, the hardware metrics relate to an accelerator device that processes inference requests from the neural network inference engine.
In one embodiment, the infrastructure management circuitry is configured to identify a remote network interface device to configure as a standby network interface device and replicate a network flow configuration associated with the packet processing circuitry to the standby network interface device. The infrastructure management circuitry is configurable to receive an event including an adjustment to a network flow configuration associated with the packet processing circuitry, translate the event into a network message including the adjustment, and transmit the network message to the standby network interface device.
One embodiment provides a method comprising providing access to a physical function of a programmable network interface device via a host interface. The programmable network interface device including a network interface and packet processing circuitry coupled with the network interface. The physical function to enable access to infrastructure management circuitry coupled with the network interface and the host interface. The method additionally comprises monitoring, via the infrastructure management circuitry, status of a first node associated with a database shard of a vector database, determine a failure probability associated with the first node, and configuring a query for data of the first node to be serviced via a replica of the first node in response to a determination that the failure probability exceeds a threshold.
In one embodiment, the method additionally comprises receiving request from a neural network inference engine for access to data associated with a second node, selecting one of a plurality of replicas of the second node, and transmitting a request for the data associated with the second node to a selected replica of the second node. The method may additionally comprise monitoring, via the infrastructure management circuitry a status of respective replicas of the plurality of replicas of the second node via heartbeat data and/or telemetry data. The heartbeat data can indicate a network availability of the second node and/or its respective replicas and the telemetry data includes in-band network telemetry generated via forwarding elements between the network interface and the second node and/or its respective replicas. The telemetry data may additionally or alternatively include hardware metrics associated with the second node and/or its respective replicas. In one embodiment, any aspects of the method described above may be implemented by a system comprising means to perform the operations of the method. Additionally a non-transitory machine readable medium may store instructions to cause a processor to perform aspects of the method described above.
One embodiment provides a system comprising a memory device, a first host processor coupled with the memory device, and a second host processor coupled with the memory device. The system additionally includes a first network interface device including a first network interface, first packet processing circuitry coupled with the first network interface, and a host interface including first circuitry configured to provide access to a first physical function and second circuitry configured to provide access to a second physical function. The first host processor is coupled with the first network interface device via the first physical function and the second host processor is coupled with the first network interface device via the second physical function. The system additionally includes third circuitry configured to identify a second network interface device to configure as a standby network interface device and replicate a network flow configuration associated with the first packet processing circuitry to the second network interface device.
In one embodiment, the third circuitry is configured to receive an event including an adjustment to a network flow configuration associated with the first packet processing circuitry, translate the event into a network message including the adjustment, and transmit the network message to the second network interface device. The second network interface device is configurable to receive the network message, determine that the network message includes the adjustment, and apply the adjustment to a flow table associated with second packet processing circuitry within the second network interface device. In one embodiment, the second network interface device is to determine that the network message includes the adjustment based on an identifier associated with the network message and/or a port associated with the network message. The first packet processing circuitry and the second packet processing circuitry include programmable packet processor circuits.
References in the specification to “one embodiment,” “an embodiment,” “an illustrative embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may or may not necessarily include that particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Additionally, it should be appreciated that items included in a list in the form of “at least one A, B, and C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly, items listed in the form of “at least one of A, B, or C” can mean (A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and C).
The disclosed embodiments may be implemented, in some cases, in hardware, firmware, software, or any combination thereof. The disclosed embodiments may also be implemented as instructions carried by or stored on a transitory or non-transitory machine-readable (e.g., computer-readable) storage medium, which may be read and executed by one or more processors. A machine-readable storage medium may be embodied as any storage device, mechanism, or other physical structure for storing or transmitting information in a form readable by a machine (e.g., a volatile or non-volatile memory, a media disc, or other media device). This machine-readable storage medium may have instructions stored thereon, which when executed cause one or more processors to perform operations described herein.
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. In some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features.
The foregoing description and drawings are to be regarded in an illustrative rather than a restrictive sense. Persons skilled in the art will understand that various modifications and changes may be made to the embodiments described herein without departing from the broader spirit and scope of the features set forth in the appended claims.
