High beta output stage for high speed operational amplifier

Abstract

The present invention provides an high beta, high speed operational amplifier output stage (100). The advantages of the operational amplifier output stage over conventional methods disclosed is up to β2 rather than a single beta. The present invention achieves this using an pre-driver sub-stage (122) having a plurality of translinear loops so that there is no net signal loss to the final sub-stage (123). The output of the disclosed operational amplifier output stage takes the form:

Description

TECHNICAL FIELD OF THE INVENTION

[0001] This invention generally relates to electronic systems and in particular to operational amplifier output stages.

BACKGROUND OF THE INVENTION

[0002] Operational amplifiers are used in many electronic circuits to condition, manipulate and amplify signals. The operating characteristics of a particular operational amplifier are dependent upon its circuit topology. Generally, the operational amplifier consists of a number of stages, each containing internal sub-stages.

[0003] Two important operating characteristics of an operational amplifier are its amplification characteristics and its speed. High beta (β) and high speed are desirable in operational amplifiers that have a variety of application, including DSL Drivers. Beta (β) refers to the ratio of DC collector current to DC base current in a bipolar junction transistor or current gain from base to collector. β is very important parameter that varies with collector current temperature.

SUMMARY OF THE INVENTION

[0004] The present invention achieves technical advantages as a high β, high speed operational amplifier output stage using a localized feedback system in which current gains are close to βn*βp, where βn refers to the beta of either the pre-driver npn transistor, output driver npn transistor or an average of both, depending on the current signal and βp refers to the beta of either the pre-driver pnp transistor, output pnp transistor or an average of both. Where signal current is large and positive, load conduction is through the output npn transistor and pre-driver pnp transistor. Where signal current is large and negative, load conduction is through the pre-driver npn transistor and output pnp transistor. Where the signal is small, load conduction varies in tandem through the output npn transistors and pre-diver pnp transistor and the output pnp transistor and pre-driver npn transistor.

[0005] The output stage can be seen to comprise a pre-driver sub-stage and final sub-stage. The pre-driver sub-stage is further comprised of a first and a second pre-driver sub-stage circuit. In addition, the final sub-stage is further comprised of a first and a second final sub-stage circuit. The input to the present invention comprises a transconductance (“gm”) cell which, when a voltage is applied thereto, an error voltage appears across the input gm cell and an error current is produced at the output of the input gm cell. The error current (δIin) flows into the emitters of two pre-driver sub-stage transistors and flows out of their collectors into the bases of two other pre-driver transistors. Through this translinear loop, no net signal is lost. The gained up error currents then flow into the final sub-stage translinear loop, specifically, into the bases of two final sub-stage transistors. Effectively, in the small signal context, the first pre-driver sub-stage circuit amplifies a positive portion of the current signal for output to the first final sub-stage circuit while the second pre-driver sub-stage circuit amplifies a negative portion of the current signal for output to the second final sub-stage circuit. The first and second final sub-stages further amplify the positive portion and negative portion, respectively, of the current signal.

[0006] The first and second final sub-stage circuits are interconnected at an output terminal of the operational amplifier output stage such that the amplified positive portion of the signal and amplified negative portion of the signal are joined substantially in phase, in the form δIo≈Bn*Bp*δIin. By feeding back a portion of the output signal using a variety of feedback principles, speed characteristics can be further improved.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] For a more complete understanding of the present invention, reference is made to the detailed description taken in conjunction with the following drawings:

[0008] FIG. 1 is a circuit diagram of a first conventional operational amplifier output stage;

[0009] FIG. 2 is a circuit diagram of a second conventional operational amplifier output stage;

[0010] FIG. 3 is a graph illustrating the linearity characteristics of the first conventional operational amplifier. This figure shows the first derivative (δVo/δVi) of the amplifier's DC transfer characteristic;

[0011] FIG. 4 is a graph illustrating the linearity characteristics of the second conventional operational amplifier. This figure shows the first derivative (δVo/δVi) of the amplifier's DC transfer characteristic;

[0012] FIG. 5 shows the single ended and differential linearity characteristics of the first conventional operational amplifier output stage using a discrete multi-tone (“DMT”) signal with missing tones;

[0013] FIG. 6 is a graph illustrating the typical linearity characteristics of the first conventional operational amplifier output stage in harmonic distortion form;

[0014] FIG. 7 is a circuit diagram of a first embodiment of the present invention with a gm cell input;

[0015] FIG. 8 is a circuit diagram of a second embodiment of the present invention with a gm cell input;

[0016] FIG. 9 is a graph illustrating the linearity characteristics of the first embodiment of the present invention. This figure shows the first derivative (δVo/δVi) of the amplifier's DC transfer characteristic;

[0017] FIG. 10 is a graph illustrating the linearity characteristics of the first embodiment of the present invention using a DMT signal with missing tones;

[0018] FIG. 11 is a graph illustrating the linearity characteristics of the first embodiment of the present invention in harmonic distortion form;

[0019] FIG. 12 illustrates the translinear loop formed by the first, second, third and fourth transistors;

[0020] FIG. 13 illustrates the translinear loop formed by the fifth, sixth, seventh and eight transistors;

[0021] FIG. 14 is a circuit diagram of the final sub-stage of the first embodiment of the present invention using type I biasing of the output transistors in a no-load configuration;

[0022] FIG. 15 is a circuit diagram of the final sub-stage of the first embodiment of the present invention using type I biasing of the output transistors with a load;

[0023] FIG. 16 is a graph illustrating the current gain of the final sub-stage of the first embodiment of the present invention;

[0024] FIG. 17 is a circuit diagram of the final sub-stage of the second embodiment of the present invention using type II biasing of the output transistors in a no load configuration;

[0025] FIG. 18 is a circuit diagram of the final sub-stage of the second embodiment of the present invention using type II biasing of the output transistors with a signal applied to such final sub-stage's input;

[0026] FIG. 19 is a graph illustrating the DC current transfer characteristic of the final sub-stage of FIG. 18;

[0027] FIG. 20 is a graph illustrating the DC current transfer characteristic of the final sub-stage of FIG. 15;

[0028] FIG. 21 is a graph illustrating the linearity characteristic of the final sub-stage of FIG. 15 and FIG. 18. This figure shows the first derivative (δIo/δIi) of the amplifiers' DC current transfer characteristics;

[0029] FIG. 22 is a circuit diagram of a conventional operational amplifier illustrating bias setup for the output transistors;

[0030] FIG. 23 is a graph illustrating the DC current transfer characteristics of circuit depicted in FIG. 22;

[0031] FIG. 24 is a circuit diagram of the first embodiment of the present invention with current feedback circuitry;

[0032] FIG. 25 is a circuit diagram of the first embodiment of the present invention with voltage feedback circuitry;

[0033] FIG. 26 is a circuit diagram of the second embodiment of the present invention with current feedback;

[0034] FIG. 27 is a circuit diagram of the second embodiment of the present invention with voltage feedback;

[0035] FIG. 28 is a graph comparing the linearity characteristics between the two conventional operational amplifiers and the first and second embodiments of the present invention. The figure shows the first derivative of the amplifiers' gain.

[0036] FIG. 29 is a circuit diagram of the first embodiment of the present invention with a compound darlington output stage using type I biasing;

[0037] FIG. 30 is a circuit diagram of the first embodiment of the present invention with a compound darlington output stage using type I biasing and a differential pair input gm cell;

[0038] FIG. 31 is a circuit diagram illustrating a current feedback stability loop;

[0039] FIG. 32 is a circuit diagram implementing conventional Miller compensation using a current feedback with the embodiments of the present invention;

[0040] FIG. 33 is a circuit diagram illustrating a voltage feedback stability loop;

[0041] FIG. 34 is a circuit diagram illustrating implementation of conventional Miller compensation using voltage feedback to achieve right-half-plane zero is (“RHPZ”) cancellation with the embodiments of the present invention; and

[0042] FIG. 35 is a circuit diagram illustrating a method for achieving low frequency precision in either of the first or second embodiments of the present invention.

DESCRIPTION OF CONVENTIONAL AMPLIFIER OUTPUT STAGES

[0043] FIG. 1 is a circuit diagram of a first conventional operational amplifier output stage. FIG. 2 is a circuit diagram of a second conventional operational amplifier output stage. FIG. 3 illustrates the linearity characteristics of such first conventional operational amplifier by showing the first derivative of the DC transfer characteristic. FIG. 4 illustrates the linearity of such second conventional operational amplifier by showing the first derivative of the DC transfer characteristic. FIG. 5 illustrates the single ended and differential linearity of such first conventional operational amplifier with a discrete multi tone (“DMT”) signal with missing tones. DMT signal is a broadband signal containing many sinusoids spaced at equal intervals. The missing tone performance looks for intermodulation products from the broadband DMT signal in at a frequency where there is no sinewave present in the DMT signal. DMT is a rigorous test of an amplifier's linearity. FIG. 6 illustrates the typical linearity of such first and second conventional operational amplifiers in harmonic distortion form.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

[0044] Two embodiments of the present invention are shown in FIGS. 7 and 8. As compared to the conventional operational amplifier output stages as disclosed in FIGS. 1 and 2, the disclosed embodiments of an operational amplifier output stage as shown in FIGS. 7 and 8, provide a high β output (up to β2) and high speed with significantly reduced crossover distortion. Because of its high speed, the disclosed invention has the advantage of extended bandwidth. The disclosed operational amplifier output stage comprises a pre-driver sub-stage utilizing translinear current loops and a final sub-stage. The final sub-stage of the operational amplifier output stage disclosed herein comprises a complementary set of compound darlington transistors enclosed in a localized feedback system.

[0045] As used herein, translinearity refers to the characteristics of non-linear circuits whose operation is based on the exponential current-voltage relationship of the bipolar junction transistor; β refers to the ratio of DC collector current to DC base current in a bipolar junction transistor or current gain from base to collector; α represents the fraction of signal current going into one half of the pre-driver sub-stage, λ refers to the fraction of signal current going into the other half of the pre-driver sub-stage, and A refers to the emitter area of the BJT in consideration.

[0046] FIG. 7 is a circuit diagram of the first embodiment of an operational amplifier output stage having reduced supply current and high linearity constructed according to the teachings of the present invention. The circuit 100 includes an input gm cell 121, pre-driver sub-stage comprised of eight pre-driver sub-stage transistors 101, 102, 103, 104, 105, 106, 107 and 108, a final sub-stage comprising four final sub-stage transistors 109, 110, 111 and 112, and four current sources 131, 132, 133 and 134. The input gm cell 121 is configured to accept an input voltage signal, produce an error voltage across its input, and produce an output error current (δIin).

[0047] As shown therein, a first voltage supply rail 41 is coupled to a first node 51, a second voltage supply rail 42 is coupled to a fifth node 55.

[0048] The first pre-driver sub-stage circuit consists of four transistors 101, 102, 103 and 104. In the first pre-driver sub-stage circuit, the emitter of the first transistor 101 is coupled to the first voltage supply rail 41 at the first node 51, and the base of the first transistor 101 is coupled to a second node 52. The emitter of the second transistor 102 is also coupled to the second node 52; and its base is coupled to a third node 53. The base and collector of the third transistor 103 are also coupled to the third node 53. The collector and base of the fourth transistor 104 are each coupled to a fourth node 54. The emitter of the fourth transistor 104 is coupled to the voltage supply rail 41 at the first node 51.

[0049] The second pre-driver sub-stage circuit comprises four transistors 105, 106, 107 and 108. The second voltage supply rail 42 is coupled to the fifth node 55. The emitter of the fifth transistor 105 is coupled to the second voltage supply rail 42 at the fifth node 55 and its base is coupled to a the sixth node 56. The emitter of the sixth transistor 106 is coupled to the sixth node 56 and its base is coupled to a seventh node 57. The collector of the sixth transistor 106 is coupled to the second node 52. The base and collector of the seventh transistor 107 are coupled to a seventh node 57 and its emitter is coupled to an eighth node 58. The collector and base of the eighth transistor 108 are coupled to the eighth node 58, and the emitter of the eighth transistor 108 is coupled to the second voltage supply rail 42 at the fifth node 55.

[0050] The collector of the second transistor 102 and the emitter of the sixth transistor 106 are coupled to a common sixth node 56. The emitter of the second transistor 102 and the emitter of the sixth transistor 106 are coupled to a common second node 52. The cross connection advantageously results in no error current being lost in the translinear loops.

[0051] A first current source 131 is coupled to the first voltage supply rail 41 at the first node 51 and at the second node 52. A second current source 132 is coupled to the first voltage supply rail 41 at the first node 51 and at the seventh node 57. A third current source 133 is coupled to the second voltage supply rail 42 at the fifth node 55 and at the third node 53. A fourth current source 134 is coupled to the voltage supply rail 42 at the fifth node 55 and at the sixth node 56.

[0052] The final sub-stage 123 comprises a complementary pair of darlington transistors. The first set of darlington transistors is comprised of the ninth and tenth transistors 109 and 110. The emitter of the ninth transistor 109 is coupled to the collector of the first transistor 101 at a ninth node 59. The base and collector of the ninth transistor 109 are coupled at a tenth node 60. The base of the tenth transistor 110 is coupled to the ninth node 59, and the collector of the tenth transistor 110 is coupled to the first voltage supply rail 41 at the first node 51.

[0053] The second set of darlington transistors is comprised of the eleventh and twelfth transistors 111 and 112. The emitter of the eleventh transistor 111 is coupled to the collector of the fifth transistor 105 at an eleventh node 61. The base and collector of the eleventh transistor 111 are coupled to the base and collector of the ninth transistor 109 at the tenth node 60. The base of the twelfth transistor 112 is coupled to the eleventh node 61, and the collector of the twelfth transistor 112 is coupled to the second voltage supply rail 42 at the fifth node 55. The twelfth node 62 couples the emitter of the tenth transistor 110 to the emitter of the twelfth transistor 112. An output terminal 91 is coupled to the twelfth node 62. The twelfth node 62 also interconnects the output terminal 91 to the gm cell input 121. The configuration of the ninth transistor 109 and eleventh transistor 111 of the first embodiment of the present invention is also referred to as type I biasing.

[0054] A second embodiment of the present invention is disclosed in FIG. 8. The second embodiment is also referred to as type II biasing of the output transistors. In this second embodiment, the collectors of the ninth transistor 109 and the eleventh transistor 111 are not coupled at the tenth node 60. The collector of the ninth transistor 109 is coupled to the second voltage supply rail Vee 42 at the fifth node 55 and the collector of the eleventh transistor 111 is coupled to the first voltage supply rail Vcc 41 at the first node 51. In this case the current gain from the collectors of 101 or 105 to the output node 91 is the average of βn and βp. This arrangement minimizes crossover distortion in the output signal. As used herein, βn refers to the beta of transistor 110 and βp refers to the beta of transistor 101, where α=1 and λ=1; or βn refers to the beta of transistor 105 and βp refers to the beta of transistor 112, where α=0 and λ=0, or, in the small signal context, where α=0.5 and λ=0.5, βn refers to the average of the beta of transistor 110 and transistor 105 and βp refers to the beta of the average of transistor 101 and transistor 112, the relative contribution of each such pnp transistor and npn transistor to Bn and Bp varying proportionally with the variation in α and λ.

[0055] FIGS. 9, 10 and 11 illustrate different performance aspects of the present invention. Specifically, FIG. 9 shows the linearity characteristics of the first embodiment of the present invention, specifically the first derivative (δVo/δVi) of the amplifier's DC transfer characteristic. FIG. 10 shows the linearity characteristics of the first embodiment of the present invention using a DMT signal with missing tones. FIG. 11 shows the linearity characteristics of the first embodiment of the present invention in harmonic distortion form.

[0056] As shown in FIG. 12, in the first embodiment of the present invention a translinear loop is formed by the third transistor 103, fourth transistor 104, second transistor 102 and first transistor 101. In operation, two sets of current flow into this first translinear loop which sets up a quiescent current through a branch 170 connected at the collector of the first transistor 101. In addition, as shown in FIG. 13, a translinear loop is formed by the seventh transistor 107, the eighth transistor 108, the sixth transistor 106 and the fifth transistor 105. Two sets of current flow in this second translinear loop which sets up a quiescent current through a branch 171 connected at a collector of the fifth transistor 105. These two quiescent currents establish the bias currents for the respective tenth transistor 110 and for the twelfth transistor 112 by means of translinear principles in the loop formed by the ninth transistor 109, eleventh transistor 111, tenth transistor 110 and twelfth transistor 112.

[0057] When an input voltage is applied to the input gm cell 121, an error voltage appears across the output of the input gm cell 121 and an error current is produced. Advantageously, the cross-connection of the collector of the second transistor 102 to the emitter of the sixth transistor 106, and the collector of the sixth transistor 106 to the emitter of the second transistor 102 ensures that whatever proportion of the error current flowing into the emitters of the second transistor 102 and sixth transistor 106 also flows back out through the collectors of the second transistor 102 and the sixth transistor 106 into the bases of the first transistor 101 and the fifth transistor 105. Advantageously, there is no net signal loss in the pre-driver sub-stage translinear loops.

[0058] The error currents into the bases of the first transistor 101 and the fifth transistor 105, are thus gained up by the pre-driver sub-stage contribution of βp and βn. These error currents flow into the translinear loop formed by the ninth transistor 109, eleventh transistor 111, tenth transistor 110 and twelfth transistor 112. These amplified error currents can only flow into the bases of the tenth transistor 110 and twelfth transistor 112, where they are amplified by the final sub-stage contribution of βn and βp respectively. Thus, irrespective of whether the error current flows through the top or the bottom route through the circuit it appears at the output terminal 91 amplified by approximately βn multiplied by βp, where it develops a correction voltage across the load resistor to move the output to a point of minimum error of the feedback into the input gm cell 121.

[0059] Output Transistor Biasing

[0060] FIG. 14 is a circuit diagram of the final sub-stage 123 of the first embodiment of the operational amplifier output stage in a no load configuration. FIG. 14 illustrates type I biasing of the output transistors as follows: Current is flowing into the collector of the tenth transistor 110, referred to as IQ110C, and current is flowing out of the collector of the twelfth transistor 112, referred to as IQ112C. The emitter area of the ninth transistor 109 is referred to as AQ109 and the emitter area of the eleventh transistor 111 is referred to as AQ111. The emitter area of the tenth transistor 110 is referred to as AQ110 and the emitter area the twelfth transistor 112 is referred to as AQ112. Two current sources I135 and I136 are shown thereon: 1$I_{135}=I+\frac{\delta I_{\mathrm{sig}}}{2}\mathrm{and}{I}_{136}=I-\frac{\delta I_{\mathrm{sig}}}{2}$

[0061] Therefore, 2$\frac{I_{135}^2}{A_{\mathrm{Q109}}*A_{\mathrm{Q111}}}=\frac{I_{\mathrm{Q110C}}*I_{\mathrm{Q112C}}}{A_{\mathrm{Q112}}*A_{\mathrm{Q110}}}$ for βn and βp>>1 and VAn and VAp>>1,

IQ110C=IQ112C=IC.

[0062] 3 $$ Therefore , I 135 2 A Q109 * A Q111 = I C 2 A Q112 * A Q110 ; and ⁢   ⁢ futher $$ I C = I 135 · A Q110 * A Q112 A Q109 * A Q111

[0063] FIG. 15 is a circuit diagram of the final sub-stage 123 of the first embodiment of the present invention with a load 43. Type I biasing of the output transistors is thus described as follows: When a load 43 is connected to the output terminal 91 and the following do not hold:

βn and βp>>1, or

VAn and VAp>>1, or

[0064] there is an imbalance between current IQ110C and IQ112C.

[0065] Since current IQ110C is not equal to IQ112C, an error current flows in the load 43 thus developing an offset voltage Verror across the load 43.

[0066] When the difference in current in the final sub-stage transistors 110 and 112, are taken care of by a localized feedback system, the characteristics of the final sub-stage can be seen as follows: The signal current changes the bias currents by increasing the current through the top circuit and decreasing the current through the bottom circuit. In the limiting case for large current through the top circuit and miniscule current through the bottom circuit, and α is equal to one (1), the translinear loop cuts off the twelfth transistor 112 and all of the signal current flows into the base of the tenth transistor 110 where it appears in the load 43 as follows:

βn*(δIsig).

[0067] Conversely, for large signal current through the bottom circuit and miniscule current at the top circuit, and where α is equal to 0, the translinear loop is again cut off and all of the signal current flows into the base of the twelfth transistor 112 where it appears in the load 43 as follows:

βp*(δIsig).

[0068] For small signal currents, where α is close to half (0.5), the translinear loop is active, that is a quiescent current is flowing through both the tenth transistor 110 and the twelfth transistor 112, the signal current splits with α and (1−α) multiplied by δIsig flowing into the base of the twelfth transistor 112. Thus the current gain from input to output is as follows:

α*βn+(1−α)*βp,

[0069] for all cases of α such that α is equal to or greater than zero and equal to or less than 1.

[0070] As shown in the graph of FIG. 16, the gain will transition from βp to βn through the translinear region.

[0071] FIG. 17 is a circuit diagram of the final sub-stage of the second embodiment of an operational amplifier in a no load configuration. FIG. 17 illustrates type II biasing of the output transistors as follows: 4$\frac{{\beta }_n*{\beta }_p*i_b^2}{A_{\mathrm{Q109}}*A_{\mathrm{Q111}}}=\frac{I_{\mathrm{Q110C}}*I_{\mathrm{Q112C}}}{A_{\mathrm{Q112}}-A_{\mathrm{Q110}}},\mathrm{and}$$\frac{{\beta }_n*{\beta }_p*i_b^2}{A_{\mathrm{Q109}}*A_{\mathrm{Q111}}}=\frac{\left({\beta }_n^{*}I-{\beta }_p*{\beta }_n*i_b\right)\left(\beta I-{\beta }_n*{\beta }_p*i_b\right)}{A_{\mathrm{Q112}}-A_{\mathrm{Q110}}}.$

[0072] The current through branch 70 is: βp*ib.

[0073] The current through branch 75 is: I−βp*ib.

[0074] The current through branch 72 is: βn*ib.

[0075] The current through branch 74 is: I−βn*ib.

[0076] The current through branch 76 is: βn*I−βp*βn*ib.

[0077] The current through branch 77 is: βp*I−βn*βp*ib.

[0078] As can be seen, an offset current (βn−βp)*I will develop an offset voltage in a load, and would self correct in the localized feedback circuit.

[0079] Referring to FIG. 18, which illustrates type II biasing of the output transistors:

[0080] The current through branch 75 is: I+δI−βp ib.

[0081] The current through branch 74 is: I+δI−βn ib.

[0082] The current is through branch 76 is: (βn*I)+(βn*δI)−(βn*βp*ib).

[0083] The current through branch 77 is: (βp*I)−(βp*δI)−(βn*βp*δI).

[0084] Thus, the output current through branch 78 is: io=I*(βn−βp)+(βn+βp)*δI.

[0085] This result theoretically indicates no crossover distortion in the output, albeit with an offset.

[0086] FIGS. 19, 20 and 21 illustrate the-current drive relationships of the type I and type II biasing schemes.

[0087] Pre-Driver Biasing

[0088] FIG. 22 is a circuit diagram illustrating one technique of bias current generation for a rail to rail output stage in a conventional operational amplifier. The main disadvantage of this configuration is that current gain from the input to the output is only a single β. Also this type of stage will have a large output impedance making compensation more difficult given variation in a load's impedance. In the first and second embodiments of the present invention, translinear principles are used to establish the bias currents in the pre-driver stage.

[0089] Referring back to FIGS. 7 and 8, if there is a slight mismatch in the currents through the second transistor 102 and sixth transistor 106 due to an Early voltage mismatch between these two devices, a cascode on the second transistor 102 and the sixth transistor 106 will remedy this effect.

[0090] Also referring to FIGS. 7 and 8, assume that feedback introduces a correction term into the circuit to establish equality of collector currents in the first transistor 101 and the fifth transistor 105, then:

IQ101C=IQ105C=IQpre

[0091] Thus, from translinear principles: 5$\begin{array}{cc}1.\frac{I_{132}^2}{A_{\mathrm{Q107}}*A_{\mathrm{Q108}}}=\frac{I_{\mathrm{Q106C}}}{A_{\mathrm{Q106}}}*\frac{I_{\mathrm{Qpre}}}{A_{\mathrm{Qpre}}};& \\ 2.\frac{I_{132}^2}{A_{\mathrm{Q103}}*A_{\mathrm{Q104}}}=\frac{I_{\mathrm{Q102C}}}{A_{\mathrm{Q102}}}*\frac{I_{\mathrm{Qpre}}}{A_{\mathrm{Qpre}}};& \\ 3.I_{\mathrm{Q106C}}+I_{\mathrm{Q102C}}=I_{131};& \\ 4.\frac{I_{132}^2}{A_{\mathrm{Q107}}*A_{\mathrm{Q108}}}=\frac{A_{\mathrm{Q101}}}{I_{Q_{\mathrm{pre}}C}}*A_{\mathrm{Q106}}=I_{\mathrm{Q106C}};\text{(derived from equation 1);}& \\ 5.\frac{I_{132}^2}{A_{\mathrm{Q103}}*A_{\mathrm{Q104}}}=\frac{I_{\mathrm{Q105}}}{A_{Q_{\mathrm{pre}}C}}*A_{\mathrm{Q102}}=I_{\mathrm{Q102C}};\text{(derived from equation 2);}& \\ 6.\frac{I_{132}^2}{A_{\mathrm{Q107}}*A_{\mathrm{Q108}}}*\frac{I_{\mathrm{Q105}}}{A_{Q_{\mathrm{pre}}C}}*A_{\mathrm{Q106}}+\frac{I_{132}^2}{A_{\mathrm{Q103}}*A_{\mathrm{Q104}}}*\frac{A_{\mathrm{Q101}}}{I_{Q_{\mathrm{pre}}C}}*A_{\mathrm{Q102}}=I_{131};\text{(derived from equations 3, 4 and 5)}& \end{array}$6$\mathrm{Thus},I_{Q_{\mathrm{pre}}C}=\frac{I_{132}^2}{I_{131}}\left(\frac{A_{\mathrm{Q105}}*A_{\mathrm{Q106}}}{A_{\mathrm{Q107}}*A_{\mathrm{Q108}}}+\frac{A_{\mathrm{Q101}}*A_{\mathrm{Q102}}}{A_{\mathrm{Q103}}*A_{\mathrm{Q104}}}\right).$

[0092] Referring to the operational amplifier output stage 100 shown in FIG. 7, the change in current in the first transistor 101 and the fifth transistor 105 in response to a change in input current is computed as follows: The input current change takes the form of an equal but opposite change in IX and IY given that the difference current between IX and IY (i.e. δI) has to be divided between the bases of the first transistor 101 and the fifth transistor 105. Therefore,

I o =I Y −α*δI*β p −I Y −(1−α)δI−βn

δIo=−α*δI*βp−(1−α)*δI*βn;

δIo=−δI(α*βp+(1−α)−βn).

[0093] Where α is greater than zero and less than one, the value of α indicates the proportion of δI delivered into the bases of each of the pre-driver transistors, first transistor 101 and fifth transistor 105.

[0094] Where α is approximately zero, IX has significantly increased and IY has significantly decreased by equal and opposite quantities. The base-emitter voltage is large in the second transistor 102 and small in the sixth transistor 106. The second transistor 102 cuts off and all of the difference current between IX and IY (i.e. δI) flows into the base of the fifth transistor 105. This gives a current gain in the circuit of βn.

[0095] Where α is approximately equal to one, the opposite of where α is approximately equal to zero occurs. Where IX significantly decreases, IY significantly increases causing all difference current, δI, to flow into base of the first transistor 101, resulting in a current gain of βp.

[0096] Where α is greater than zero but less than one, the pre-driver sub-stage 122 is in translinear mode. The difference current is split in varying proportion into the first transistor 101 and the fifth transistor 105. Thus, δIo/δI=α*βp+(1−α)*βn.

[0097] Referring to FIG. 23, the DC response of the pre-driver sub-stage 122 of the present invention is shown.

[0098] In connection with the coupling of the pre-driver sub-stage 122 to the final sub-stage 123, the biasing scheme of the pre-drivers and the biasing scheme of the final drivers of the present invention have the advantageous property of not absorbing any signal current. All of the signal current is delivered directly into the bases of the transistors, and none is lost in translinear loops.

[0099] The current gain from the input to the output has approximately the form:

δIo≈βn*βp*∂Iin.

[0100] Feedback Analysis

[0101] When feedback is locally applied by means of some localized feedback circuit, the errors are corrected within a very tight loop which will respond much more quickly than relying on the amplifier overall feedback loop. This localized feedback provides the present invention with high speed capabilities.

[0102] Four (4) possibilities are presented: (i) current feedback, transitional β output (ii) current feedback, constant β output (iii) voltage feedback, transitional β output, and (iv) voltage feedback, constant β output.

[0103] FIG. 24 is a circuit diagram of a first embodiment of the present invention with a current feedback circuitry. FIG. 25 is a circuit diagram of the first embodiment of the present invention with a voltage feedback circuitry.

[0104] When the input gm cell 121 takes the form of a complementary differential pair, the inherent RHPZ appearing when the pre-driver sub-stage is Miller compensated vanishes as the feed forward term contributing to the RHPZ is pulled back out by the differential pair.

[0105] FIG. 28 illustrates the output in a closed loop configuration with [greater than unity gain] driving a heavy load over a wide voltage range. In all cases the worst ease non-linearity is approximately plus/minus 1 part in 1000. For the current feedback, constant β output, cross-over distortion is virtually eliminated.

[0106] FIG. 29 is a circuit diagram of the first embodiment of the present invention with a compound darlington output stage using type I biasing. A generalized evaluation of this circuit is as follows:

[0107] Referring to current through branches 150, 152, 154156, 158, 160, 172 and 174 in FIG. 29:

[0108] Current through branch 150 is ILTP; where ILTP refers to the current through current source 131.

[0109] Current through branch 152 is: −α·δI.

[0110] Current through branch 154 is: 7$\frac{I_{\mathrm{LTP}}}{2}+\delta I\left(\frac{1}{2}-\alpha \right).$

[0111] Current through branch 156 is: 8$\frac{I_{\mathrm{LTP}}}{2}-\frac{\delta I}{2}.$

[0112] Current through branch 158 is: 9$\frac{I_{\mathrm{LTP}}}{2}+\frac{\delta I}{2}.$

[0113] Current through branch 160 is: Ibias p−βQ101·α·δI.

[0114] Current through branch 162 is approximately 10$I_{\mathrm{bias}p}-\frac{I_{\mathrm{LTP}}}{2}-\delta I·{\beta }_{\mathrm{Q101}}·\alpha .$

[0115] Current through 172 is: −λ·δI(βQ101·α+βQ105(1−α)).

[0116] Current through 174 is: −λ·δI·(βQ101·α+βQ105 (1−α))+Ibias out.

[0117] Referring to current through branches 151, 153, 155, 157, 159, 161, 163, 173 and 175:

[0118] Current through branch 151 is ILTP; where ILTP refers to the current through current source 134 which is the same as the current through current source 131.

[0119] Current through branch 153 is: (1−α) δI.

[0120] Current through branch 155 is: 11$\frac{I_{\mathrm{LTP}}}{2}+\delta I\left(\frac{1}{2}-\alpha \right).$

[0121] Current through branch 157 is: 12$\frac{I_{\mathrm{LTP}}}{2}+\frac{\delta I}{2}.$

[0122] Current through branch 159 is: 13$\frac{I_{\mathrm{LTP}}}{2}-\frac{\delta I}{2}.$

[0123] Current through branch 161 is: Ibias p+βQ105·(1−α)δI.

[0124] Current through branch 163 is: 14$I_{\mathrm{bias}p}-\frac{I_{\mathrm{LTP}}}{2}+{\beta }_{\mathrm{Q105}}·\left(1-\alpha \right)\delta I.$

[0125] Current through branch 173 is: (1−λ)·δI(βQ101·α+βQ105(1−α).

[0126] Current through 175 is: (1−λ)−δI (βQ101·α+βQ105(1−α)+Ibias out.

[0127] Therefore:

I out =−λ·δI·β Q110 ·(βQ101·α+βQ105(1−α))−(1−λ)·δI·βQ112(βQ101·α+βQ105(1−α)).

[0128] In a first case where Iout is large and positive, and load conduction is through transistor 110 and transistor 101, where α=1, λ=1, then:

I out =−δI·β Q110 ·βQ101

[0129] In a second case where Iout is large and negative, and load conduction is through transistor 112 and transistor 105, where α=0, λ=0, then:

I out =−δI·β Q112 ·βQ105

[0130] In a third case where Iout is very small through the cross-over point, and load conduction is through transistor 110 and transistor 112, where α≈0.5, λ≈0.5, then: 15$I_{\mathrm{out}}=-\delta I\left(\frac{{\beta }_{\mathrm{Q101}}+{\beta }_{\mathrm{Q105}}}{2}\right)\left(\frac{{\beta }_{\mathrm{Q110}}+{\beta }_{\mathrm{Q112}}}{2}\right)$

[0131] Thus, for βQ112=βQ101=βp

[0132] and βQ110=βQ105=βn16$I_{\mathrm{out}}=-\delta {I\left(\frac{{\beta }_p+{\beta }_n}{2}\right)}^2$

[0133] FIG. 30 is a circuit diagram of the first embodiment of the present invention with a compound darlington output stage using type I biasing and a differential pair input gm cell. A specific evaluation of this circuit is as follows:

[0134] Referring to the current through branches 140, 142, 152, 160, 172 and 174 in FIG. 30:

[0135] The current through branch 140 is:

I 131 +δI (½−α)

[0136] The current through branch 142 is: 17$-\frac{\delta I}{2}$

[0137] The current through branches 152, 160, 172 and 174 are the same as that in the equivalent numbered branches in FIG. 29.

[0138] Referring to the current through branches 141, 143, 153, 161, 173, and 175 in FIG. 30:

[0139] The current through branch 141 is:

I 134 +δI (½−α)

[0140] The current through branch 143 is: 18$\frac{\delta I}{2}$

[0141] The current through branches 153, 161, 173 and 175 are the same as that in the equivalent numbered branches in FIG. 29.

[0142] Therefore:

I out =−λ·δI·β Q110 ·(βQ101·α+βQ105(1−α))−(1−λ)·δI·βQ112(βQ101·α+βQ105(1−α))

[0143] Referring to FIG. 30, and as noted in FIG. 29, in a first case, where Iout is large and positive, and load conduction is through transistor 110 and transistor 101, where α=1, λ=1, then:

I out =−δI·β Q110 ·βQ101

[0144] In a second case where Iout is large and negative, and load conduction is through transistor 112 and transistor 105, where α=0, λ=0, then:

I out =−δI·β Q112 ·βQ105

[0145] In a third case, where case Iout is very small through the cross-over point, and load conduction is through transistor 110 and transistor 112, where α≈0.5, λ≈0.5, then: 19$I_{\mathrm{out}}=-\delta I\left(\frac{{\beta }_{\mathrm{Q101}}+{\beta }_{\mathrm{Q105}}}{2}\right)\left(\frac{{\beta }_{\mathrm{Q110}}+{\beta }_{\mathrm{Q112}}}{2}\right)$

[0146] Thus, for βQ112=βQ101=βp

[0147] and βQ110=βQ105=βn20$I_{\mathrm{out}}=-\delta {I\left(\frac{{\beta }_p+{\beta }_n}{2}\right)}^2$

[0148] where 0<α<1;

[0149] and 0<λ<1.

[0150] Ibiasp and Ibiasout are established using translinear principles.

[0151] Compensation

[0152] FIGS. 31, 32, 33 and 34 show the various types of compensation techniques that can be used with the present invention. FIG. 31 is a half circuit showing the current feedback case with small signal AC. The circuit is a 2 voltage gain stage amplifier with voltage gain being developed at nodes 63 and 64. The circuit lends itself to classic Miller compensation as shown in FIG. 31.

[0153] Referring to FIG. 32, the resistor 81 eliminates the right half plane through the compensation capacitor 85. At the quiescent condition, the value is the reciprocal of the transconductance of the first transistor 101.

[0154] FIG. 33 illustrates the voltage feedback case. Referring to the circuit in FIG. 33, there are two (2) loops to be compensated, inner loop 2 and outer loop 1. As can be seen in FIG. 32, similar to the current feedback implementation, the system is a 2 voltage gain stage amplifier with voltage gain at nodes 63 and 64. This circuit can also be Miller compensated. There is no concern with RHPZ because the differential transistor 113 draws the feed forward signal out.

[0155] Implementation

[0156] It is noted that the voltage feedback implementation can only be used for gain greater than 1. Further, the current feedback implementation can be used for arbitrary gain. All four implementations can be used as a stand alone amplifier configuration.

[0157] FIG. 35 illustrates how gain from the present invention can be preserved where additional lower frequency precision is required.

[0158] The advantages of the present invention over conventional operational amplifier output stages is significantly higher linearity for the same supply current or linearity equal to the conventional operational amplifiers.

[0159] The current gain obtained in the error correction loop of each of the first and second conventional operational amplifiers is only a single current gain whereas the current gain of the present invention is up to β2. Further, the DC non-linearity of conventional amplifiers is approximately 2 parts per 1000, a factor of 25 worse than the present invention. Reduced current draw is one of the advantages afforded by the design of each of the present invention.

[0160] The numerous innovative teachings of the present application are described with particular reference to the disclosed embodiments. However, it should be understood that these embodiments provide only two examples of the many advantageous uses and innovative teachings herein. Various alterations, modifications and substitutions can be made to the disclosed invention without departing in any way from the spirit and scope of the invention, as defined in the claims that follow. For example, although the embodiments have been presented herein with reference to particular transistor types, voltage and current polarities and methods of coupling, the present inventive structures and characteristics are not necessarily limited to particular transistor types, polarities or methods of coupling, as used herein. It should be understood the embodiment used hereinabove can easily be implemented using many diverse transistor types, polarities and methods of coupling so long as the combinations achieve an ultra linear, high speed operational amplifier output stage with reduced current draw and extended bandwidth.

Claims

1. An operational amplifier output stage, comprising: a pre-driver sub-stage and a final sub-stage, the pre-driver sub-stage having a plurality of transistors being biased by a plurality of current sources, the pre-driver sub-stage being adapted to accept a current signal (δIin) from an input gm cell; the pre-driver stage being further adapted to provide biasing to a plurality of transistors in the final sub-stage; and the pre-driver sub-stage being coupled to the final sub-stage so as to provide current gain from input to output of δIo≈βn*βp*δIin; and localized feedback circuitry enclosed in the output stage operable to correct signal errors more rapidly than an overall amplifier feedback loop, thereby improving the speed characteristics of the operational output stage.

2. The operational amplifier output stage recited in claim 1, further comprising inherent RHPZ cancellation operable to extend bandwidth.

3. The operational amplifier output stage recited in claim 1, wherein the plurality of transistors in the final sub-stage comprises 4 transistors arranged as a complementary pair of differential transistors enclosed in a localized feedback system.

4. The operational amplifier output stage recited in claim 1 for use in an integrated circuit.

5. The operational amplifier output stage recited in claim 1 for use in a DSL driver.

6. An operational amplifier output stage, comprising: a pre-driver sub-stage having a plurality of transistors configured as translinear loops such that there is minimal net signal loss or signal attenuation in the pre-driver sub-stage; a final sub-stage coupled to, and biased by currents from, the pre-driver sub-stage, operable to provide up to β2; and a localized feedback circuitry and inherent RHPZ in the output stage operable to improve speed characteristics and extend bandwidth.

7. An operational amplifier output stage, comprising: a first voltage supply rail Vcc connected to a first node; two connection terminals to an input stage, a first terminal connected to a second node for receiving a positive portion of an input signal and a second terminal connected to a sixth node for receiving a negative portion of an input signal; a first pre-driver sub-stage circuit coupled at the second node, the first pre-driver sub-stage circuit further comprising: a first transistor having its emitter coupled to the first voltage supply rail Vcc at the first node, and its base coupled at the second node; a second transistor having its emitter coupled to the second node and its base coupled to a third node; a third transistor having its base and collector coupled to the third node; a fourth transistor having its collector and base being coupled to a fourth node, and its emitter coupled to the first voltage supply rail Vcc at the first node; a second voltage supply rail Vee coupled to a fifth node; a second pre-driver sub-stage circuit coupled to the sixth node, the second pre-driver sub-stage circuit further comprising: a fifth transistor having its emitter coupled to the second voltage supply rail Vee at the fifth node, and its base coupled to the sixth node; a sixth transistor having its emitter coupled to the sixth node, its base coupled to a seventh node, and its collector coupled to the second node; a seventh transistor having its base and collector coupled to a seventh node; and its emitter coupled to an eighth node; an eighth transistor having its collector and base being coupled to the eighth node, and its emitter coupled to the second voltage supply rail Vee at the fifth node; a cross connection between the second transistor's collector and the sixth transistor's emitter at the sixth node, and the second transistor's emitter and the sixth transistor's collector at the second node, the cross connection resulting in a proportion of any error current flowing into the second transistor's emitter and sixth transistor's emitter to flow out through the second transistor's collector and the sixth transistor's collector into the base of the first transistor and the base of the fifth transistor; a first current source coupled between the first voltage supply rail Vcc at the first node and the second node; a second current source coupled between the first voltage supply rail Vcc at the first node and the seventh node; a third current source coupled between the second voltage supply rail Vee at the fifth node and at the third node; a fourth current source coupled between the second voltage supply rail Vee at the fifth node and the sixth node; a final sub-stage, comprising: a first final sub-stage circuit further conditioning the positive portion of the current signal provided by the first pre-driver sub-stage circuit, the first final sub-stage circuit comprising: a ninth transistor having its emitter coupled to the first transistor's collector at a ninth node, and its base and collector coupled to a tenth node; a tenth transistor having its base coupled to the ninth node, and its collector coupled to the first voltage supply Vcc rail at the first node; a second final sub-stage circuit further conditioning the negative portion of the current signal, provided by the second pre-driver sub-stage circuit, the second final sub-stage circuit comprising: an eleventh transistor having its emitter coupled to the fifth transistor's collector at an eleventh node, its base and collector coupled to the ninth transistor's base and collector at the tenth node; a twelfth transistor having its base coupled to the eleventh node, and its collector coupled to the second voltage supply rail Vee at the fifth node; a twelfth node interconnecting the tenth transistor's emitter with the twelfth transistor's emitter; and an output terminal coupled to the twelfth node; and localized feedback circuitry enclosed within the operational amplifier output stage.

8. The operational amplifier output stage recited in claim 7 wherein the first, second, third, fourth, ninth and twelfth transistors are pnp transistors and the fifth, sixth, seventh, eight, tenth and eleventh transistors are npn transistors.

9. The operational amplifier output stage recited in claim 7, including a localized feedback circuitry enclosed within the operational amplifier output stage.

10. The operational amplifier output stage recited in claim 7, wherein the localized feedback circuitry utilizes current feedback principles operable to substantially eliminate cross-over distortion.

11. An operational amplifier output stage, comprising: a first voltage supply rail Vcc connected to a first node; two connection terminals to an input stage, a first terminal connected to a second node for receiving a positive portion of a current signal and a second terminal connected to a sixth node for receiving a negative portion of a current input signal; a first pre-driver sub-stage circuit coupled at the second node, the first pre-driver sub-stage circuit further comprising: a first transistor having its emitter coupled to the first voltage supply rail Vcc at the first node, and its base coupled at the second node; a second transistor having its emitter coupled to the second node and its base coupled to a third node; a third transistor having its base and collector coupled to the third node; a fourth transistor having its collector and base being coupled to a fourth node, and its emitter coupled to the first voltage supply rail Vcc at the first node; a second voltage supply rail Vee coupled to a fifth node; a second pre-driver sub-stage circuit coupled to the sixth node, the second pre-driver sub-stage circuit further comprising: a fifth transistor having its emitter coupled to the second voltage supply rail Vee at the fifth node, and its base coupled to the sixth node; a sixth transistor having its emitter coupled to the sixth node, its base coupled to a seventh node, and its collector coupled to the second node; a seventh transistor having its base and collector coupled to a seventh node; and its emitter coupled to an eighth node; an eighth transistor having its collector and base being coupled to the eighth node, and its emitter coupled to the second voltage supply rail Vee at the fifth node; a cross connection between the second transistor's collector and the sixth transistor's emitter at the sixth node, and the second transistor's emitter and the sixth transistor's collector at the second node, the cross connection resulting in a proportion of any error current flowing into the second transistor's emitter and sixth transistor's emitter to flow out through the second transistor's collector and the sixth transistor's collector into the base of the first transistor and the base of the fifth transistor; a first current source coupled between the first voltage supply rail Vcc at the first node and the second node; a second current source coupled between the first voltage supply rail Vcc at the first node and the seventh node; a third current source coupled between the second voltage supply rail Vee at the fifth node and at the third node; a fourth current source coupled between the second voltage supply rail Vee at the fifth node and the sixth node; a final sub-stage, comprising: a first final sub-stage circuit further conditioning the positive portion of the current signal provided by the first pre-driver sub-stage circuit, the first final sub-stage circuit comprising: a ninth transistor having its emitter coupled to the first transistor's collector at a ninth node, and its base coupled to a tenth node and its collector coupled to the second voltage supply rail Vee at the fifth node; a tenth transistor having its base coupled to the ninth node, and its collector coupled to the first voltage supply Vcc rail at the first node; a second final sub-stage circuit further conditioning the negative portion of the current signal, provided by the second pre-driver sub-stage circuit, the second final sub-stage circuit comprising: an eleventh transistor having its emitter coupled to the fifth transistor's collector at an eleventh node, its base coupled to the ninth transistor's base and collector at the tenth node and its collector coupled to the first voltage supply rail Vcc at the first node; a twelfth transistor having its base coupled to the eleventh node, and its collector coupled to the second voltage supply rail Vee at the fifth node; a twelfth node interconnecting the tenth transistor's emitter with the twelfth transistor's emitter; an output terminal coupled to the twelfth node; and localized feedback circuitry enclosed within the operational amplifier output stage.

12. The operational amplifier output stage recited in claim 11, wherein the localized feedback circuitry utilizes current feedback principles.

13. The operational amplifier output stage in claim 11, wherein the localized feedback circuitry utilizes voltage feedback principles.

14. The operational amplifier output stage recited in claim 11, wherein the first, second, third, fourth, ninth and twelfth transistors are pnp transistors, and the fifth, sixth, seventh, eighth, tenth and eleventh transistors are npn transistors.

15. A method of amplifying a signal, comprising the steps of: biasing a plurality of transistors in a pre-driver sub-stage; biasing a plurality of transistors in a final sub-stage; routing the positive cycle of the signal through a first, biased pre-driver sub-stage circuit; routing the negative cycle of the signal through a second, biased pre-driver sub-stage circuit; amplifying the positive cycle of the signal in the first, biased pre-driver sub-stage circuit; amplifying the negative cycle of the signal in the second, biased pre-driver sub-stage circuit; routing the amplified positive cycle of the signal to a first, biased final sub-stage circuit; routing the amplified negative cycle of the signal to a second, biased final sub-stage circuit; further amplifying the positive cycle of the signal in a first, biased final sub-stage circuit in tandem with the pre-driver sub-stage amplification action; further amplifying the negative cycle of the signal in a second, final sub-stage circuit in tandem with the pre-driver sub-stage amplification action; employing a plurality of translinear loops in the pre-driver sub-stage circuits and final sub-stage circuits so as to preserve the amplitude, frequency and phase characteristics of the signals during routing and amplification; joining in phase the amplified portions of the positive and negative signal at an output stage terminal in a manner that results in high beta amplification and of an output signal when compared to the input signal; and feeding back a portion of the signal in a localized feedback system to increase speed and extend bandwidth.

16. A method of amplifying signals in an operational amplifier output stage, comprising the steps of: generating bias currents in a pre-driver sub-stage and a final sub-stage; inputting the signals into the pre-driver sub-stage and a final sub-stage; amplifying the signals in tandem in the pre-driver sub-stage and final sub-stage to achieve high beta amplification of the signal; employing a plurality of translinear loops in the pre-driver sub-stage and final sub-stage such that there is minimal signal loss in the pre-driver sub-stage and the final sub-stage; and using localized feedback principles so as to achieve high speed response of the operational amplifier output stage.