Claims
- 1. An digital signal processing apparatus, comprising:
a memory means for retaining information; a digital signal processing means communicatively engageable with said memory means, the digital signal processing means capable of executing instructions to:
generate at least one channel using a first set of codes; generate a high-rate channel using a second set of codes; transmit said at least one channel via a first carrier; and transmit said high-rate channel via a second carrier that is orthogonal to said first carrier.
- 2. The apparatus in accordance with claim 1, wherein said at least one channel is a set of channels.
- 3. The apparatus in accordance with claim 1, wherein said first set of codes is a long Walsh code.
- 4. The apparatus in accordance with claim 1, wherein said second set of codes is a short Walsh code.
- 5. The apparatus in accordance with claim 1, wherein said at least one channel is a set of channels, wherein said first set of codes is a long Walsh code, and wherein said second set of codes is a short Walsh code.
- 6. The apparatus in accordance with claim 2, said digital signal processing means capable of executing further instructions to:
modulate a first instance of said set of channels with an in-phase pseudorandom noise code and an in-phase carrier; modulate a second instance of said set of channels with a quadrature-phase pseudorandom noise code and a quadrature-phase carrier; and sum said first instance of said set of channels with said second instance of said set of channels.
- 7. The apparatus in accordance with claim 2 further said digital signal processing means capable of executing further instructions to:
modulate a first instance of said high-rate channel with an in-phase pseudorandom noise code and an in-phase carrier; modulate a second instance of said high-rate channel with a quadrature-phase pseudorandom noise code and a quadrature-phase carrier; invert said second instance of said high-rate channel; and sum said first instance of said high-rate channel with said second instance of said high-rate channel.
- 8. The apparatus in accordance with claim 1 further comprising the step of transmitting pilot data on one channel from said set of channels.
- 9. The apparatus in accordance with claim 3, wherein said second set of codes is a short Walsh code.
- 10. The apparatus in accordance with claim 9, wherein said at least one channel is a set of channels.
- 11. The apparatus in accordance with claim 7 further comprising the step of transmitting pilot data on one channel from said set of channels.
- 12. The apparatus in accordance with claim 2 wherein said set of channels includes a pilot channel, a synchronization channel and a traffic channel.
- 13. The apparatus in accordance with claim 4 wherein said short code occupies a set of evenly spaced long Walsh codes.
- 14. The apparatus in accordance with claim 3 wherein said long Walsh codes comprise sixty-four Walsh symbols.
- 15. A digital signal processing apparatus, comprising:
a memory means for retaining information; a digital signal processing means communicatively engageable with said memory means, the digital signal processing means capable of executing instructions to: generate a set of medium rate data channels; and generate a high rate data channel that is orthogonal to the set of medium rate data channels.
- 16. The apparatus in accordance with claim 15 wherein said digital signal processing means generates said set of medium rate data channels using a set of long channel code modulators.
- 17. The apparatus in accordance with claim 16 wherein said digital signal processing means generates said set of high rate data channels using a short channel code modulator.
- 18. The apparatus in accordance with claim 15 wherein said digital signal processing means generates said set of high rate data channels using a means for transmitting data via a set of evenly distributed long code channels.
CROSS REFERENCE
[0001] This application is a continuation application of co-pending application Ser. No. 09/364,778, filed Jul. 30, 1999, entitled “High-Data-Rate Supplemental Channel for CDMA Telecommunications System” which is a divisional application of application Ser. No. 08/784,281, now U.S. Pat. No. 6,173,007, filed Jan. 15, 1997 and currently assigned to the assignee of the present application.
Divisions (1)
|
Number |
Date |
Country |
Parent |
08784281 |
Jan 1997 |
US |
Child |
09364778 |
Jul 1999 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
09364778 |
Jul 1999 |
US |
Child |
09924336 |
Aug 2001 |
US |