The present invention relates to the field of connectors, more specifically to the field of connectors suitable for use in applications where the connector is supported by a circuit board.
Connectors are widely used to provide an interface between a circuit board and another connector (such as a plug connector). Due to the continual improvement in computing power and the increased demand for high bandwidth communication channels on the end user side, there has been increased demand for connectors that can handle higher density of transmission channels while at the same time there has been an increased desire to provide connectors that take up less space on a supporting circuit board. Consequentially, connector designs have continued to attempt to increase performance while at the same time increasing density. One major complication with this effort is that more closely arranged communication channels create cross-talk on neighboring channels, thus it becomes more challenging to improve data rates while providing for an increase in density that can actually be mounted on a circuit board. Another major concern for system level developers is that the space required to mount a connector is often not representative of the space needed to route out the connector on a circuit board. In particular, ground vias (which are required to electrically connect to ground terminals) tend to be positioned in locations that interfere with ideal signal trace routing configurations. Accordingly, certain individuals would appreciate further improvements in connector design.
A connector is disclosed that allows for very compact routing on a minimal number of layers while providing for high performance. In an embodiment, the connector includes pair of signal wafers that are positioned side-by side, each wafer including a first terminal with a contact, a tail and a body extending between the tail and contact so that a pair of the first terminals can form a differential pair. The differential pair can be configured to provide a broad-side coupled configuration in the body of the terminals. The tails are configured to be positioned in a line and the line can be positioned between the body of the different pairs. At least one of the wafers that forms the pair of wafers includes a tail stub that is electrically isolated from the first terminal and includes a tail. A ground wafer is provided adjacent one of the pair of wafers and can include one or more terminals that are arranged such that the body is aligned with the body of the terminals that provide the differential pair. The ground terminal omits a tail and instead the ground terminal is coupled to the tail stub in one of the signal wafers. A conductive member can connect a junction in the ground terminal to a junction in the tail stub.
The present invention is illustrated by way of example and not limited in the accompanying figures in which like reference numerals indicate similar elements and in which:
The detailed description that follows describes exemplary embodiments and is not intended to be limited to the expressly disclosed combination(s). Therefore, unless otherwise noted, features disclosed herein may be combined together to form additional combinations that were not otherwise shown for purposes of brevity.
It should be noted that the depicted housing and wafers have lines indicating two or more piece construction. Such a construction was done for purposes of modeling and is not required in an actual part and it is expected that the various frames and housings can be formed in one piece using convention molding technology. Therefore, the depicted seam lines are not intended to be limiting.
As depicted, the set of wafers 50 includes a wafer triplet 55 that includes a ground wafer 60 with a frame 61, a first signal wafer 80 with a frame 81 and a second signal wafer 100 with a frame 101. The frame 61 of the ground wafer 60 supports a first ground terminal 62, a second ground terminal 63, a third ground contact 64 and a fourth ground terminal 65. Each of the ground terminals includes a contact 62a, 63a, 64a, 65a and a body 62b-65b and each ground terminal includes an end, such as end 62c. As depicted, the ground terminals do not have tails but do include junction 66.
The frame 81 of the first signal wafer 80 supports signal terminals 82-85 and each terminal includes a contact, a body and a tail. For example, terminal 82 includes a contact 82a and a body 82b and tails 82c. Similarly the frame 101 of the second signal wafer 100 supports terminals 102-105 and each terminal includes a contact, a body and a tail. For example, terminal 102 includes a contact 102a, a body 102b and a tail 102c. The terminals 62, 82, 102 are configured such that their respective contacts 62a, 82a, 102a are aligned side-by-side on the first side 21a of the first card slot 21 while the contacts 63a, 83a, 103a of terminals 63, 83, 103 are on the second side 21b. The same type of arrangement is also provided for the second card slot 22. Thus, the depicted embodiment also includes sufficient signal terminals such that wafers 80, 100 provide four signal pairs, each pair on an opposite side of one card slots 21, 22. Thus the depicted embodiment illustrates four terminals in each signal wafer so that the two signal wafers collectively provide four differential pairs.
As can be appreciated, the differential pairs are edge coupled in the contacts, broad-side coupled in the body and then edge coupled again at the tails. One benefit of the depicted design is that all the tails of the wafer triplet can be arranged in a single row 58a, 58b. This allows the circuit board to have its vias arranged in a corresponding single row 34a, 34b. In addition, the vias are configured so that a row has a G1 via, a S+, S− pair, a G2 via, a S+, S− pair, a G3 via, a G4 via, a S+, S− pair, a G5 via, a S+, S− pair, and a G6 via. In between the rows 34a, 34b are trace paths 35 that allows the signal traces in the board to be routed out in four layers while minimizing board space. In the depicted embodiment, for example, a first trace pair 33a can be routed out on a first layer, a second trace pair 33b can be routed out on a second layer, a third trace pair 33c can be routed out on a third layer and a fourth trace pair 33d can be routed out on a fourth layer, all while staying between a first via row 34a and a second via row 34b. Such a design is particularly helpful when the number of layers available is sufficient to support the multiple rows of traces and the horizontal board space needs to be conserved. Furthermore, such a design is well suited to ganged applications because connectors can be placed beside each other without the need to worry about traces needing to fan out in order to route out the connector on the circuit board, even if the connector is a stacked configuration. Thus the depicted connector allows for simple routing of the traces. In addition the simple routing configuration that is possible tends to improve the performance on the circuit board as there are reduced losses in the circuit board compared to existing designs that route around different ground vias (typically providing more of a fan-out routing in the circuit board).
As can be appreciated, the ground terminals include junctions that intended to be electrically connected to tail stubs 95. Thus, the ends of the ground terminals are electrically connected to the tail stubs 95 via conductive members 140 that connect to junctions 66 in the tail stubs 95 and the ground terminals. As depicted, there are three junctions 66, one on each side of the ends of ground terminals 62a and 62b, and the ends of the ground terminals are connected together with a bar 68a, 68b that includes the three junctions 66. Tail stubs 95 are supported by the signal wafers 80, 100 so as to provide grounds G′1, G′2, G′3, G′4, G′5, G′6 and the conductive member 140 ensures that there is a return to ground path for each ground terminal so that the ground terminals can be electrically connected to a ground via (such as ground vias G1, G2, G3, G4, G5, G6) with the grounds. As depicted, the majority of the tails stubs 95 can be configured to be the same design, which can help to keep the overall costs lower and may also provide more consistent performance.
It should be noted that while ground terminals are depicted as being substantially the same size as the signal terminals, in alternative embodiments the ground terminals could be provided as shields that are at least twice as wide as the signal terminals and in certain embodiments the ground terminal should be replaced with a shield that would extend between and overlap the ground terminals 62a, 62b. In addition, a wide shield that extends across substantially the entire ground wafer could also be provided. In each embodiment, the junctions 66 and conductive members 140 would allow the ground terminals/ground shield to electrically couple to tails stubs that are electrically coupled to ground (e.g., provide a return path for energy carried on the ground terminals).
As depicted, the signal wafers are configured so that signal wafer 80 includes three ground stubs 70 and signal wafer 100 includes three ground stubs 70. This allows, when looking at a row, a ground, signal, signal, ground, signal, signal, ground pattern that is repeated. Thus, signal pairs 57 are positioned between ground vias and two ground vias are positioned between the signals pairs in the first and second card slot. The additional ground via helps provide further electrical isolation between the top and bottom card slot and can help reduce cross-talk in a connector that is configured to be compactly designed such that there is limited space between vertical card slots.
As can be appreciated from
A connector 210 includes a housing 220 with a wafer set 250. The housing can include two card slots 221, 222 and each card slot can include a first side 221a, 222a and a second side 221b, 222b. As can be appreciated, the card slots 221, 222 are on a mating face of the connector 210 and the tails are on a mounting face of the connector 210. As in the above embodiment, triplets 41a, 41b, 41c, 41d are positioned on opposite sides of their respective card slots but are all configured to be connected to a supporting circuit board in the row 258a, thus row 258a includes four terminal pairs 257 and each terminal pair 257 is separated from another terminal pair in the row 258a by at least tail that is connected to a ground terminal by a conductive member 340. As in the above embodiments, the ground tails are formed by tail stubs that are also in the row 258a and the tail stubs are electrically isolated from the signal terminals.
Similar to the above embodiment, the connector includes rows 258a, 258b of tails and conductive members 340 are used to connect junctions 266 in the bars of the ground terminals to junctions 266 in tail stubs. The tail stubs provide grounds G″1, G″2, G″3, G″4, G″5, G″6. As in the above embodiment, signal pairs S+, S− are positioned so that a ground is on each side of the signal pair.
The conductive members 340 can be shaped like flat plates and the additional surface area can provide additional shielding between signal pairs within a row. The conductive members 340 can be pressed into channels 361 in the bottom of the wafers (e.g., inserted into the wafers on the mounting side) so that the conductive members 340 can engage the junctions 266 supported by the frames 261, 281, 301. As can be appreciated, the conductive member extends past the frames 281, 301 in the case of a channel 360. In an embodiment, each signal pair will have a conductive member 340 positioned on opposing sides.
As can be appreciated from
The disclosure provided herein describes features in terms of preferred and exemplary embodiments thereof Numerous other embodiments, modifications and variations within the scope and spirit of the appended claims will occur to persons of ordinary skill in the art from a review of this disclosure.
This application claims priority to U.S. Provisional Application No. 61/642,005, filed May 3, 2013, which is incorporated herein by reference in its entirety.
Filing Document | Filing Date | Country | Kind |
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PCT/US13/39459 | 5/3/2013 | WO | 00 |
Number | Date | Country | |
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61642005 | May 2012 | US |