Claims
- 1. An integrated circuit comprising:a first silicon gate structure dielectrically spaced above a first silicon base layer and laterally between a first pair of silicon source/drain structures, wherein an upper surface of said first silicon gate structure is coplanar with upper surfaces of said first pair of silicon source/drain structures; a second silicon gate structure dielectrically spaced above a second silicon base layer and laterally between a second pair of silicon source/drain structures, wherein an upper surface of said second silicon gate structure is coplanar with upper surfaces of said second pair of silicon source/drain structures, and wherein said second silicon base layer is spaced above said first silicon base layer; a first pair of dielectric spacer structures laterally disposed between said first silicon gate structure and said first pair of silicon source/drain structures, wherein upper surfaces of said first pair of dielectric spacer structures are coplanar with said upper surfaces of said first pair of silicon source/drain structures; a second pair of dielectric spacer structures laterally disposed between said second silicon gate structure and said second pair of silicon source/drain structures, wherein upper surfaces of said second pair of dielectric spacer structures are coplanar with said upper surfaces of said second pair of silicon source/drain structures; and an insulating layer disposed above said first silicon gate structure and below said second silicon base layer, such that a lower surface of said insulating layer is adjacent an upper surface of said first silicon gate structure, and an upper surface of said insulating layer is adjacent a lower surface of said second silicon base layer.
- 2. The integrated circuit as recited in claim 1, wherein said first silicon base layer includes a first pair of source/drain regions arranged directly below said first pair of silicon source/drain structures.
- 3. The integrated circuit as recited in claim 1, wherein said second silicon base layer includes a pair of source/drain regions arranged directly below said second pair of silicon source/drain structures.
- 4. The integrated circuit as recited in claim 1, wherein said first pair of dielectric spacer structures and said second pair of dielectric spacer structures comprise silicon nitride.
- 5. The integrated circuit as recited in claim 1, wherein said insulating layer comprises oxide.
- 6. The integrated circuit as recited in claim 1, wherein said second pair of dielectric spacer structures are in contact with interior sidewalls of said second pair of silicon source/drain structures and with sidewalls of said second silicon gate structure.
- 7. The integrated circuit as recited in claim 1, wherein said second pair of dielectric spacer structures are in contact with interior sidewalls of said second pair of silicon source/drain structures and with sidewalls of said second silicon gate structure.
Parent Case Info
This application is a Division of application Ser. No. 08/844,975, filed Apr. 23, 1997, now U.S. Pat. No. 5,851,883.
US Referenced Citations (9)