Claims
- 1. A high density memory module with improved data bus performance comprising:
- a printed circuit card having tabs which interconnect with a connector on a system board, said printed circuit card having a card data bus;
- two or more banks of random access memory devices mounted on said printed circuit card and connected to said card data bus; and
- at least two bus switches, selected ones of the random access memory devices of said two or more banks being connected to said at least two bus switches via said card data bus, said bus switches being enabled responsive to a READ/WRITE selection state of said connected two or more banks.
- 2. The high density memory module recited in claim 1 wherein said random access memory is synchronous dynamic random access memory (SDRAM).
- 3. The high density memory module recited in claim 2, wherein each said SDRAM bank provides a signal indicating a READ/WRITE state, said READ/WRITE state of all said SDRAM banks being combined to generate a signal for enabling said bus switches.
RELATED APPLICATION
The present invention is a continuation in part of U.S. Patent application Ser. No. 08/676,609 entitled "High Density Memory Modules With Improved Data Bus Performance" to Connolly et al., filed Jul. 8, 1996, now U.S. Pat. No. 5,802,395, assigned to the assignee of the present application, now U.S. Pat. No. 5,802,395.
US Referenced Citations (25)
Continuation in Parts (1)
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Number |
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676609 |
Jul 1996 |
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