High density vertical SRAM cell using bipolar latchup induced by gated diode breakdown

Abstract

Area efficient static memory cells and arrays containing p-n-p-n transistors which can be latched in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. Also provided is a CMOS fabrication process to create the cells and arrays.

Description

FIELD OF THE INVENTION

This invention relates generally to non-volatile static memory devices. Particularly, this invention relates to a high density Static Random-Access Memory (SRAM) cell taking advantage of the latch-up phenomenon in a Complementary Metal Oxide Semiconductor (CMOS).

BACKGROUND OF THE INVENTION

One known type of static read/write memory cell is a high-density static random access memory (SRAM). A static memory cell is characterized by operation in one of two mutually-exclusive and self-maintaining operating states. Each operating state defines one of the two possible binary bit values, zero or one. A static memory cell typically has an output which reflects the operating state of the memory cell. Such an output produces a “high” voltage to indicate a “set” operating state. The memory cell output produces a “low” voltage to indicate a “reset” operating state. A low or reset output voltage usually represents a binary value of zero, while a high or set output voltage represents a binary value of one.

A static memory cell is said to be bistable because it has two stable or self-maintaining operating states, corresponding to two different output voltages. Without external stimuli, a static memory cell will operate continuously in a single one of its two operating states. It has internal feedback to maintain a stable output voltage, corresponding to the operating state of the memory cell, as long as the memory cell receives power.

The operation of a static memory cell is in contrast to other types of memory cells such as dynamic cells which do not have stable operating states. A dynamic memory cell can be programmed to store a voltage which represents one of two binary values, but requires periodic reprogramming or “refreshing” to maintain this voltage for more than very short time periods.

A dynamic memory cell has no internal feedback to maintain a stable output voltage. Without refreshing, the output of a dynamic memory cell will drift toward intermediate or indeterminate voltages, resulting in loss of data. Dynamic memory cells are used in spite of this limitation because of the significantly greater packaging densities which can be attained. For instance, a dynamic memory cell can be fabricated with a single MOSFET transistor, rather than the six transistors typically required in a static memory cell.

One of the limitations of static memory cells utilizing both n-channel and p-channel devices (CMOS SPAMS) is their exceptionally large cell areas, typically over 100 F 2 , where F is the minimum feature size. Even using only n-channel devices, cell size in a compact SRAM design is over 5F 2 . See U.S. Pat. No. 5,486,717. The result is much lower densities than for DRAMs, where the cell size is only 6 or 8 F 2 .

Conventional CMOS SRAM cells essentially consist of a pair of cross-coupled inverters as the storage flip-flop or latch, and a pair of pass transistors as the access devices for data transfer into and out of the cell. Thus, a total of six Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), or four MOSFETs plus two very high resistance load devices, are required for implementing a conventional CMOS SRAM cell.

To achieve higher packing densities, several methods are known for reducing the number of devices needed for CMOS SRAM cell implementation, or the number of the devices needed for performing the Read and Write operations. However, increased process complexity, extra masks, and high fabrication cost are required and the corresponding product yield is not high.

For example, K. Sakui, et al., “A new static memory cell based on reverse base current (RBC) effect of bipolar transistor,” IEEE IEDM Tech. Dig., pp. 44-47, December 1988), refers to a Bipolar-CMOS (BICMOS) process in which only two devices are needed for a SRAM cell: one vertical bipolar transistor, and one MOSFET as a pass device. Extra processing steps and increased masks are required, along with special deep isolation techniques, resulting in high fabrication cost and process complexity. Yield of SRAM products utilizing such complex processes is usually low compared with the existing CMOS processes.

A problem with CMOS circuits in general is their propensity to “latchup.” Latchup is a phenomenon that establishes a very low-resistance path between the V DD and V SS power lines, allowing large currents to flow through the circuit. This can cause the circuit to cease functioning, or even to destroy itself due to heat damage caused by high power dissipation.

The susceptibility to latchup arises from the presence of complementary parasitic bipolar transistor structures, which result from the fabrication of the complementary MOS devices in CMOS structures. Since they are in close proximity to one another, the complementary bipolar structures can interact electrically to form device structures which behave like p-n-p-n diodes. In the absence of triggering currents, such diodes act as reverse-biased junctions and do not conduct. Such triggering currents, however, may be and in practice are established in any one or more of a variety of ways, e.g., terminal overvoltage stress, transient displacement currents, ionizing radiation, or impact ionization by hot electrons.

Gregory, B. L., et al., “Latchup in CMOS integrated circuits,” IEEE Trans. Nuci. Sci. (USA), Vol. 20, no. 6, p. 293-9, proposes several techniques designed to eliminate latchup in future CMOS applications. Other authors, such as Fang, R. C., et al., “Latchup model for the parasitic p-n-p-n path in bulk CMOS,” IEEE Transactions on Electron Devices , Vol. ED-31, no. 1, pp. 113-20, provide models of the latchup phenomenon in CMOS circuits in an effort to facilitate design optimizations avoiding latchup.

The present invention takes advantage of the normally undesirable latchup phenomenon in CMOS circuits to construct a compact static memory cell.

SUMMARY OF THE INVENTION

The present invention provides area efficient static memory cells and memory arrays by the use of parasitic bipolar transistors which can be latched in a bistable on state with small area transistors. Each bipolar transistor memory cell includes a gate which is pulse biased during the write operation to latch the cell. These cells can be realized utilizing CMOS technology to create vertical structures in trenches with a minimum of masking steps and minimal process complexity.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates one embodiment of a SRAM cell array with latchup and gated diode according to the present invention.

FIGS. 2 ( a )- 2 ( f ) depict a SRAM cell with latchup and gated diode and circuit diagrams.

FIGS. 3 ( a ) and 3 ( b ) illustrate the current-voltage characteristics and avalanche multiplication in the gated diode structure of the SRAM cell of FIGS. 2 ( a )- 2 ( f ), and the related structure responsible for these characteristics, respectfully.

FIG. 4 depicts the blocking, write and latchup states of the SRAM cell of FIG. 2 .

FIGS. 5 ( a ) and 5 ( b ) depict circuit diagrams for the SRAM cell having gated diode induced latchup of FIGS. 2 ( a )- 2 ( f ).

FIGS. 6 ( a ) and 6 ( b ) illustrate a SRAM cell array with interconnect circuitry.

FIG. 7 shows an in-process wafer for producing a SPAM cell arty using oxide isolation on a p+ substrate.

FIG. 8 shows an in-process wafer for producing a SRAM cell array using an isolated inverted structure on a p-type substrate.

FIG. 9 shows an in-process wafer for producing a non-inverted SRAM cell array using an additional n-type layer to achieve isolation on a p-type substrate.

FIG. 10 show the wafer of FIG. 9 at a processing step subsequent that shown in FIG. 9 .

FIG. 11 shows the wafer of FIG. 9 at a processing step subsequent to that shown in FIG. 10 .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

The terms wafer or substrate used in the following description include any semiconductor-based structure having an exposed silicon surface in which to form the structure of this invention. Wafer and substrate are to be understood as including doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure or foundation. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

Referring now to the drawings, where like elements are designated by like reference numerals, an embodiment of the SRAM device array 9 of the present invention is shown in FIG. 1 . The array 9 is comprised of a plurality of vertical parasitic bipolar transistor pairs on n-type layer 34 on p-type silicon substrate 33 . Vertical transistor pairs or devices, noted generally 10 , are separated from each other by isolation trenches 7 , 8 . Each parasitic bipolar transistor device 10 has dimensions of one F by one F, and each isolation trench 7 , 8 is preferably one F wide. Thus, with the inclusion of transistor to transistor isolation, the area per programmed device cell is 4 F 2 (2 F ×2 F).

Referring to FIG. 2 , a static memory cell, generally designated 5 , comprises two complementary bipolar transistors which can latch-up, normally an undesirable characteristic in CMOS but utilized here to construct a compact SRAM cell. If vertical structures are used, a 4 F 2 cell results as also shown in FIG. 2 ( d ). As shown in FIGS. 2 and 3 , p+ region 17 , n-region 16 , and p-region 15 comprise a p-n-p bipolar transistor 18 ; and n+ region 14 , p-region 15 , and n-region 16 comprise an n-p-n bipolar transistor 19 . Thus, each parasitic bipolar transistor device 10 can be considered as a p-n-p transistor 18 and an n-p-n transistor 19 connected with the collector of one transistor attached to the base of the other, and vice versa, as shown in FIGS. 3 ( b ) and 5 ( b ). The center junction (J 2 ) acts as a collector of electrons from (J 1 ) and of holes from (J 3 ). In equilibrium, there is at each junction a depletion region with a built-in potential determined by the impurity doping profile. When a positive voltage is applied to the anode, junction (J 2 ) will become reverse-biased, while (J 1 ) and (J 3 ) will be forward biased.

There are three sets of interconnects in the device array 9 . Row address line 11 is in connection with lowermost p+ region 17 of each transistor device 10 . Column address line 12 is in connection with the uppermost n+ region 14 , and write row address line 25 is in connection with gate 13 . A high density array is achieved by the use of vertical devices and by placing gate 13 in the isolation trench 7 . Gate 13 gates the central p-n junction (J 2 ) of each transistor structure, as shown in FIGS. 1 , 2 ( d ) and ( f ), and runs within isolation trench 7 on one side of each parasitic bipolar transistor device 10 .

Referring to FIG. 2 , showing static memory cell 5 , containing gate 13 , FIG. 2 ( b ) shows memory cell 5 in the latched condition. FIG. 2 ( c ) shows memory cell 5 in the blocking (not latched) condition. These conditions reflect CMOS latchup action, initiated by gated diode current multiplication and avalanche breakdown from gate 13 , as discussed in detail below. Gate 13 induces latchup in the parasitic bipolar transistor device 10 , thus creating one of the two bistable states for the static memory cell.

If bipolar transistors 18 , 19 are off, then the cell will block and not become latched until the power supply voltage, V DD , becomes very high. However, the cell can be induced to latch up at low power supply voltages of a few volts by the application of a pulsed gate bias, thus inducing avalanche multiplication and breakdown in the gated diode structure in the center p-n junction (J 2 ) as shown in FIGS. 3 and 4 . Referring to FIG. 3 ( b ), inversion region 20 in central p-type region 15 , and depletion region 21 in central n-type region 16 , occur when a pulse of negative voltage is applied to gate 13 and result in gated diode avalanche breakdown and current multiplication in region 22 .

To turn on the device, it is necessary to introduce an external stimuli, e.g., base current by initiating current multiplication in the gated diode with a pulsed gate bias and higher column voltage. The operation must be designed such that pulsing yields enough current such that the sum of the common base current gains, α 1 and α 2 , of bipolar transistors 18 , 19 exceeds one. The bias applied to induce latchup is “pulsed” in the sense that it is only applied to initiate latchup. The cell is stable in the latched condition as a result of the pulse initiated latchup, which occurs during the “write” operation as discussed below.

The collector and base currents (I C and I B , respectively) and the common base forward current transfer ratios or “current gain” α 1 and α 2 are shown in FIG. 5 ( a ). From FIG. 5 ( a ), the collector current of the n-p-n transistor 19 provides the base drive for the p-n-p transistor 18 . Also, the collector current of the p-n-p transistor 18 supplies the base drive for the n-p-n transistor 19 . The base current of p-n-p transistor 18 , I 81 is given by

I B1 =(1−α 1 ) I A

which is supplied by the collector of n-p-n transistor 19 . The collector current of n-p-n transistor 19 with a common base current gain, α 2, is given by

I C2 =α 2 I K

By equating I B1 and I C2 with I AVALANCHE :

I B1 −I AVALANCHE =i C2

Since I A =I K , when the collector-base reverse saturation currents approach zero (neglecting leakage), then: $$ I A = I AVALANCHE 1 - ( α 1 + α 2 )

which gives the static characteristic of the device up to the breakdown voltage. I AVALANCHE is small, so I A is small, unless (α 1 +α 2 ) approaches unity; at this point, the denominator of the equation approaches zero, and latch up will occur.

An illustration of the current multiplication and breakdown voltages required in the gated diode is given in FIG. 3 ( a ). Diode dopings of over 10 18 /cm 3 will result in breakdown voltages (V B ) of only a few volts. Region 24 in FIG. 3 ( a ) shows where avalanche multiplication and breakdown (due to tunneling) occur, in terms of voltage V B and dopant concentration in the p-n-p-n parasitic bipolar transistor device 10 . The preferred dopant concentration for the central p-n diode is above 10 17 atoms per cm 3 , with concentrations equal to or above 10 18 atoms per cm 3 being most preferred.

Referring now to FIG. 6 , the array structure of the CMOS SRAM includes column decoder 26 and row decoder 27 . Data can be read most conveniently by addressing a row and a column and increasing the power supply voltage across device 10 to 0.9 V or more at the coincidence of the address. If the cell is latched up, a large current will be sensed between these row and column lines. If not latched, there will be little extra current. When the cell is not addressed, it can be left in some low voltage state with V DD around 0.7 V to 0.8 V to reduce power consumption. Read can be accomplished by lowering the row address voltage.

Write can be accomplished by a coincidence of address in the polysilicon gate lines 25 and high column address voltages, to induce carrier multiplication in the gated diode and turn the transistors on strongly. Writing “one” or turning the transistors on and latching up the cell can be achieved when the cell is in a higher V DD . voltage state.

It is most convenient to “write” a row or word as one operation. To do so, the row voltage comes positive to leave some very low value like 0.4 V or less across transistors in the row to turn off any transistors which are latched up, thus writing “zero” in all cells along the row or word line. Sufficient time is then allowed for any excess base charge in the latched-up cells to recombine. Following this, “ones” are written into selected locations along the word line by a coincidence of row gate line address and selected high column voltages.

In 0.2 micron technology, at moderate forward bias during the read operation, transistor devices 10 will provide about 100 μA of current. If this is read in 1.6 nanoseconds, then the total signal will be one million electrons, which is comparable to the read signal in DRAMs and easily sensed above any noise. A 4 F 2 cell will result in an area of less than 1 cm 2 for a 128 Mbit SRAM in 0.2 micron technology. If the standby current in each cell is 10 nanoamperes, then the standby current will be 1.28 A and the power dissipation about 1 Watt or 1 Watt/cm 2 , which is easily dissipated. A ratio of read current to standby current of 100 μA/0.01 μA can be achieved since the read current is an exponential function of voltage, as shown in FIG. 4 . These considerations can readily be scaled to other size, or minimum feature size, dimensions.

If planar CMOS peripheral circuits are to be used, the substrate array and peripheral circuit doping profiles must be separated. The exact realization depends on the type of substrate to be used and the technology used to isolate the array structures from the substrate. FIG. 7 illustrates peripheral area 31 , array area 32 , epitaxial p-layers 28 (EPI) on p+ substrate 29 , and oxide isolation layer 30 undercutting the p+ columns in the array area. FIG. 8 illustrates the use of a p-type substrate 33 and inversion of the array structure to achieve junction isolation. FIG. 9 illustrates an array structure which is not inverted, but an additional n-type layer 34 is used to achieve junction isolation on p-type substrate 33 . The preferred embodiment described in detail below relates to this latter structure, but the techniques described are also applicable to other structures.

The device array is manufactured through a process described as following, and illustrated by FIGS. 9 through 11 and FIG. 1 . First, a silicon substrate 33 is selected as the base for the device array. The silicon substrate 33 may be doped or undoped, but a doped p-type wafer is preferred. Next, an oxide pad layer 35 is grown or deposited on top of the silicon substrate 33 by means of, for example, thermal oxidation of the silicon substrate 33 .

A resist (not shown) and mask (not shown) are applied to cover peripheral circuit area 31 and expose array area 32 , and photolitographic techniques are used to define the array area 32 to be etched out.

An etchant is then applied to define an array window in the oxide pad 35 . After removing the resist, the remaining oxide pad 35 is then used as a mask to directionally etch the silicon substrate 33 to a depth of preferably about 1 μm. Any suitable directional etching process may be used, including, for example, Reactive Ion Etching (RIE), to form an array trench in array area 32 of substrate 33 .

An oxide layer 36 is then grown or deposited to cover the bare silicon 33 . Oxide layer 36 is then directionally etched to remove oxide from the trench bottom, while leaving oxide layer 36 on the vertical side walls of the array trench. Selective epitaxial silicon is then grown in the array trench in the following preferred doping profile: 0.1 μm n-, 0.3 μm p+, 0.2 μm n-, 0.2 μm p-, 0.2 μm n+, resulting in the cross section as shown in FIG. 9 .

Oxide pad 35 is then stripped from the surface of the peripheral area 31 . An oxide pad (not shown) of about 10 nm is then grown atop the exposed n+ epitaxial silicon layer in the array area. Next, a nitride pad 37 is formed by depositing a layer of silicon nitride (Si 3 N 4 ) (“nitride”) by CVD or other means, on top of the pad oxide. The nitride pad 37 is preferably about 60-100 nm thick.

The next step is to define a first set of trenches 8 of the minimum dimension width and space in the column direction. A resist (not shown) and mask (not shown) are applied, and photolithographic techniques are used to define the area to be etched-out. A directional etching process such as RIE is used to etch through the pad layers 35 and 37 and into the silicon to a depth sufficient to expose the buried p+ layer (i.e., below junction 3 (J 3 )).

The resist is then removed. The set of trenches 8 is defined by the sidewalls of the p-n-p-n epitaxial layers. The trenches are then filled with silicon oxide by CVD and the surface is planarized by CMP, stopping on the nitride pad 37 .

A second nitride pad layer 37 ′ is then applied, preferably by CVD, to a thickness of about 100 nm. Photolithography is used to define a second set of trenches 7 orthogonal to the first set of trenches 8 . Resist and mask are applied to define the minimum dimension width and space stripes in the row direction. The nitride pad layer and the array layer are etched out by a directional etching process such as RIE to form sidewalls 38 orthogonal to the sidewalls which define the first set of trenches 8 . After etching through the nitride pad to expose alternate silicon and oxide regions, either a simultaneous silicon/oxide etchant or a sequential etch of oxide and silicon may be used to form trenches 7 of uniform depth in the row direction and of sufficient depth to expose the bottom n-layer as shown in FIG. 10 . Etching is continued down to the level of the n-layer below junction 4 (J 4 ), and then the resist is removed.

Oxide layer 40 is then deposited to fill the trenches up to n-type layer (i.e., above J 2 ). Oxide 40 may be planarized by CMP and is preferably deposited by CVD, and may then be etched back to below J 2 , as shown in FIG. 11 .

A thin gate oxide 39 is then grown on trench walls 38 . A p+ polysilicon layer 41 is then formed by deposition of doped polysilicon, preferably by CVD. The thickness of the p+ polysilicon layer 41 is preferable less than or equal to about one-third the minimum lithographic dimension.

Referring now to FIG. 1 , the next step is to remove excess polysilicon by directional etching of exposed portions of the polysilicon layer 41 so that the layer is recessed below the level of junction 1 (J 1 ). Resist and mask are applied to cover alternate trench walls. Polysilicon layer 41 is etched to remove exposed polysilicon and leave remaining polysilicon as gates 13 on one sidewall of each trench as shown in FIG. 1 .

The device array then undergoes a finishing process. Trenches 7 are filled with silicon oxide and the surface of the device array is planarized, by CVD and CMP, respectively, or other suitable processes. Conventional processing methods may then be used to form contact holes and metal wiring to connect gate lines and to equip the device array for peripheral circuits. The final structure of the device array is as shown in FIG. 1 .

The process sequence described and illustrated above provides for the formation of minimum dimension programmable devices. It follows that other structures may also be fabricated, different methods of isolating the bipolar transistors, and different methods of forming the p-n-p-n diodes, such as single dopant and implant techniques, may be realized, by process integration with common process steps.

The above description and drawings illustrate preferred embodiments which achieve the objects, features and advantages of the present invention. It is not intended that the present invention be limited to the illustrated embodiments. Any modification of the present invention which comes within the spirit and scope of the following claims should be considered part of the present invention.

Claims

1. A memory cell, comprising:a gated diode structure having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latchup of said diode structure; and a gate structure, said gate structure gating said diode structure, wherein said diode structure is isolated by trenches, and said gate structure is adjacent to said diode structure and at least partially within one of said trenches, and wherein said memory cell has an area of about 4 F2 where F is the minimum lithographic dimension.

2. The memory cell of claim 1 wherein said diode structure is a p-n-p-n diode.

3. The memory cell of claim 2 wherein said p-n-p-n diode comprises two complementary vertical bipolar transistor structures, wherein said transistor structures are stacked in a single vertical column.

4. The memory cell of claim 3 wherein said complementary bipolar transistor structures comprise a p-n-p transistor and an n-p-n transistor, and the collector region of said p-n-p transistor is connected with the base region of said n-p-n transistor.

5. The memory cell of claim 4 wherein said gate structure of said p-n-p-n diode spans the central p-n junction of said diode.

6. The memory cell of claim 5 wherein the p and n regions of said junction have respective p and n dopant concentrations of at least about 1018 atoms per cm3.

7. The memory cell of claim 1 wherein said gate-induced latchup is achieved by a pulsed gate bias.

8. The memory cell of claim 1 wherein said cell is a static random access memory cell.

9. A circuit for storing information as one of at least two possible bistable current states, comprising:at least one vertically stacked p-n-p-n structure comprising complementary transistors including a p-n-p transistor and a n-p-n transistor; and a single transistor gate shared by the p-n-p transistor and the n-p-n transistor and spanning the central n-p junction of said p-n-p-n structure wherein said circuit is a static random access memory cell having an area of about 4 F2 where F is the minimum lithographic dimension.

10. The circuit of claim 9 wherein said transistor gate operates to latch-up said p-n-p-n structure and said latch-up results in one of said bistable current states.

11. The circuit of claim 10 further comprising a substrate for supporting said p-n-p-n structure.

12. The circuit of claim 11 wherein said p-n-p-n structure is vertically disposed in a trench within said substrate.

13. The circuit of claim 9 wherein said central n-p junction contains a dopant concentration of at least about 1018 atoms per cm3.

14. A SRAM array, comprisinga substrate; a plurality of vertical p-n-p-n transistors; a first set of isolation trenches between said p-n-p-n transistors for isolating said transistors in a first direction; a second set of isolation trenches orthogonal to said first set of trenches for isolating said transistors in a second direction; gate lines in one of said first or second sets of trenches and connecting the central p-n junctions of at least some of said plurality of transistors; and an insulating material layer between each of said p-n-p-n transistors and the substrate, horizontally isolating the transistors.

15. The SRAM array of claim 14 wherein said insulating material is an oxide.

16. The SRAM array of claim 14 wherein said insulating material is a buried n-layer.

17. The SRAM array of claim 14 wherein said plurality of p-n-p-n transistors are inverted transistors and are supported on a p-type substrate.

18. A computer system, comprising:a processor; and a memory circuit connected to the processor, the memory circuit containing at least one memory cell comprising a gated p-n-p-n diode having bistable current states for storing information, one of said current states being achieved by operation of gate-induced latch-up of said p-n-p-n diode, wherein said memory cell has an area of about 4 F2 where F is the minimum lithographic dimension.

19. The computer system of claim 18 wherein the memory cell comprises two complementary bipolar transistors.

20. The computer system of claim 19 wherein the complementary bipolar transistors comprise a p-n-p transistor and an n-p-n transistor and the collector region of said p-n-p transistor is connected with the base region of said n-p-n transistor.

21. The computer system of claim 20 wherein said gated p-n-p-n diode has a gate in connection with the central p-n junction of said diode.

22. The computer system of claim 21 wherein said gate-induced latchup is achieved by a pulsed gate bias.

23. The computer system of claim 22 wherein said memory cell is a static random access memory cell.

24. A method of storing a binary logic value comprising:inducing latch-up in a gated diode, wherein the act of inducing latch-up comprises application of a pulsed gate bias and inducement of carrier multiplication and breakdown in the gated diode.

25. The method of claim 24 wherein said pulsed gate bias is approximately one volt.

26. The method of claim 24 wherein the act of inducing latch-up further comprises application of a positive voltage.

27. The method of claim 26 wherein said positive voltage is approximately one volt.