The present invention relates to a high frequency amplifier that amplifies first and second signals that are differential signals.
Non-Patent Literature 1 set out below discloses a high frequency amplifier that amplifies differential signals using a differential amplifier.
Since a power supply is virtually short-circuited, the differential signals amplified by the differential amplifier are not fed back to the differential input terminal of the differential amplifier via the power supply.
When a differential amplifier, which is a conventional high frequency amplifier, amplifies differential signals, in-phase signals such as noise may be superimposed on the differential input terminal of the differential amplifier. Since a power supply is not virtually short-circuited, the in-phase signals may be fed back to the differential input terminal of the differential amplifier via the power supply. There has been a problem that, since the in-phase signals may be fed back to the differential input terminal of the differential amplifier via the power supply, a circuit in which a high frequency amplifier is mounted may oscillate.
The present invention has been conceived to solve the problems as described above, and it is an object of the present invention to obtain a high frequency amplifier capable of suppressing output of in-phase signals.
A high frequency amplifier according to the present invention includes a first transistor for amplifying a first signal, a second transistor for amplifying a second signal that is a differential signal with respect to the first signal, a polyphase filter that includes a first input terminal connected to an output terminal of the first transistor, a second input terminal connected to an output terminal of the second transistor, and first to fourth output terminals, generates a first differential signal from the first signal amplified by the first transistor and outputs the first differential signal from the first and third output terminals, and generates a second differential signal from the second signal amplified by the second transistor and outputs the second differential signal from the first and third output terminals, a plurality of loads having one end connected to each of the first and third output terminals of the polyphase filter and the other end connected to a power supply, and a plurality of amplifier output terminals connected to each of the first and third output terminals of the polyphase filter.
According to the present invention, there is provided a polyphase filter that generates the first differential signal from the first signal amplified by the first transistor, outputs the first differential signal from the first and third output terminals, generates the second differential signal from the second signal amplified by the second transistor, and outputs the second differential signal from the first and third output terminals, whereby output of in-phase signals can be suppressed.
Hereinafter, embodiments of the present invention will be described to explain the present invention in more detail with reference to the accompanying drawings.
In
The first signal input terminal 1a is a terminal for receiving the first signals. The second signal input terminal 1b is a terminal for receiving the second signals.
A transistor pair 2 includes a first transistor 2-1 and a second transistor 2-2.
Each of the first transistor 2-1 and the second transistor 2-2 is implemented by, for example, a bipolar transistor, a metal-oxide semiconductor field-effect transistor (MOSFET), or the like.
In the first transistor 2-1, a base terminal that is a control terminal is connected to the first signal input terminal 1a, an emitter terminal is connected to a current source 3, and a collector terminal that is an output terminal is connected to a first input terminal 5a of the polyphase filter 5.
The first transistor 2-1 amplifies the first signals input from the first signal input terminal 1a, and outputs the amplified first signals to the first input terminal 5a of the polyphase filter 5.
In the second transistor 2-2, a base terminal that is a control terminal is connected to the second signal input terminal 1b, an emitter terminal is connected to the current source 3, and a collector terminal that is an output terminal is connected to a second input terminal 5b of the polyphase filter 5.
The second transistor 2-2 amplifies the second signals input from the second signal input terminal 1b, and outputs the amplified second signals to the second input terminal 5b of the polyphase filter 5.
One end of the current source 3 is connected to the emitter terminal of the first transistor 2-1 and the emitter terminal of the second transistor 2-2, and the other end is connected to the ground.
A transistor load 4 includes the polyphase filter 5, a load group 6, and a power supply 7.
The transistor load 4 is a load connected to each of the output terminal of the first transistor 2-1 and the output terminal of the second transistor 2-2.
In order to increase the gain of the high frequency amplifier including the transistor pair 2, it is necessary to increase the impedance of the transistor load 4.
The polyphase filter 5 includes the first input terminal 5a connected to the output terminal of the first transistor 2-1, and the second input terminal 5b connected to the output terminal of the second transistor 2-2.
In
The polyphase filter 5 includes a first output terminal 5-1, a second output terminal 5-2, a third output terminal 5-3, and a fourth output terminal 5-4.
In
When the first signals amplified by the first transistor 2-1 are input from the first input terminal 5a, the polyphase filter 5 generates first differential signals from the first signals, and outputs the first differential signals from the first output terminal 5-1 and the third output terminal 5-3.
Further, when the second signals amplified by the second transistor 2-2 are input from the second input terminal 5b, the polyphase filter 5 generates second differential signals from the second signals, and outputs the second differential signals from the first output terminal 5-1 and the third output terminal 5-3.
The load group 6 includes a load 6a and a load 6b.
Each of the load 6a and the load 6b is implemented by, for example, a resistor, an inductive element, or the like.
One end of the load 6a is connected to the first output terminal 5-1 of the polyphase filter 5, and the other end is connected to the power supply 7.
One end of the load 6b is connected to the third output terminal 5-3 of the polyphase filter 5, and the other end is connected to the power supply 7.
A differential output terminal 8 includes an amplifier output terminal 8a and an amplifier output terminal 8b.
The amplifier output terminal 8a is connected to the first output terminal 5-1 of the polyphase filter 5.
The amplifier output terminal 8b is connected to the third output terminal 5-3 of the polyphase filter 5.
Hereinafter, an internal circuit in the case where the polyphase filter 5 is an open input type will be described.
In
One end of a resistor 12 is connected to the second output terminal 5-2.
One end of a resistor 13 is connected to the second input terminal 5b, and the other end is connected to the third output terminal 5-3.
One end of a resistor 14 is connected to the fourth output terminal 5-4.
One end of a capacitive element 15 is connected to the first output terminal 5-1, and the other end is connected to the other end of the resistor 12.
One end of a capacitive element 16 is connected to the second output terminal 5-2, and the other end is connected to the second input terminal 5b.
One end of a capacitive element 17 is connected to the third output terminal 5-3, and the other end is connected to the other end of the resistor 14.
One end of a capacitive element 18 is connected to the fourth output terminal 5-4, and the other end is connected to the first input terminal 5a.
In the case where the polyphase filter 5 is an input short circuit type, the other end of the resistor 12 and the other end of the capacitive element 15 are connected to the first input terminal 5a, as illustrated in
Further, the other end of the resistor 14 and the other end of the capacitive element 17 are connected to the second input terminal 5b.
Operation of the polyphase filter 5 in the case of the open input type and operation of the polyphase filter 5 in the case of the input short circuit type are similar.
Next, the operation will be described.
When the first signals are input from the first signal input terminal 1a, the first transistor 2-1 amplifies the first signals, and outputs the amplified first signals to the first input terminal 5a of the polyphase filter 5.
When the second signals are input from the second signal input terminal 1b, the second transistor 2-2 amplifies the second signals, and outputs the amplified second signals to the second input terminal 5b of the polyphase filter 5.
When the first signals amplified by the first transistor 2-1 are input from the first input terminal 5a, the polyphase filter 5 generates first differential signals from the first signals, and outputs the first differential signals from the first output terminal 5-1 and the third output terminal 5-3.
Further, when the second signals amplified by the second transistor 2-2 are input from the second input terminal 5b, the polyphase filter 5 generates second differential signals from the second signals, and outputs the second differential signals from the first output terminal 5-1 and the third output terminal 5-3.
In the example of
Further, the polyphase filter 5 generates, as second differential signals, differential signals including signals having a phase of 0 degrees and signals having a phase of 180 degrees, outputs the signals having the phase of 0 degrees from the first output terminal 5-1, and outputs the signals having the phase of 180 degrees from the third output terminal 5-3.
Accordingly, at the first output terminal 5-1 of the polyphase filter 5, the signals having the phase of 0 degrees included in the first differential signals and the signals having the phase of 0 degrees included in the second differential signals are subject to in-phase synthesis, thereby amplifying the signals having the phase of 0 degrees.
Further, at the third output terminal 5-3 of the polyphase filter 5, the signals having the phase of 180 degrees included in the first differential signals and the signals having the phase of 180 degrees included in the second differential signals are subject to in-phase synthesis, thereby amplifying the signals having the phase of 180 degrees.
When the signals having the phase of 0 degrees are output from the first output terminal 5-1 of the polyphase filter 5, signals having a phase of 0 degrees are output from the amplifier output terminal 8a.
Further, when the signals having the phase of 180 degrees are output from the third output terminal 5-3 of the polyphase filter 5, signals having a phase of 180 degrees are output from the amplifier output terminal 8b.
Note that, at the time of generating the first and second differential signals, the polyphase filter 5 generates third differential signals having a phase shifted by 90 degrees from that of the first differential signals, and outputs the third differential signals from the second output terminal 5-2 and the fourth output terminal 5-4. That is, the polyphase filter 5 generates, as the third differential signals, differential signals including signals having a phase of 90 degrees and signals having a phase of 270 degrees, outputs the signals having the phase of 90 degrees from the second output terminal 5-2, and outputs the signals having the phase of 270 degrees from the fourth output terminal 5-4.
Further, the polyphase filter 5 generates fourth differential signals having a phase shifted by 90 degrees from that of the second differential signals, and outputs the fourth differential signals from the second output terminal 5-2 and the fourth output terminal 5-4. That is, the polyphase filter 5 generates, as the fourth differential signals, differential signals including signals having a phase of 90 degrees and signals having a phase of 270 degrees, outputs the signals having the phase of 90 degrees from the second output terminal 5-2, and outputs the signals having the phase of 270 degrees from the fourth output terminal 5-4.
However, since each of the second output terminal 5-2 and the fourth output terminal 5-4 of the polyphase filter 5 is open, the signals having the phase of 90 degrees are not output from the output terminal 5-2 to the differential output terminal 8. In addition, the signals having the phase of 270 degrees are not output from the output terminal 5-4 to the differential output terminal 8.
When the first transistor 2-1 amplifies the first signals and the second transistor 2-2 amplifies the second signals, in-phase signals having a phase of 0 degrees may be input to the differential input terminal 1.
In the case where the in-phase signals having the phase of 0 degrees are input to the differential input terminal 1, the in-phase signals are amplified by each of the first transistor 2-1 and the second transistor 2-2. Thereafter, as illustrated in
In this case, the polyphase filter 5 generates differential signals including signals having a phase of 0 degrees and signals having a phase of 180 degrees from the signals having the phase of 0 degrees input from the first input terminal 5a, outputs the signals having the phase of 0 degrees from the first output terminal 5-1, and outputs the signals having the phase of 180 degrees from the third output terminal 5-3.
Further, the polyphase filter 5 generates differential signals including signals having a phase of 180 degrees and signals having a phase of 0 degrees from the signals having the phase of 0 degrees input from the second input terminal 5b, outputs the signals having the phase of 180 degrees from the first output terminal 5-1, and outputs the signals having the phase of 0 degrees from the third output terminal 5-3.
Further, the polyphase filter 5 generates differential signals including signals having a phase of 90 degrees and signals having a phase of 270 degrees from the signals having the phase of 0 degrees input from the first input terminal 5a, outputs the signals having the phase of 90 degrees from the second output terminal 5-2, and outputs the signals having the phase of 270 degrees from the fourth output terminal 5-4.
Further, the polyphase filter 5 generates differential signals including signals having a phase of 270 degrees and signals having a phase of 90 degrees from the signals having the phase of 0 degrees input from the second input terminal 5b, outputs the signals having the phase of 270 degrees from the second output terminal 5-2, and outputs the signals having the phase of 90 degrees from the fourth output terminal 5-4.
As a result, at the first output terminal 5-1 of the polyphase filter 5, the signals having the phase of 0 degrees, which are generated from the signals having the phase of 0 degrees input from the first input terminal 5a, and the signals having the phase of 180 degrees, which are generated from the signals having the phase of 0 degrees input from the second input terminal 5b, cancel each other out.
Further, at the third output terminal 5-3 of the polyphase filter 5, the signals having the phase of 180 degrees, which are generated from the signals having the phase of 0 degrees input from the first input terminal 5a, and the signals having the phase of 0 degrees, which are generated from the signals having the phase of 0 degrees input from the second input terminal 5b, cancel each other out.
At the second output terminal 5-2 of the polyphase filter 5, the signals having the phase of 90 degrees, which are generated from the signals having the phase of 0 degrees input from the first input terminal 5a, and the signals having the phase of 270 degrees, which are generated from the signals having the phase of 0 degrees input from the second input terminal 5b, cancel each other out.
Furthermore, at the second output terminal 5-4 of the polyphase filter 5, the signals having the phase of 270 degrees, which are generated from the signals having the phase of 0 degrees input from the first input terminal 5a, and the signals having the phase of 90 degrees, which are generated from the signals having the phase of 0 degrees input from the second input terminal 5b, cancel each other out.
Therefore, the output of the in-phase signals from the polyphase filter 5 is suppressed.
As apparent from the above, according to the first embodiment, there is provided the polyphase filter 5 that generates the first differential signals from the first signals amplified by the first transistor 2-1, outputs the first differential signals from the first output terminal 5-1 and the third output terminal 5-3, generates the second differential signals from the second signals amplified by the second transistor 2-2, and outputs the second differential signals from the first output terminal 5-1 and the third output terminal 5-3, whereby the output of the in-phase signals can be suppressed.
In the first embodiment, an exemplary case where the load group 6 includes the load 6a and the load 6b, and the differential output terminal 8 includes the amplifier output terminal 8a and the amplifier output terminal 8b is described.
However, this is merely an example, and for example, the load group 6 may include loads 6-1 to 6-4, and the differential output terminal 8 may include amplifier output terminals 8-1 to 8-4, as illustrated in
In
One end of the load 6-1 is connected to the first output terminal 5-1 of the polyphase filter 5, and the other end is connected to the power supply 7.
One end of the load 6-2 is connected to the second output terminal 5-2 of the polyphase filter 5, and the other end is connected to the power supply 7.
One end of the load 6-3 is connected to the third output terminal 5-3 of the polyphase filter 5, and the other end is connected to the power supply 7.
One end of the load 6-4 is connected to the fourth output terminal 5-4 of the polyphase filter 5, and the other end is connected to the power supply 7.
The amplifier output terminal 8-1 is connected to the first output terminal 5-1 of the polyphase filter 5.
The amplifier output terminal 8-2 is connected to the second output terminal 5-2 of the polyphase filter 5.
The amplifier output terminal 8-3 is connected to the third output terminal 5-3 of the polyphase filter 5.
The amplifier output terminal 8-4 is connected to the fourth output terminal 5-4 of the polyphase filter 5.
In the case of the high frequency amplifier illustrated in
Further, the signals having the phase of 180 degrees are output from the third output terminal 5-3 of the polyphase filter 5, and the signals having the phase of 180 degrees are output from the amplifier output terminal 8-3.
At the second output terminal 5-2 of the polyphase filter 5, the signals having the phase of 90 degrees included in the first differential signals and the signals having the phase of 90 degrees included in the second differential signals are subject to in-phase synthesis, thereby amplifying the signals having the phase of 90 degrees.
Further, at the fourth output terminal 5-4 of the polyphase filter 5, the signals having the phase of 270 degrees included in the first differential signals and the signals having the phase of 270 degrees included in the second differential signals are subject to in-phase synthesis, thereby amplifying the signals having the phase of 270 degrees.
As a result, the signals having the phase of 90 degrees are output from the second output terminal 5-2 of the polyphase filter 5, and the signals having the phase of 90 degrees are output from the amplifier output terminal 8-2.
Further, the signals having the phase of 270 degrees are output from the fourth output terminal 5-4 of the polyphase filter 5, and the signals having the phase of 270 degrees are output from the amplifier output terminal 8-4.
In the first embodiment, an exemplary case where the load group 6 includes the load 6a and the load 6b is described.
However, this is merely an example, and for example, the load group 6 may include the loads 6-1 to 6-4, as illustrated in
In the example of
Note that the other end of the load 6-2 and the other end of the load 6-4, which are not connected to the amplifier output terminal, are connected to the ground.
In the first embodiment, an exemplary case where the polyphase filter 5 includes the capacitive elements 15 to 18 has been described.
In a second embodiment, an exemplary case where a polyphase filter 5 includes a first to fourth inductive elements 25 to 28 will be described.
In
The polyphase filter 5 includes a first resistor 21, a second resistor 22, a third resistor 23, a fourth resistor 24, a first inductive element 25, a second inductive element 26, a third inductive element 27, and a fourth inductive element 28.
The polyphase filter 5 is configured in such a manner that the first resistor 21, the first inductive element 25, the third resistor 23, the second inductive element 26, the second resistor 22, the third inductive element 27, the fourth resistor 24, and the fourth inductive element 28 are annularly connected in that order.
Specifically, they are connected as follows.
One end of the first resistor 21 is connected to a first input terminal 5a, and the other end is connected to a first output terminal 5-1.
One end of the second resistor 22 is connected to a second input terminal 5b, and the other end is connected to a third output terminal 5-3.
One end of the third resistor 23 is connected to the other end of the first inductive element 25, and the other end is connected to a second output terminal 5-2.
One end of the fourth resistor 24 is connected to the other end of the third inductive element 27, and the other end is connected to a fourth output terminal 5-4.
One end of the first inductive element 25 is connected to the first output terminal 5-1, and the other end is connected to one end of the third resistor 23.
One end of the second inductive element 26 is connected to the second input terminal 5b, and the other end is connected to the second output terminal 5-2.
One end of the third inductive element 27 is connected to the third output terminal 5-3, and the other end is connected to one end of the fourth resistor 24.
One end of the fourth inductive element 28 is connected to the first input terminal 5a, and the other end is connected to the fourth output terminal 5-4.
Next, the operation will be described.
When the first signals are input from the first signal input terminal 1a, the first transistor 2-1 amplifies the first signals, and outputs the amplified first signals to the first input terminal 5a of the polyphase filter 5.
When the second signals are input from the second signal input terminal 1b, the second transistor 2-2 amplifies the second signals, and outputs the amplified second signals to the second input terminal 5b of the polyphase filter 5.
When the first signals amplified by the first transistor 2-1 are input from the first input terminal 5a, the polyphase filter 5 generates first differential signals from the first signals, and outputs the first differential signals from the first output terminal 5-1 and the third output terminal 5-3.
Further, when the second signals amplified by the second transistor 2-2 are input from the second input terminal 5b, the polyphase filter 5 generates second differential signals from the second signals, and outputs the second differential signals from the first output terminal 5-1 and the third output terminal 5-3.
In the second embodiment, the polyphase filter 5 includes, instead of the capacitive elements 15 to 18, the first to fourth inductive elements 25 to 28. In a similar manner to the first embodiment, in the case where a phase of the first signals input from the first input terminal 5a is 0 degrees and a phase of the second signals input from the second input terminal 5b is 180 degrees, the polyphase filter 5 outputs signals similar to those in the first embodiment.
That is, signals having a phase of 0 degrees are output from the first output terminal 5-1 of the polyphase filter 5, and signals having a phase of 90 degrees are output from the second output terminal 5-2 of the polyphase filter 5.
Further, signals having a phase of 180 degrees are output from the third output terminal 5-3 of the polyphase filter 5, and signals having a phase of 270 degrees are output from the fourth output terminal 5-4 of the polyphase filter 5.
Note that output of in-phase signals from the polyphase filter 5 can be suppressed on the basis of a principle similar to that in the first embodiment.
When the high frequency amplifier of
Accordingly, while a direct voltage is applied to the loads 6-1 to 6-4, the first transistor 2-1, the second transistor 2-2, and a current source 3, a direct voltage is not applied to the polyphase filter 5, whereby no voltage drop occurs in the polyphase filter 5.
As a result, the voltage between the emitter and the collector of the first transistor 2-1 and the voltage between the emitter and the collector of the second transistor 2-2 can be maintained higher than those in the first embodiment, whereby the gain of the high frequency amplifier can be increased.
As apparent from the above, while the polyphase filter 5 includes the first to fourth inductive elements 25 to 28 instead of the capacitive elements 15 to 18 in the second embodiment, output of in-phase signals can be suppressed in a similar manner to the first embodiment.
In addition, since the polyphase filter 5 includes the first to fourth inductive elements 25 to 28, the gain of the high frequency amplifier can be made higher than that in the first embodiment.
Although an exemplary case where the polyphase filter 5 includes the first to fourth inductive elements 25 to 28 is described in the second embodiment, the connection form of the first to fourth inductive elements 25 to 28 is not limited to the example illustrated in
The polyphase filter 5 illustrated in
The polyphase filter 5 is configured in such a manner that the first resistor 21, the first inductive element 31, the third resistor 23, the second inductive element 32, the second resistor 22, the third inductive element 33, the fourth resistor 24, and the fourth inductive element 34 are annularly connected in that order.
Specifically, they are connected as follows.
One end of the first inductive element 31 is connected to the first input terminal 5a, and the other end is connected to the second output terminal 5-2.
One end of the second inductive element 32 is connected to the third output terminal 5-3, and the other end is connected to one end of the third resistor 23.
One end of the third inductive element 33 is connected to the second input terminal 5b, and the other end is connected to the fourth output terminal 5-4.
One end of the fourth inductive element 34 is connected to the first output terminal 5-1, and the other end is connected to one end of the fourth resistor 24.
Even when the connection form of the first to fourth inductive elements 31 to 34 in the polyphase filter 5 is the connection form illustrated in
In a third embodiment, an exemplary case where a transistor pair 2 includes, in addition to a first transistor 2-1 and a second transistor 2-2, a third transistor 2-3 and a fourth transistor 2-4 will be described.
In
Each of the third transistor 2-3 and the fourth transistor 2-4 is implemented by, for example, a bipolar transistor, a MOSFET, or the like.
In the third transistor 2-3, a base terminal that is a control terminal is connected to a first signal input terminal 1a, an emitter terminal is connected to a current source 9, and a collector terminal that is an output terminal is connected to a third input terminal 5c of a polyphase filter 5.
The third transistor 2-3 amplifies first signals input from the first signal input terminal 1a, and outputs the amplified first signals to the third input terminal 5c of the polyphase filter 5.
In the fourth transistor 2-4, a base terminal that is a control terminal is connected to a second signal input terminal 1b, an emitter terminal is connected to the current source 9, and a collector terminal that is an output terminal is connected to a fourth input terminal 5d of the polyphase filter 5.
The fourth transistor 2-4 amplifies second signals input from the second signal input terminal 1b, and outputs the amplified second signals to the fourth input terminal 5d of the polyphase filter 5.
The polyphase filter 5 includes, in a similar manner to the first embodiment, a first input terminal 5a connected to the output terminal of the first transistor 2-1, and a second input terminal 5b connected to the output terminal of the second transistor 2-2.
In addition, the polyphase filter 5 includes a third input terminal 5c connected to the output terminal of the third transistor 2-3, and a fourth input terminal 5d connected to the output terminal of the fourth transistor 2-4.
The third input terminal 5c is connected to one end of a third resistor 23, and the other end of a first inductive element 25.
The fourth input terminal 5d is connected to one end of a fourth resistor 24, and the other end of a third inductive element 27.
One end of the current source 9 is connected to the emitter terminal of the third transistor 2-3 and the emitter terminal of the fourth transistor 2-4, and the other end is connected to the ground.
Next, the operation will be described.
When the first signals are input from the first signal input terminal 1a, the first transistor 2-1 amplifies the first signals, and outputs the amplified first signals to the first input terminal 5a of the polyphase filter 5.
When the second signals are input from the second signal input terminal 1b, the second transistor 2-2 amplifies the second signals, and outputs the amplified second signals to the second input terminal 5b of the polyphase filter 5.
When the first signals are input from the first signal input terminal 1a, the third transistor 2-3 amplifies the first signals, and outputs the amplified first signals to the third input terminal 5c of the polyphase filter 5.
When the second signals are input from the second signal input terminal 1b, the fourth transistor 2-4 amplifies the second signals, and outputs the amplified second signals to the fourth input terminal 5d of the polyphase filter 5.
When the first signals amplified by the first transistor 2-1 are input from the first input terminal 5a and the first signals amplified by the third transistor 2-3 are input from the third input terminal 5c, the polyphase filter 5 generates first differential signals from both of the input first signals, and outputs the first differential signals from a first output terminal 5-1 and a third output terminal 5-3.
Further, when the second signals amplified by the second transistor 2-2 are input from the second input terminal 5b and the second signals amplified by the fourth transistor 2-4 are input from the fourth input terminal 5d, the polyphase filter 5 generates second differential signals from both of the input second signals, and outputs the second differential signals from the first output terminal 5-1 and the third output terminal 5-3.
In the third embodiment, in the case where a phase of the first signals input from each of the first input terminal 5a and the third input terminal 5c is 0 degrees and a phase of the second signals input from each of the second input terminal 5b and the fourth input terminal 5d is 180 degrees, the polyphase filter 5 outputs signals similar to those in the first embodiment.
That is, signals having a phase of 0 degrees are output from the first output terminal 5-1 of the polyphase filter 5, and signals having a phase of 90 degrees are output from the second output terminal 5-2 of the polyphase filter 5.
Further, signals having a phase of 180 degrees are output from the third output terminal 5-3 of the polyphase filter 5, and signals having a phase of 270 degrees are output from the fourth output terminal 5-4 of the polyphase filter 5.
However, in the third embodiment, the transistor pair 2 includes the third transistor 2-3 and the fourth transistor 2-4 in addition to the first transistor 2-1 and the second transistor 2-2, thereby enhancing the symmetry of the circuit.
Accordingly, the phase accuracy of the signals output from the first to fourth output terminals 5-1 to 5-4 of the polyphase filter 5 is higher than that of the first embodiment.
That is, compared to the first embodiment, the signals output from the first output terminal 5-1 of the polyphase filter 5 are closer to 0 degrees, and the signals output from the third output terminal 5-3 of the polyphase filter 5 are closer to 180 degrees.
Further, compared to the first embodiment, the signals output from the second output terminal 5-2 of the polyphase filter 5 are closer to 90 degrees, and the signals output from the fourth output terminal 5-4 of the polyphase filter 5 are closer to 270 degrees.
Note that output of in-phase signals from the polyphase filter 5 can be suppressed on the basis of a principle similar to that in the first embodiment.
When the high frequency amplifier of
Accordingly, while a direct voltage is applied to the loads 6-1 to 6-4, the first transistor 2-1, the second transistor 2-2, the third transistor 2-3, the fourth transistor 2-4, and the current sources 3 and 9, a direct voltage is not applied to the polyphase filter 5, whereby no voltage drop occurs in the polyphase filter 5.
As a result, the voltage between the emitter and the collector of the first to fourth transistors 2-1 to 2-4 can be maintained higher than that in the first embodiment, whereby the gain of the high frequency amplifier can be increased.
As apparent from the above, according to the third embodiment, the transistor pair 2 includes the third transistor 2-3 and the fourth transistor 2-4 in addition to the first transistor 2-1 and the second transistor 2-2, whereby the effects similar to those in the first embodiment can be obtained, and the symmetry of the circuit is enhanced so that the phase accuracy of the signals output from the first to fourth output terminals 5-1 to 5-4 of the polyphase filter 5 can be enhanced.
Although an exemplary case where the polyphase filter 5 includes the first to fourth inductive elements 25 to 28 is described in the third embodiment, the connection form of the first to fourth inductive elements 25 to 28 is not limited to the example illustrated in
Although an exemplary case where the polyphase filter 5 includes the first to fourth inductive elements 25 to 28 is described in the third embodiment, the first inductive element 25 may have inductive reactance that cancels out parasitic capacitance 2-3a of the third transistor 2-3, and the second inductive element 26 may have inductive reactance that cancels out parasitic capacitance 2-2a of the second transistor 2-2.
Further, the third inductive element 27 may have inductive reactance that cancels out parasitic capacitance 2-4a of the fourth transistor 2-4, and the fourth inductive element 28 may have inductive reactance that cancels out parasitic capacitance 2-1a of the first transistor 2-1.
Accordingly, it is possible to cancel out the parasitic capacitance 2-1a to 2-4a, which adversely affects the amplification operation, when the high frequency amplifier amplifies high frequency signals.
In a fourth embodiment, an exemplary case where a first series circuit 41 is connected to a base terminal that is a control terminal of a third transistor 2-3 included in a transistor pair 2, and a second series circuit 44 is connected to a base terminal that is a control terminal of a fourth transistor 2-4 will be described.
In
The first series circuit 41 is a circuit in which a capacitive element 42 and a resistor 43 are connected in series, and one end thereof is connected to the base terminal of the third transistor 2-3, and the other end is connected to the ground.
The second series circuit 44 is a circuit in which a capacitive element 45 and a resistor 46 are connected in series, and one end thereof is connected to the base terminal of the fourth transistor 2-4, and the other end is connected to the ground.
Next, the operation will be described.
Unlike the third embodiment, in the fourth embodiment, the base terminal of the third transistor 2-3 is input-terminated by the first series circuit 41, and the base terminal of the fourth transistor 2-4 is input-terminated by the second series circuit 44.
Accordingly, while the third transistor 2-3 does not amplify first signals and the fourth transistor 2-4 does not amplify second signals, input impedance at a third input terminal 5c of a polyphase filter 5 is matched with input impedance at a first input terminal 5a. Further, input impedance at a fourth input terminal 5d of the polyphase filter 5 is matched with input impedance at a second input terminal 5b.
This enhances the symmetry of the circuit compared to, for example, the high frequency amplifier of
The operation of the polyphase filter 5 according to the fourth embodiment is similar to, for example, the operation of the polyphase filter 5 illustrated in
Although an exemplary case where first to fourth inductive elements 25 to 28 in the polyphase filter 5 are connected as illustrated in
Although an exemplary case where the polyphase filter 5 includes the first to fourth inductive elements 25 to 28 is described in the fourth embodiment, the first inductive element 25 may have inductive reactance that cancels out parasitic capacitance 2-3a of the third transistor 2-3, and the second inductive element 26 may have inductive reactance that cancels out parasitic capacitance 2-2a of the second transistor 2-2.
Further, the third inductive element 27 may have inductive reactance that cancels out parasitic capacitance 2-4a of the fourth transistor 2-4, and the fourth inductive element 28 may have inductive reactance that cancels out parasitic capacitance 2-1a of the first transistor 2-1.
Accordingly, it is possible to cancel out the parasitic capacitance 2-1a to 2-4a, which adversely affects the amplification operation, when the high frequency amplifier amplifies high frequency signals.
In a fifth embodiment, an exemplary case where each of matching circuits for matching impedance is connected between first to fourth transistors 2-1 to 2-4 and a polyphase filter 5 will be described.
In
A capacitive element 51 has one end connected between a first input terminal 5a of the polyphase filter 5 and the ground, which is a first matching circuit for matching impedance between the first input terminal 5a of the polyphase filter 5 and the output terminal of the first transistor 2-1.
A capacitive element 52 has one end connected between a second input terminal 5b of the polyphase filter 5 and the ground, which is a second matching circuit for matching impedance between the second input terminal 5b of the polyphase filter 5 and the output terminal of the second transistor 2-2.
A capacitive element 53 has one end connected between a third input terminal 5c of the polyphase filter 5 and the ground, which is a third matching circuit for matching impedance between the third input terminal 5c of the polyphase filter 5 and the output terminal of the third transistor 2-3.
A capacitive element 54 has one end connected between a fourth input terminal 5d of the polyphase filter 5 and the ground, which is a fourth matching circuit for matching impedance between the fourth input terminal 5d of the polyphase filter 5 and the output terminal of the fourth transistor 2-4.
In the fifth embodiment, the high frequency amplifier includes the capacitive elements 51 to 54 that are the first to fourth matching circuits, thereby matching the impedance between the first to fourth transistors 2-1 to 2-4 and the polyphase filter 5.
Accordingly, the first signals output from the output terminal of the first transistor 2-1 are hardly reflected at the first input terminal 5a of the polyphase filter 5.
In addition, the second signals output from the output terminal of the second transistor 2-2 are hardly reflected at the second input terminal 5b of the polyphase filter 5.
Accordingly, the loss of the first signals and the second signals can be reduced, whereby the gain of the high frequency amplifier can be made higher than the first embodiment.
Although an exemplary case where first to fourth inductive elements 25 to 28 in the polyphase filter 5 are connected as illustrated in
In the first embodiment described above, an exemplary case where the load group 6 includes the loads 6-1 to 6-4 is described.
In a sixth embodiment, an exemplary case where a plurality of loads included in a load group 6 is inductive elements 6-5 to 6-8 will be described.
In
The load group 6 includes the inductive elements 6-5 to 6-8.
One end of the inductive element 6-5 is connected to a first output terminal 5-1 of the polyphase filter 5, and the other end is connected to a power supply 7.
One end of the inductive element 6-6 is connected to a second output terminal 5-2 of the polyphase filter 5, and the other end is connected to the power supply 7.
One end of the inductive element 6-7 is connected to a third output terminal 5-3 of the polyphase filter 5, and the other end is connected to the power supply 7.
One end of the inductive element 6-8 is connected to a fourth output terminal 5-4 of the polyphase filter 5, and the other end is connected to the power supply 7.
When the high frequency amplifier of
Note that the plurality of loads included in the load group 6 is the inductive elements 6-5 to 6-8.
Accordingly, while a direct voltage is applied to the first transistor 2-1, the second transistor 2-2, and a current source 3, a direct voltage is not applied to the polyphase filter 5 and the load group 6, whereby no voltage drop occurs in the polyphase filter 5 and the load group 6.
As a result, the voltage between the emitter and the collector of the first and second transistors 2-1 and 2-2 can be maintained higher than that in the first embodiment, whereby the gain of the high frequency amplifier can be increased.
Although an exemplary case where the first to fourth inductive elements 25 to 28 in the polyphase filter 5 are connected as illustrated in
In a seventh embodiment, an exemplary case where a plurality of loads included in a load group 6 is inductive elements 61-1 to 61-4 and the inductive elements 61-1 to 61-4 also serve as inductive elements included in a polyphase filter 5 will be described.
In
The inductive element 61-1 serves as the inductive element 6-5 illustrated in
In the inductive element 61-1, a terminal (1) is connected to a third input terminal 5c of a polyphase filter 5, a terminal (2) is connected to a first output terminal 5-1 of the polyphase filter 5, and a terminal (3) is connected to a power supply 7.
The inductive element 61-2 serves as the inductive element 6-6 illustrated in
In the inductive element 61-2, a terminal (1) is connected to a second input terminal 5b of the polyphase filter 5, a terminal (2) is connected to a second output terminal 5-2 of the polyphase filter 5, and a terminal (3) is connected to the power supply 7.
The inductive element 61-3 serves as the inductive element 6-7 illustrated in
In the inductive element 61-3, a terminal (1) is connected to a fourth input terminal 5d of the polyphase filter 5, a terminal (2) is connected to a third output terminal 5-3 of the polyphase filter 5, and a terminal (3) is connected to the power supply 7.
The inductive element 61-4 serves as the inductive element 6-8 illustrated in
In the inductive element 61-4, a terminal (1) is connected to a first input terminal 5a of the polyphase filter 5, a terminal (2) is connected to a fourth output terminal 5-4 of the polyphase filter 5, and a terminal (3) is connected to the power supply 7.
While operation of the high frequency amplifier according to the seventh embodiment is similar to the operation of the high frequency amplifier according to the sixth embodiment, the inductive elements 61-1 to 61-4 included in the load group 6 also serve as the inductive elements included in the polyphase filter 5, whereby the number of parts can be reduced compared to the sixth embodiment.
Note that, in the present invention, the respective embodiments can be freely combined, any constituent element of each embodiment can be modified, and any constituent element of each embodiment can be omitted within the scope of the invention.
The present invention is suitable for a high frequency amplifier that amplifies first and second signals that are differential signals.
1: Differential input terminal, 1a: First signal input terminal, 1b: Second signal input terminal, 2: Transistor pair, 2-1: First transistor, 2-2: Second transistor, 2-3: Third transistor, 2-4: Fourth transistor, 2-1a, 2-2a, 2-3a, 2-4a: Parasitic capacitance, 3, 9: Current source, 4: Transistor load, 5: Polyphase filter, 5a: First input terminal, 5b: Second input terminal, 5c: Third input terminal, 5d: Fourth input terminal, 5-1: First output terminal, 5-2: Second output terminal, 5-3: Third output terminal, 5-4: Fourth output terminal, 6: Load group, 6a, 6b, 6-1 to 6-4: Load, 6-5 to 6-8: Inductive element, 7: Power supply, 8: Differential output terminal, 8a, 8b, 8-1 to 8-4: Amplifier output terminal, 11 to 14: Resistor, 15 to 18: Capacitive element, 21: First resistor, 22: Second resistor, 23: Third resistor, 24: Fourth resistor, 25: First inductive element, 26: Second inductive element, 27: Third inductive element, 28: Fourth inductive element, 31: First inductive element, 32: Second inductive element, 33: Third inductive element, 34: Fourth inductive element, 41: First series circuit, 42: Capacitive element, 43: Resistor, 44: Second series circuit, 45: Capacitive element, 46: Resistor, 51: Capacitive element (First matching circuit), 52: Capacitive element (Second matching circuit), 53: Capacitive element (Third matching circuit), 54: Capacitive element (Fourth matching circuit), 61-1 to 61-4: Inductive element.
Filing Document | Filing Date | Country | Kind |
---|---|---|---|
PCT/JP2017/022359 | 6/16/2017 | WO | 00 |