Patent Application
20070257735
The present invention relates to a frequency divider; more particuiarly, relates to, without changing a circuit structure, ad justing an oscillation frequency to obtain a compensation to a power sensitivity of an input, to reduce a power consumption of the input and to increase a frequency range for division.
A general injection locked frequency divider has a structure of an oscillator, an LC structure or a ring structure, where signals are injected from an in injection terminal. When an injected signal has a phase synchronization to an inner oscillation signal, a division is done. The operative frequency of the circuit is decided by an oscillator, where the power required is low enough to be used in circuits with low power. Such a circuit is characterized in a big division ratio, a small locked frequency and a small phase noise.
Generally speaking, the injection locked frequency divider has a smaller locked frequency than that of a static frequency divider so that an operation under a frequency deviated from the oscillation frequency requires an increased input signal power level to get a correct state of a division. Yet, regarding the operation under the deviated frequency, because the inner oscillating signal is no more synchronization with the input signal, a division is impossible even through the power level of the input signal is increased. Therefore, the injection locked frequency divider is only suitable for narrow-band communication systems with low transferring rates.
A prior art is proclaimed in Taiwan, called “A frequency divider circuit”, where a multi-phase signal according to an input signal is outputted and the outputted signal has a frequency obtained by equally dividing a period (integer) of the frequency of the in put signal. The prior art comprises an N-stage ringed-amplifier circuit and a current-deviation modulator circuit, where the current-deviation modulator circuit produces an alternating current having the same frequency as that of the input signal. Then the alternating current is injected into the ringed-amplifier circuit to obtain a fixed oscillation frequency. After the ringed-amplifier circuit obtains a state of a steady oscillation, an output terminal of the ringed-amplifier circuit outputs a signal equally dividing the period and the frequency is a 1/N part of the reference frequency.
Another prior art is revealed in Taiwan, named “A frequency divider”, comprising a divider to produce a first clock and a second clock according to an input clock; a switching device to out putting an output clock of the first clock upon an input switching signal of a first state, or of the second clock upon an output switching signal of a second state; and a switching control device to produce the input or output switching signal for the first state or the second state and to output the input or output switching signal to the switching device according to the frequency of the output clock from the switching device.
Although the prior arts have the frequency-division function, the ranges for frequency division are narrow. For a wider range for frequency division, a bigger input power or a change in circuit structure is required. Hence, the prior arts do not fulfill users' requests on actual use.
The main purpose of the present invention is to ad just an oscillation frequency by in putting a DC control voltage without changing the circuit structure to maintain a lowest power strength of an in put signal, to reduce a power consumption of the input signal and to increase the frequency range for dividing the input signal.
To achieve the above purpose, the present invention is a high frequency divider with input-sensitivity compensation, comprising an input terminal, an injection transistor, a first inductance, a second inductance, a first transistor, a second transistor, a third transistor, a fourth transistor, a first output buffer, a second output buffer, a first output terminal, a second output terminal, and a voltage control terminal, where the above components are connected electrically to form a cross-coupled LC structure; a DC control voltage is inputted from the voltage control terminal to change capacities of the third transistor and the fourth transistor to adjust an oscillation frequency. Or, the frequency divider can be comprised of a plurality of inverters, an input terminal, an injection transistor, an output buffer, an output terminal and a voltage control terminal, where the above components are connected electrically to form a ring structure; the inverter comprises a fifth transistor, a sixth transistor and a seventh transistor connected electrically; a DC control voltage is inputted from the voltage control terminal to change an RC time of each inverter to adjust an oscillation frequency. Accordingly, a novel high frequency divider with input-sensitivity compensation is obtained.
The present invention will be better understood from the following detailed descriptions of the preferred embodiments according to the present invention, taken in conjunction with the accompanying drawings, in which
The following descriptions of the preferred embodiments are provided to understand the features and the structures of the present invention.
Please refer to
Each transistor 141, 142, 151, 152 in the components is a metal oxide semiconductor (MOS) transistor, a high electron mobility transistor (HEMT), a bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT). The third transistor 151 and the fourth transistor 152 are va varactors or diodes. The first inductance 131 and the second inductance 132 are spiral or curved (meander type). And the first output buffer 161 and the second output buffer 162 both have a structure of an emitter-coupled logic (ECL), a common mode logic (CML), a positive-ECL (PECL) or a low voltage differential signaling (LVDS) circuit.
The frequency divider 1 according to the present invention is an injection locked frequency divider with a cross-coupled LC structure. The frequency divider 1 can be an oscillator. A direct-current (DC) control voltage is inputted from the voltage control terminal 18 into the third transistor 151 and the fourth transistor 152 to change capacities of the third transistor 151 and the fourth transistor 152. A first transistor 141 and a second transistor 142 are used coordinately with negative impedances to eliminate positive resistances of the first inductance 131 and the second inductance 132. Thus, an oscillation frequency is obtained from the frequency divider 1. By doing so, before inputting any signal, the frequency divider 1 obtains an oscillation frequency through inputting a DC control voltage for an adjustment in advance. Then, the oscillation frequency can be adjusted under different levels by controlling the DC control voltage.
In the other hand, an input signal for frequency division is inputted from the input terminal 11, whose frequency is an even times to the oscillation frequency of the frequency divider 1. After the division, the frequency-divided input signal is amplified by the first output buffer 161 and the second output buffer 162 to be outputted from the first output terminal 171 and the second output terminal 172, where the outputted divisor of the frequency divider 1 is an even number.
But, if the frequency of the input signal is deviated from the oscillation frequency and therefore is not divided, a DC control voltage is in inputted from the voltage control terminal 18 to change the capacities of the third transistor 151 and the fourth transistor 152 to further adjust the oscillation frequency into a reciprocal of an even times of the frequency of the input signal.
Please refer to
The plurality of inverters 19 has an odd number of inverters; and each inverter 19 comprises a fifth transistor 191, a sixth transistor 192 and a seventh transistor 193 connected electrically, where the fifth transistor 191 and the sixth transistor 192 are inverters to obtain RC time; and the seventh transistor 193 is a delay-time adjusting transistor. By inputting a DC control voltage to each inverter 19 from each voltage control terminal 18a to change the RC time, the oscillation frequency is changed into a reciprocal of an even times of frequency of an input signal so that a compensation to an input power sensitivity is obtained.
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To sum up, the present invention is a high frequency divider with input-sensitivity compensation, where, without changing the circuit, a DC control voltage is controlled to adjust an oscillation frequency so that a power sensitivity of the input signals is lowered, the consumption of input power is reduced and the frequency range for division is increased.
The preferred embodiments herein disclosed are not intended to unnecessarily limit the scope of the invention. Therefore, simple modifications or variations belonging to the equivalent of the scope of the claims and the instructions disclosed herein for a patent are all within the scope of the present invention.
