Patent Application
20180175513
Performance of an array antenna is often limited by the size and bandwidth limitations of the antenna elements which make up the array. Improving the bandwidth while maintaining a low profile enables array system performance to meet bandwidth and scan requirements of next generation of communication applications, such as software defined or cognitive radio. These applications also frequently require antenna elements that can support either dual linear or circular polarizations.
In one aspect, a unit cell of a phased array antenna includes a metal plate having a hole, a first side and a second side opposite the first side, a first plurality of laminate layers disposed on the first side, a second plurality of layers disposed on the second side of the metal plate, a radiator disposed in the first plurality of layer on the first side, a feed circuit disposed in the second plurality of laminate layers on the second side and configured to provide excitation signals to the radiator and a first plurality of vias extending through the hole connecting the feed circuit to the radiator.
In another aspect, a method of manufacturing a unit cell of a phased array antenna includes machining a metal plate to have at least one hole, filling the at least one hole with a laminate, adding a first plurality of laminate layers to a first surface of the metal plate, adding a second plurality of laminate layer to a second surface of the metal plate opposite the first surface, adding a radiator in the first plurality of layer on the first side; adding a feed circuit in the second plurality of laminate layers on the second side and configured to provide excitation signals to the radiator and adding a plurality of vias extending through the hole connecting the feed circuit to the radiator.
Described herein is a phased array antenna that includes one or more unit cells. In one example, the unit cell includes a high frequency radiator fabricated in a polymer-on-metal (POM) structure.
The unit cell described herein provides one or more of the following advantages. The unit cell provides out-of-band filtering and shielding inherently. The unit cell is well grounded, low profile structure that controls surface wave propagation extended frequency and scan performance. The unit cell provides excellent axial ratio performance over scan out to 60°. High density thin film metallization on a laminate achieves 0.002″ linewidths and gaps. The unit cell has thermal management benefits due to a metal plate.
Current loop radiators have been successfully realized in printed wiring board (PWB) technology from frequencies ranging from C-band to K-band. At Ka-band and above it becomes difficult to maintain performance due to the sensitivity of the radiator performance to via location and the need for smaller gaps and linewidths. In PWB technology, via location from nominal can vary within a 0.01″ diameter circle centered on nominal, meaning that vias can move as much as 0.005″ in any direction. As frequency increases, the wavelength and unit cell decrease, so this movement becomes more significant. Additionally, PWB technology has difficulty realizing linewidths and gaps below 0.004″ due to limitations of the processing and equipment. The approach described herein enable producible current loop elements for high frequencies.
Polymer on Metal (POM) technology offers the needed improvement. High density thin film metallization on a liquid crystalline polymer (LCP) attached to a metal plane can achieve 0.002″ linewidths and gaps. Misregistration of these metallization layers is greatly reduced compared to PWB technology, which helps reduce maximum via movement from 0.005″ to <0.001″. Additionally, vias are made with precision laser micro-machining, not drill bits. This combination of improvements provides the ability to realize current loops at much higher frequencies than was possible before. POM technology offers additional advantages in thermal management and shielding. Because the radiator circuit is constructed around a metal plate of significant thickness (e.g., 0.02″), it possesses waveguide-like frequency rejection properties for out-of-band frequencies. Construction can be simplified by placing the feed circuitry on one side of the metal plate and the radiating structure on the other. This simplifies fabrication of the POM circuitry and reduces fabrication cost by reducing the number of laminations required.
Referring to
Referring to
In one example, the WAIM sheet is a 0.01″ Cyanide Ester resin/quartz pixelated WAIM. In one example, the first laminate region 104 and the second laminate region 108 are liquid crystalline polymer (LCP) laminates. The first laminate region 104 may include one or more layers of laminate. The second laminate region 108 may include one or more layers of laminate. As will be further described herein, metallization (including vias 122a-122d) may be added after a laminate layer is added. For example, the vias 122a-122d are formed in stages.
Referring to
Each of the dipole arms 132a-132d is grounded to the metal plate 106 by a corresponding via. For example, the dipole arm 132a is grounded using a via 124a, the dipole arm 132b is grounded using a via 124b, the dipole arm 132c is grounded using a via 124c and the dipole arm 132d is grounded using a via 124d. In one example, one or more of the vias 132a-132d are added at a particular distance from a respective via 124a-124d to control tuning.
In one example, the vias (e.g., vias 122a-122d and vias 124a-124d) are micromachined laser vias that allow high accuracy placement of the vias that reduce performance variations in the built part. It is important to the successful design of the radiator that the layers of the stackup are implemented in such a way that the vias needed can be realized as required for radiator performance, particularly, balancing such elements as the diameter of the hole 202 in the metal plate 106 to be large enough that the four signal vias 122a-122d between the feed circuit 120 and the radiator 116 can be realized and small enough that the ground vias 124a-124d between the radiator circuit layer 116 and the metal plate 106 can be placed close enough to the signal vias 122a-122d to be effective at eliminating the propagation of surface waves in the dielectrics (e.g., laminates).
Referring to
The pads 320a-320d are connected to a corresponding one of the radiator dipole arms 132a-132d using the vias 122a-122d (
Referring to
The resistors 412a-412c provide isolation between the first rat-race coupler 402a, the second-rat-race coupler 402b and the branchline coupler 406, which improves scan performance. The branch coupler 406 is connected to the RF connector 124 at the pad 450.
The pads 420a-420d are connected to a corresponding one of the radiator dipole arms 132a-132d using the vias 122a-122d (
Referring to
Process 500 fills one or more of the holes (506). For example, the hole 202 of the metal plate 106 is filled with an LCP.
Process 500 adds a first laminate layer to a top surface of the metal plate (510). For example, a first laminate layer of LCP is added to the top surface of the metal layer 106. In one particular example, 0.004′ of LCP is added.
Process 500 adds a second laminate layer to a bottom surface of the metal plate (514). For example, a second laminate layer of LCP is added to the bottom surface of the metal layer 106. In one particular example, 0.002′ of LCP is added.
Process 500 adds laser vias to the first and second laminate layers (518). In one particular example, the first and second layers are patterned for the laser vias. For example, 0.01″ laser vias are added to the first and second laminate layers. In another example, 0.006″ laser vias are added to the first laminate layer 104 and 0.003″ laser vias are added to the second laminate layer 108. In one example, the staggered 0.003″ laser vias are or grounding where the larger via size would be unable to fit.
Process 500 adds resistors to the second laminate layer (522). For example, resistors (e.g., 25 Ohms per square material (OPS)) are added to the second laminate layer 108. In one example, the resistors include the resistors 312a, 312b in the feed circuit 120.
Process 500 add additional laminate to the first and second laminate layers (526). For example, 0.002″ of LCP is added to the second laminate layer 108 and 0.008″ of LCP is added to the first laminate layer 104.
Process 500 adds laser vias to the additional laminate layers (532). In one particular example, the first and second layers 104, 108 are patterned for the laser vias. In another example, 0.003″ and 0.006″ laser vias are added to the second laminate layer 108 and 0.008″ laser vias are added to the first laminate layer 104. In one example, with the formation of the 0.008″ laser vias that are stacked on top of the 0.008″ vias added (see, for example, processing block 518), the signal vias 122a-122d are completed.
Process 500 adds the feed circuit (536). For example, the feed circuit 120 is formed, using metallization, to connect to the signal vias 122a-122d.
Process 500 adds the radiator (542). For example, the radiator 116 is formed, using metallization, to connect to the ground vias 124a-124d and the signal vias 122a-122d
Process 500 add WAIM layer (546). For example, the WAIM layer 102 is added and place above the first laminate region 104 leaving an air gap of 0.02″ between the first laminate region 104 and the WAIM layer 102.
The processes described herein are not limited to the specific examples described. For example, the process 500 is not limited to the specific processing order of
Elements of different embodiments described herein may be combined to form other embodiments not specifically set forth above. Various elements, which are described in the context of a single embodiment, may also be provided separately or in any suitable subcombination. Other embodiments not specifically described herein are also within the scope of the following claims.
This invention was made with U.S Government support. The Government has certain rights in the invention.
