Patent Application
20100262887
The present invention relates generally to data transmission systems and more particularly to a system and process for the recovery of data in networks disposed to transmission errors.
State of the art wired (e.g. fiber optic and copper) networking equipment offers bit error rates (BERs) on the order of 1 in 1012 bits. As the data transmission rates start to approach these BERs, the frequency of errors becomes problematic, particularly for the larger systems. For example, a typical sensor data network contained in a digital radar system may be operating at 4×109 to 10×109 bits per second, with dozens of these networks contained in the radar system. This means that, on average, somewhere in the system data is being corrupted by a communications error every 1 to 2 minutes or less. Given that these radars are real-time sensors operating at very high data rates it is not practical to employ traditional retransmission techniques to recover the erroneous data.
Typical methods for solving the aforementioned problem include: (a) buffering the data and using software protocols for error detection and retransmit requests; (b) forward error correction data with the data; (c) using fully redundant networks (though generally employed for full failover); (d) accepting the error. Data buffering requires significant memory buffering and processing overhead, as well as additional weight, power, space, and cost to the system due to added components. In the event of an error, retransmission of data interrupts the normal data flow, and in the event of excessive errors can prevent the data from getting through at all. Forward error correction data schemes require complex computations both at the sending end and at the receiving end if an error occurs. Fully redundant networking schemes have obvious cost, weight, power, and size implications because at least two networks are required. Error acceptance without correction is often intolerable to effective systems operation. An alternative solution that requires simpler computations, is reasonable in cost, weight, power, and size implications, and provides error correction as required for a particular application is highly desired.
The present invention comprises a system for transmitting data comprising: a plurality of parallel transmission channels receiving interleaved data words of a block of data for transmission over a network. Each channel includes an associated check sum data generator to compute check sum associated with that channel's data words. A logic circuit computes parity data based on the interleaved data words from the respective channels to generate a parity data stream on a separate parity channel. A checksum generator associated with the parity channel is responsive to the parity data stream for providing parity check sum. An encoder arrangement encodes each of the transmission channel data words and checksum and parity data words and parity checksum for serial transmission over a physical network.
A receiver arrangement is responsive to the transmission from the physical network for receiving and decoding the transmitted data. A corresponding plurality of parallel receiver channels receives the decoded information and performs a corresponding checksum (e.g. a CRC check) on the received, decoded, transmitted data words to compute a checksum. The computed checksum associated with each channel is compared to the received, decoded checksum associated with that channel. Based on the comparison, a logic circuit determines that if an error exists in only one of the data channels, and not in the parity channel, the logic circuit causes a recovery circuit to reconstruct the information data words in the channel in error according to the information data words received from the remaining data channels and the received parity data.
A system for transmitting information data packets over a network includes a plurality of parallel transmission channels, each receiving interleaved data words constituting the data packets. Each channel includes a corresponding check sum data generator to compute check sum data for a corresponding sequence of data words. A logic circuit responsive to the interleaved data words from each channel performs an arithmetic operation on the data words from those channels to generate a parity data stream onto a separate channel. A check sum data generator computes checksum data based on the parity data stream. An encoder device downstream from each checksum data generator encodes the data and checksum from each channel for serial transmission over a network.
Another aspect of the invention comprises a system for receiving data comprising: a plurality of reception channels having associated check sum data checkers to compute check sum data associated with received data; and at least one channel for receiving parity and an associated check sum; and a comparator to compare the computed check sum of the check sum checker with the received associated check sum.
The present invention also comprises a system for correcting errors in information data transmitted over multiple transmission channels, comprising: a plurality of transmission channels conveying interleaved information data constituting a data block, each of the channels having a corresponding check sum device to compute a check sum associated with the information data conveyed via the channels; a processor for computing parity data based on the interleaved information data; a channel for transmitting the parity data and check sum data associated with the parity data. The system includes a transmitter arrangement which transfers the channel information data and channel checksum for each of the plurality of transmission channels, and the channel parity data and parity checksum for the parity channel, over a network. In addition, the system includes a corresponding plurality of reception channels having associated checksum devices to compute check sums associated with the transmitted information data. A corresponding channel is adapted to receive the transmitted parity data and associated parity check sum, the corresponding channel having an associated checksum device to compute a checksum associated with the transmitted parity data; and a logic circuit that compares the computed check sum of the transmitted information and parity data with reference data, wherein if an error is determined in only one of the data channels based on the comparison, and not in the parity channel, the logic circuit causes a recovery circuit to reconstruct the information data in the channel in error according to the information data received from the remaining data channels and the received parity data.
Understanding of the present invention will be facilitated by consideration of the following detailed description of the preferred embodiments of the present invention taken in conjunction with the accompanying drawings wherein:
It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding, while eliminating, for the purpose of clarity, many other elements found in typical communications systems and methods of making and using the same. Those of ordinary skill in the art may recognize that other elements and/or steps may be desirable in implementing the present invention. However, because such elements and steps are well known by those of ordinary skill in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein. Furthermore, while the present invention is described in relation to a radar system, it is understood that the invention is applicable to other complex systems wherein error correction of transmitted and/or received information data is required.
The data words output from CRC generator 115 in
The data is received from network 130 by corresponding transceivers labeled generally as 135 and corresponding SERDES labeled generally as 140 at the receiving end. Each receiving SERDES 140 recovers a data clock to decode the data back to 16 bit parallel values and pass the data to a channel resynchronization module 145. The channel resynchronization module includes logic functions to reformat and/or realign the data into the original 16-bit parallel values.
Following reconstruction from disparate bytes into the original form, a CRC checker 150 receives the ordered data and calculates a CRC on the received data. The CRC is compared to the expected value to determine if the data's integrity is intact (i.e., no errors are detected). If the CRC is correct then the CRC value appended at transmit is stripped from the data stream and the data is stored in the receiving system's memory 160. The data is subsequently transferred via DMA engine 165 to service various applications. If the CRC is incorrect (i.e. an error is detected) then entire received data stream or packet is discarded and an error signal is sent to the error logic processing module 155 to register the error. Typically an error message is sent to the receiving system processor using means well known by those of ordinary skill in the art of data storage and transmission.
Referring now to
In the illustrated embodiment, data packets comprising data blocks in the form of data words configured according to a given application, for example, are operated on by DMA engine 210. DMA engine 210 transfers data blocks as 16-bit words via system memory 205 to three parallel channels 222a, 222b, and 222c in an interleaved or round robin fashion. As data is transferred from the DMA engine 210 and system memory 205 into each of the three channels 222a, 222b, and 222c, a parity logic module 215 operates on the data words input into the first N channels (e.g. 222a, 222b, 222c in the non-limiting example of the invention illustrated) via exclusive-or operations to provide a parity data stream onto transmission channel 222d. In the non-limiting example of the invention illustrated, the logical operation for the “exclusive-or” results in a value of “true” if and only if exactly one of the operands p, q has a value of “true”. As indicated the Nth+1 channel is reserved for the parity data 206. The parity channel 222d data is computed via a simple and inexpensive exclusive-or operation. The exclusive-or operation may be implemented using a FPGA, for example. Other implementations are contemplated including ASICs as well as other electronic circuit configurations.
Still referring to
The data words and appended checksum data output from each CRC generator are input into the respective SERDES module 225a, 225b, 225c, and 225d as bytes having length n. In the example illustrated in
The encoded data associated with each channel 222a, 222b, 222c, and 222d is received from network 235 by corresponding respective transceivers 240e, 240f, 240g, and 240h arranged in parallel and applied to corresponding decoders (e.g. SERDES) 245e, 245f, 245g, and 245h at the receiving end. Each SERDES labeled generally as 245 recovers a data clock to decode its data and reconstruct the data back to a 16-bit parallel data format.
A corresponding checksum (e.g. a cyclic redundancy check (CRC)) module labeled generally as 250 receives the output of the SERDES and computes a check sum to determine if any data received via the corresponding channel (e.g., 242e, 242f, 242g, or 242h) contains an error. The output of each CRC module (i.e. 250e, 250f, 250g, 250h) is input to error detection and correction control logic module 255. In one non-limiting embodiment, module 255 receives each of the N checksum inputs (N=4) and determines if all the check sums from channels, 242e, f, g, h indicate that the data for each channel is received and is intact, i.e., no errors detected (e.g. all inputs=0), then the data from the received channels, 242e, 242f, 242g is passed on to system memory 275 (via modules 265, 270, for example) for further application processing with no requirement for correction. If one and only one of the check sums from channels, 242e, 242f, 242g, 242h indicate that the data is not intact, (i.e., an error is detected via error detection and correction control 255) on one of the received channels, e, f, g, h, (e.g. one single input=1) then the erroneous channel data can be recovered by using the data from the remaining three error free channels via the channel selection and error recovery logic module 265. In one non-limiting embodiment of the invention an exclusive-or computation of the remaining three error-free channels (including for example the parity data channel) may be employed to recover the channel data having disclosed an error. A channel resynchronization 270 function reformats the data blocks to ensure the data is in the order required by system memory 275 and DMA engine 260. Upon reformatting, the data is then applied to memory 275 and DMA engine 260. If the determined error(s) emanated from only the parity channel (e.g., channel h), then no error recovery is required. If more than one check sum detects an error (i.e. errors are determined to exist in multiple channels) then the entire data packet from all channels is discarded.
Thus, as illustrated in
The system 200 further comprises a receiver arrangement for receiving data including a plurality of reception channels 242e, 242f, 242g and 242h having associated decoders for decoding the received channel data from each of the channels; and respective check sum data check logic modules 250 to compute check sum data associated with received decoded data. Error detection and correction control module 255 receives the output checksum data from each corresponding CRC module 250e, 250f, 250g, and 250h and compares the computed check sum data with reference data (e.g. the received and decoded checksum data). Based on the comparison, if it is determined that only one data channel has a detected error, then module 255 causes channel selection and error recovery logic module 265 to read the buffers from the error free channels and perform an XOR operation on the data to regenerate the data words from the detected error channel. Upon completion, all of the channel data is re-aligned (e.g. temporal re-alignment of the data for the transmitted/received data packet) to ensure the data words constituting the packet(s) are in the correct order via channel resynchronization module 270 and provided to system memory 275 for further processing by DMA engine 260.
Referring now to
Thus, embodiments of the present invention illustrate that by placing information data (e.g. interleaving data words) on three transmission channels and placing parity data words on a fourth transmission channel, then errors occurring on any single channel can be recovered. This technique can extend all the way to having a channel fail completely, though further errors will not be recovered. The parity data words transmitted on the parity channel may be computed via a very simple and inexpensive “exclusive or” operation. Furthermore, the system and method of the present invention operates without the complexities associated with conventional data buffering software protocols for error detection and retransmission requests, forward error correction data with the data; use of fully redundant networks, simply acceptance of error conditions.
While the present invention has been described with reference to the illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art on reference to this description. For example, while one possible implementation uses four lanes or channels such as an LX4 or CX4 implementation of a 10-gigabit Ethernet, applications other than Ethernet implementations are also contemplated. Further, while the present invention lends itself to digital radar applications and radar digital data transmission and processing, other applications for the present error transmission and recovery system are also contemplated. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.
