Patent Application
20100259331
The present invention generally relates to low-noise amplifiers (LNAs), and in particular to a high-linearity low noise amplifier.
For operation in a hostile multi-radio environment, a high-performance receiver may need to have a highly-linear and highly-sensitive front end. Highly sensitive LNAs with high-output compression points are difficult to implement in low-voltage scaled CMOS technology due to the larger output swings that are required for high-performance receivers. The use of highly-linear and highly-sensitive front ends, however, generally adds considerable cost to the high-performance receiver.
The following description and the drawings sufficiently illustrate specific embodiments of the invention to enable those skilled in the art to practice them. Other embodiments may incorporate structural, logical, electrical, process, and other changes. Examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for those of other embodiments. Embodiments of the invention set forth in the claims encompass all available equivalents of those claims. Embodiments of the invention may be referred to herein, individually or collectively, by the term “invention” merely for convenience and without intending to limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed.
In some embodiments, cascode amplifier 102 comprises common-source transistor (M1) 112 coupled with common-gate transistor (M2) 114. Cascode amplifier 102 also includes integrated filters to attenuate undesired signals. As shown, cascode amplifier 102 includes two resonant traps to attenuate blockers. The first resonant trap is at the output of common-source transistor 112 and is formed by capacitor 116 (Cro) in parallel with inductor 118 (Lt), which are in series with capacitor 120 (Ct). In some embodiments, this first resonant trap is coupled with the output of common-gate transistor 114. In some embodiments, an additional resonant trap (not shown) is coupled with the output of common-gate transistor 114. The second resonant trap is at the source of common-source transistor 112 and is formed by capacitor 122 (Csd) in parallel with inductor 124 (Lsd). In one embodiment, where input 126 (Vin) is coupled with an antenna designed to receive Wifi or WiMax bands in the 2.3-2.5 GHz ranges, the resonant traps may be designed to attenuate the 1.9-2 GHz Personal Communication Services (PCS) band. In one embodiment, memory 128 represents a programmable memory that is able to control variable components (for example capacitors 116 and 122) of the resonant traps to attenuate varying frequency bands.
In some embodiments, bias voltage 129 (Vb1) of common-source transistor 112 may be selected to place LNA 100 in a class AB mode to produce linear output current to avoid current compression or excessive current expansion. In some embodiments, bias voltage 132 (Vb3) of the second common-gate transistor 104 may be selected based on bias voltage 130 of the first common-gate transistor 114. In some embodiments, bias voltages 130 and 132 are selected to place common-gate transistors 114 and 104, respectively into a high gain mode, although the scope of the invention is not limited in this respect. In some embodiments, bias voltages 130 and 132 may be dynamically biased.
In some embodiments, common-source transistor 112, common-gate transistor 114 and common-gate transistor 104 may comprise low-breakdown voltage N-MOS transistors, although the scope of the invention is not limited in this respect as the configuration of LNA 100 may also be suitable for use with P-MOS and other types of transistors (e.g., bipolar transistors).
In some embodiments when the transistors of LNA 100 share the same well, the body contacts (not shown) of the transistors may be connected to ground. In other embodiments, when the transistors have separate wells, their body contacts may be connected to the transistor's source, although the scope of the invention is not limited in this respect.
In some embodiments, cascode amplifier 102 may also include inductors 136 (Lbw) and 140 (Lin) and capacitors 134 (Csh) and 138 (Cin), which may serve as a part of an input-matching network. LNA 100 may be coupled to power supply 106 through inductor 142 (Lo) and capacitor 144 (Co1) and the output 110 of LNA 100 may be provided through output capacitor 146 (Co2). Inductor 142 and capacitors 144 and 146 may be part of an output matching network that may be selected based on the load of LNA 100.
In some embodiments, LNA 100 may be part of a differential LNA in which two single-ended LNAs may operate together as a differential LNA. In these embodiments, LNA 100 may operate as a single-ended LNA and another LNA, which may be identical to LNA 100, may operate as the other single-ended LNA. Each single-ended LNA may receive and amplify one portion of a differential signal.
In some embodiments, bias voltage 228 (Vb3) of the second common-gate transistor 216 may be selected based on bias voltage 230 of the first common-gate transistor 214. In some embodiments, bias voltages 228 and 230 are selected to place common-gate transistors 216 and 214, respectively, into a high gain mode, although the scope of the invention is not limited in this respect. In some embodiments, bias voltages 228 and 230 may be dynamically altered.
LNA 200 also includes a notch filter to attenuate undesired signals. As shown, LNA 200 includes passive components including inductor 236 (Lt) capacitor 234 (Cro) and capacitor 232 (Ct) to form a filter at the output of amplifiers 202 and 204, however it should be appreciated that components 236, 234 and 232 could be variable components as well.
Common-source amplifiers 202 and 204 are shown as including input matching networks, however the components shown are merely one example and the scope of the present invention is not limited to the configuration shown.
In some embodiments, common-source amplifiers 202 and 204 may also include bias voltages 210 and 212, respectively, which may serve to establish class AB mode biasing for large blocking signals. LNA 200 may be coupled to power supply 218 through inductor 224 (Lo) and capacitor 222 (Co1) and the output 220 of LNA 200 may be provided through output capacitor 226 (Co2). Inductor 224 and capacitors 222 and 220 may be part of an output matching network that may be selected based on the load of LNA 200.
In some embodiments, LNA 304 may amplify RF input signals received through antenna 302 with a cascode amplifier and a common-gate stage. LNA 304 may include one or more integrated notch filter(s) to attenuate undesired signals, may operate from a large power supply, and may be biased and designed to operate in a class AB mode to produce linear output current. In some embodiments, LNA 100 (
In some embodiments, LNA 304 may comprise multiply amplifiers such as LNA 200 (
In one embodiment, downconverter 306 represents a passive mixer terminated into a low impedance resulting in LNA 304 achieving a very high single tone out of channel compression point of around 0 dBm, which is typically 10-20 dB greater than prior art implementations. This compression point may be achieved with an out of channel signal as close as about 100 MHz away from the desired signal, which previously has not been possible without front end filtering.
Although receiver 300 is illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements, such as processing elements including digital signal processors (DSPs), and/or other hardware elements. For example, some elements may comprise one or more microprocessors, DSPs, application specific integrated circuits (ASICs), and combinations of various hardware and logic circuitry for performing at least the functions described herein. In some embodiments, the functional elements of receiver 300 may refer to one or more processes operating on one or more processing elements.
In some embodiments, receiver 300 may be part of a portable wireless communication device, such as a personal digital assistant (PDA), a laptop or portable computer with wireless communication capability, a web tablet, a wireless telephone, a wireless headset, a pager, an instant messaging device, a digital camera, an access point, a television, a medical device (e.g., a heart rate monitor, a blood pressure monitor, etc.), or other device that may receive and/or transmit information wirelessly.
In some embodiments, receiver 300 may be part of a wireless communication device that communicates in accordance with one or more communication techniques and/or standards, such as the Global System for Mobile Communications (GSM) standard. In some embodiments, receiver 300 may receive signals in accordance with a spread-spectrum technique, such as code division multiple access (CDMA). In some embodiments, receiver 300 may be a multicarrier transmitter that may receive orthogonal frequency division multiplexed (OFDM) communication signals over a multicarrier communication channel. The OFDM signals may comprise a plurality of orthogonal subcarriers. In some of these multicarrier embodiments, receiver 300 may be part of a wireless local area networks (WLANs) communication station such as a wireless access point (AP), base station or a mobile device including a Wireless Fidelity (WiFi) device. In some multicarrier embodiments, receiver 300 may be part of a broadband wireless access (BWA) network communication station, such as a Worldwide Interoperability for Microwave Access (WiMax) communication station, although the scope of the invention is not limited in this respect.
In some embodiments, receiver 300 may communicate in accordance with specific communication standards, such as the Institute of Electrical and Electronics Engineers (IEEE) standards including IEEE 802.11(a), 802.11(b), 802.11(g), 802.11(h) and/or 802.11(n) standards and/or proposed specifications for WLANs, although the scope of the invention is not limited in this respect as they may also be suitable to transmit and/or receive communications in accordance with other techniques and standards. In some embodiments, receiver 300 may communicate in accordance with the IEEE 802.16-2004 and the IEEE 802.16(e) standards for wireless metropolitan area networks (WMANs) including variations and evolutions thereof, although the scope of the invention is not limited in this respect as they may also be suitable to transmit and/or receive communications in accordance with other techniques and standards. For more information with respect to the IEEE 802.11 and IEEE 802.16 standards, please refer to “IEEE Standards for Information Technology—Telecommunications and Information Exchange between Systems”—Local Area Networks—Specific Requirements—Part 11 “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY), ISO/IEC 8802-11: 1999”, and Metropolitan Area Networks—Specific Requirements—Part 16: “Air Interface for Fixed Broadband Wireless Access Systems,” May 2005 and related amendments/versions.
Antenna 302 may comprise one or more directional or omnidirectional antennas, including, for example, dipole antennas, monopole antennas, patch antennas, loop antennas, microstrip antennas, or other types of antennas suitable for transmission of RF signals. In some embodiments, instead of two or more antennas, a single antenna with multiple apertures may be used. In these embodiments, each aperture may be considered a separate antenna. In some multiple-input, multiple-output (MIMO) embodiments, the antennas may be effectively separated to take advantage of spatial diversity and the different channel characteristics that may result between each of the antennas a transmitting communication station.
The Abstract is provided to comply with 37 C.F.R. Section 1.72(b) requiring an abstract that will allow the reader to ascertain the nature and gist of the technical disclosure. It is submitted with the understanding that it will not be used to limit or interpret the scope or meaning of the claims.
In the foregoing detailed description, various features are occasionally grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments of the subject matter require more features than are expressly recited in each claim. Rather, as the following claims reflect, invention may lie in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment.
