Claims
- 1. A high-voltage power device structure having a low R.sub.ds(on), comprising:
- a source region of a first conductivity type formed in a silicon substrate region;
- a gate electrode located over said silicon substrate region adjacent said source region;
- a high voltage doped drift region of said first conductivity type and a first dopant concentration located in a semiconductor region, said semiconductor region comprising at least one material other than silicon;
- a doped drain region of said first conductivity type and a second dopant concentration greater than said first dopant concentration located in said high voltage drift region;
- a first diffused region of said first conductivity type located in said silicon substrate region adjacent said gate electrode;
- a second diffused region of said first conductivity type located in said high voltage drift region and connected to said first diffused region.
- 2. The device structure of claim 1, wherein said semiconductor region comprises a GaAs substrate region.
- 3. The device structure of claim 1, wherein said semiconductor region comprises a SiC substrate region.
- 4. The device structure of claim 1, wherein said high-voltage drift region is formed within a trench of said silicon substrate region.
- 5. The device structure of claim 1, wherein said high-voltage drift region is formed on a SiO.sub.2 region separating said silicon substrate region from said high-voltage drift region.
- 6. The device structure of claim 1, wherein said silicon substrate region is formed on a first chip and said semiconductor region is formed on a second chip, said first chip being distinct from said second chip.
- 7. A method of forming a power device structure having a low R.sub.ds(on) comprising the steps of:
- forming a gate electrode over a silicon substrate region;
- forming a source region of a first conductivity type and a first diffused region of said first conductivity type in said silicon substrate region;
- forming a high voltage doped drift region of said first conductivity type and a first dopant concentration in a semiconductor region, said semiconductor region comprising at least one non-silicon material;
- forming a second diffused region of said first conductivity type and a doped drain region of said first conductivity type and a second dopant concentration greater than said first dopant concentration in said high voltage drift region; and
- connecting said first diffused region to said second diffused region.
- 8. The method of claim 7, wherein said semiconductor region comprises a GaAs substrate region.
- 9. The method of claim 7, wherein said semiconductor region comprises a SiC substrate region.
- 10. The method of claim 7, wherein said high-voltage drift region is formed within a trench of said silicon substrate region.
- 11. The method of claim 7, wherein said high-voltage drift region is formed on a SiO.sub.2 region separating said silicon substrate region from said high-voltage drift region.
- 12. The method claim 7, wherein said silicon substrate region is formed on a first chip and said semiconductor region is formed on a second chip, said first chip being distinct from said second chip.
- 13. A hybrid power MOSFET comprising:
- a source region formed in a silicon substrate region;
- a gate electrode located over said silicon substrate region adjacent said source region;
- a high voltage doped drift region of a first conductivity type and a first dopant concentration located in a non-silicon-only semiconductor region; and
- a doped drain region of the first conductivity type and a second dopant concentration greater than said first dopant concentration located in said high voltage drift region.
- 14. The hybrid power MOSFET of claim 13 further comprising:
- a first diffused region located in said silicon substrate region adjacent said gate electrode;
- a second diffused region located in said high voltage drift region and connected to said first diffused region.
- 15. The hybrid power MOSFET of claim 13, wherein said non-silicon-only semiconductor region comprises a GaAs substrate region.
- 16. The hybrid power MOSFET of claim 13, wherein said non-silicon-only semiconductor region comprises a SiC substrate region.
- 17. The hybrid power MOSFET of claim 13, wherein said high-voltage drift region is formed within a trench of said silicon substrate region.
- 18. The hybrid power MOSFET of claim 13, wherein said high-voltage drift region is formed on a SiO.sub.2 region separating said silicon substrate region from said high-voltage drift region.
- 19. The hybrid power MOSFET of claim 13, wherein said silicon substrate region is formed on a first chip and said non-silicon-only semiconductor region is forming on a second chip, said first chip being distinct from said second chip.
Parent Case Info
This is a Continuation of application Ser. No. 08/459,369, filed on Jun. 2, 1995, now U.S. Pat. No. 5,589,695.
US Referenced Citations (4)
Continuations (1)
|
Number |
Date |
Country |
Parent |
459369 |
Jun 1995 |
|