Patent Application
20080129348
The present invention relates to output drivers for integrated circuits (IC), and more particularly to low power, high performance output drivers designed to drive multiple-level switching partial-voltage signals.
In this patent application, an “output driver” is defined as the last-stage circuit used to drive output signals from an IC to external components. A “high performance output driver” is the last-stage circuit used to drive high performance switching signals from an IC to external components while it is designed to support output signal switching rate higher than thousands, millions, billions of cycles per second, or higher. A “pull up transistor” is defined as a transistor configured to provide channel current in a direction to pull the output signal only to higher voltage. A “pull down transistor” is defined as a transistor that is configured to provide channel current in a direction to pull the output signal only to lower voltage. An “n-channel transistor” is defined as a transistor that uses electrons as the majority carrier to carry its channel current. A “p-channel transistor” is defined as a transistor that uses holes as the majority carrier to carry its channel current. One transistor can comprise many legs of transistors connected in parallel. A “partial-voltage signal” is a signal with steady state voltage level lower than the pull up voltage supply of the output driver driving the signal, and higher than the pull down voltage supply of said output driver.
Today, IC technologies have progressed into nanometer (nm) ranges. Current art 65 nm logic technologies provide transistors with switching time measured by 10−12 seconds (ps). It has become a routine practice to design logic circuits capable of executing billions or even trillions of operations per second. Such powerful core circuits require the supports of powerful interface circuits. Otherwise, input/output (I/O) bandwidth would become the performance bottleneck in high performance systems. It is therefore highly desirable to provide methods to improve the performance of I/O circuits for integrated circuits.
The performance of output drivers has significant impacts to overall system performance. The most common output drivers used by prior art IC are CMOS (complemented metal-oxide-semiconductor) drivers. CMOS drivers consume little power at steady state, and provide signals in full amplitude of I/O voltage supply source to represent digital data. However, switching noise related problems limited CMOS drivers in supporting high performance interfaces. It is therefore highly desirable to provide output drivers that can avoid switching noise problems to support high performance operations.
The most popular prior art method used to improve the performance of CMOS drivers is to reduce the amplitude of the output signals by introducing one or more termination resistor(s) to each signal line. The termination resistor is typically connected to a reference voltage equal to half of the I/O voltage supply source. The same reference voltage is also used for input data sensing. This method is called “high-speed transceiver logic” (HSTL) interface when it is used by high end SRAM (static random access memory) interface. A nearly identical method is also called “stub series terminated logic” (SSTL) interface when it is used by DRAM (dynamic random access memory) interface. These type of methods are called “small amplitude interfaces” (SAI) in our discussions. SAI effectively improved interface performance relative to conventional CMOS interfaces. However, SAI drivers consume power even when they are not switching data, and they still suffer most of the noise problems suffered by conventional CMOS drivers. It is therefore highly desirable to provide further improvements in performance relative to SAI while consuming little power at steady states.
Wireless devices such as cellular phones have progressed in explosive pace. Battery powered portable devices always require low power consumption. In the mean time, the demands for higher performance increase dramatically with each generation of wireless products. For example, cellular phones used to have no or very simple displays; now they require colored liquid crystal display (LCD) at high resolution. A current art LCD driver can send out 132 RGB signals (total 396 digital-to-analogy converter output signals) with 6 bit accuracy (64 levels) switching around 12 KHZ. Such IC devices require high accuracy, low power, digital-to-analog (D/A) output drivers. Most of prior art digital-to-analog converters use operation amplifiers with negative feedback to provide high accuracy output signals, but operation amplifiers typically consume a lot of power and have poor switching speed. Tsuchi disclosed an LCD driver design in U.S. Pat. No. 6,124,997 that does not use operation amplifiers; the method requires pre-charging each output line before driving a new data. The pre-charge operation will consume power no matter the data is changed or not. Since Tsuchi only use pull down driver, the method is sensitive to noises that cause the output signal to drop below targeted voltages. It is therefore highly desirable to provide low power output drivers that can support high accuracy switching signals.
Ohba et al in U.S. Pat. No. 4,816,705 disclosed methods to make the output voltages of BiMIS logic circuits almost equal to that of the voltage supply sources. Ohba drivers drive internal signals so they are not output drivers. The non-inverting buffers in Ohba uses n-channel pull up transistors and p-channel pull down transistors as the biasing circuits for the drivers as methods to increase the range of output voltages; they are not used as the transistors to drive the outputs. Ohba disclosed methods to make the output voltages of BiMIS logic circuits almost equal to that of the voltage supply sources. The Application disclosed special kinds of output drivers that support multiple-level switching partial-voltage signals. Nair in U.S. Pat. No. 6,958,632 disclosed voltage follower buffers. The purpose of Nair is to reduce power line noise induced timing uncertainty, called “jitter”, on internal signal buffers such as clock buffers. The output of the buffer is driven by an n-channel pull up transistor that can pull the output up to Vcc−Vtn, a p-channel pull down transistor that can pull the output up to Vss+Vtp, and a CMOS buffer that drives the output to full scale voltages Vcc or Vss. Where Vtn is the threshold voltage of the n-channel transistor and Vtp is the threshold voltage of the p-channel transistor. These drivers are internal signal buffers instead of output drivers. Nair disclosed methods to make the output voltages of buffer equal to that of the voltage supply sources instead of multiple-level switching partial-voltage signals. Ahn et al in U.S. Pat. No. 6,560,290 disclosed CMOS output driver and on-chip termination for high speed data communication such as Ethernet transmitter/receiver. Ahn et al used n-channel pull up transistors and p-channel pull down transistors in the on-chip termination circuits instead of using them in the output driver. The function of a termination circuit is to imitate the functions of resistors for impedance matching purpose, and to hold the steady-state voltage of the signal bus near half of the supply voltage. There is no switching input signals connected to termination circuits so that the termination circuits are not output drivers. U.S. Pat. No. 6,384,658 by Jex disclosed circuits to generate non-inverting and inverting clock signals with balanced timing. Those circuits are clock signal generators, not output drivers. In Jex, n-channel pull up transistors and p-channel pull down transistors are used in the input stages of the clock circuits in order to balance the timing of the two inverted output signals. These transistors have no relationship to output drivers.
Previous patent application Ser. No. 11/098,991 emphasized methods and structures to reduce the power consumed by output drivers. For memory devices, cost efficiency is often considered more important than power consumption. This patent application provides additional methods and structures optimized for cost efficiency for memory input/output (I/O) interfaces such as HSTL or SSTL interfaces.
The primary objective of this invention is, therefore, to provide output drivers that consume little power at steady state while avoiding switching noise problems to support high performance operations. The other primary objective of this invention is to provide output drivers that can switch between multiple levels of high accuracy output voltages while consuming minimum power. Another objective is to support small amplitude interface protocols without using termination resistors. Another objective is to reduce the cost for output drivers that drive memory interfaces such as HSTL or SSTL interfaces. These and other objectives are achieved by using output drivers comprising n-channel pull up transistors and p-channel pull down transistors biased with proper gate voltages. The resulting circuits are capable of supporting high performance synchronized signals or high accuracy multiple level signals while consuming much less power than prior art options.
While the novel features of the invention are set forth with particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawing.
a, b) illustrate the structures and operation principles of prior art CMOS drivers;
a, b) illustrate the structures and operation principles of prior art SAI drivers;
a, b) illustrate the structures and operation principles of a basic output driver of the present invention;
c) shows the current-voltage relationship of the output driver shown in
d-i) are schematic diagrams showing variations of output driver designs of the present invention;
a-f) are schematic diagrams showing different gate voltage generation circuits to support output drivers of the present invention;
a-c) illustrate methods to use native transistors for output drivers of the present invention;
a-d) are examples of cost efficient output drivers of the present invention;
a-b) illustrate the structures and operation principles of prior art differential signal drivers; and
a-d) are examples of differential signal drivers of the present invention.
The operation principles of prior art output drivers are first discussed to facilitate clear understanding of the present invention.
a) is a schematic diagram showing the basic elements of a prior art CMOS output driver (DR1). An output driver is defined as the last-stage circuit used to drive output signals from an IC to external components. A high performance output driver defined in this patent disclosure is the last-stage circuit used to drive high performance switching signals from an IC to external components while it is designed to support output signal switching rate higher than thousands, millions, or even billions of cycles per second. This prior art output driver (DR1) comprises a p-channel pull up transistor (MP) and an n-channel pull down transistor (MN). A pull up transistor is defined as a transistor configured to provide channel current in a direction to pull the output signal only to higher voltage. A pull down transistor is defined as a transistor that is configured to provide channel current in a direction to pull the output signal only to lower voltage. An n-channel transistor is defined as a transistor that uses electrons as the majority carrier to carry its channel current. A p-channel transistor is defined as a transistor that uses holes as the majority carrier to carry its channel current. One transistor shown in a schematic diagram can comprise many legs of transistors connected in parallel.
For the prior art output driver (DR1) in
The structures of this prior art CMOS output driver (DR1) may appear to be as simple as an internal CMOS inverter, but there are many complications caused by the fact that the driver needs to provide large currents to drive heavy loading on an external signal line.
b) shows example timing control waveforms to illustrate the operation principles of the prior art CMOS driver in
For a double data rate (DDR) protocol, the rising edge of the complemented clock signal (CK#) at time T5 triggers the output driver to send out another data.
We can turn off this output driver (DR1) by setting Vgp=Vddq and Vgn=Vssq so that the output driver is at high impedance state to allow other output drivers (DR2, DR3) to drive the external signal line (Q).
The major advantages for prior art CMOS drivers are that they consume little power at steady states, and that they provide full scale outputs at voltage supply sources (Vddq, Vssq) to represent digital signals. These advantages make CMOS drivers the most popular drivers for integrated circuits. However, CMOS drivers can consume large power and cause severe noise problems during switching time. The switching noise problems and the “flow through current prevention delay time” limit the applications of CMOS output drivers in high performance applications.
a, b) illustrate the most popular prior art method used to improve the performance of CMOS drivers. This method is called “high-speed transceiver logic” (HSTL) interface when it is used by high end SRAM (static random access memory) interface. A nearly identical method is also called “stub series terminated logic” (SSTL) interface when it is used by DRAM (dynamic random access memory) interface. The major difference between the CMOS interface shown in
b) shows example timing waveforms to illustrate the operation principles of SAI in comparison with CMOS interface waveforms in
Similar to the example in
We can turn off this output driver (DR1) by setting Vgp=Vddq and Vgn=Vssq so that the output driver is at high impedance state to allow other output drivers (DR2, DR3) to drive Q′.
SAI methods improve interface performance by reducing the amplitude of switching output signals. That is achieved by using a termination resistor to fight with output drivers; the resulting circuits always consume power even at steady states. Typically, a SAI driver needs to provide a current around 15 mini-Amps to fight with the termination resistor. A 72-signal data bus will consume about 1 Amp of current even when there is no switching activity. This is a tremendous waste in energy. In addition, SAI drivers still suffers the same switching noise problems and the “flow through current prevention delay time” as CMOS output drivers. It is highly desirable to provide an output driver that has the advantages of small amplitude switching while removing the noise and power problems.
a) is a schematic diagram showing simplified structures for an output driver (DRj1) of the present invention. This output driver (DRj1) also comprises a p-channel transistor (MPj) and an n-channel transistor (MNj). The differences are that the p-channel transistor (MPj) is configured as a pull down transistor, and that the n-channel transistor (MNj) is configured as a pull up transistor. A pull up transistor is defined as a transistor configured to provide channel current in a direction to pull the output signal only to higher voltage. A pull down transistor is defined as a transistor that is configured to provide channel current in a direction to pull the output signal only to lower voltage. An n-channel transistor is a transistor that uses electrons as the majority carrier to carry its channel current. A p-channel transistor is a transistor that uses holes as the majority carrier to carry its channel current. Prior art output drivers use n-channel transistors as pull down transistors, and use p-channel transistors as pull up transistors. The present invention inverts the rolls of the driving transistors in output drivers by using n-channel transistors as pull up transistors, and using p-channel transistors as pull down transistors to drive external signals.
In
In this configuration, the channel current of the pull up n-channel transistor (MNj) is controlled by its gate voltage Vgnj relative to the out put voltage (Vqj). When (Vgnj−Vqj) is smaller than the threshold voltage (Vtn) of the n-channel transistor (MNj), the transistor is turned off. When (Vgnj−Vqj) is larger than Vtn, the channel current (Isn) of the n-channel pull up transistor (MNj) can be described by a text book equation as
Isn=Kn(Wn/Ln)(Vgnj−Vqj−Vtn)2˜Kn(Wn/Ln)(Vqtn−Vqj)2 (EQ1)
where (Wn/Ln) is the width/length ratio of the transistor, and Kn is a parameter dependent on electron mobility. In other words, the n-channel pull up transistor (MNj) will pull up the output voltage Vqj toward the target voltage Vqtn if its gate voltage is set as Vgnj˜Vqtn+Vtn. The driving channel current (Isn) increase rapidly with (Vqtn−Vqj) but the driving current is very small once the output voltage Vqj is pulled near the target voltage Vqtn. This circuit configuration has an automatic negative feedback mechanism.
Similarly, the driving capability of the pull down p-channel transistor (MPj) is controlled by its gate voltage Vgpj relative to the out put voltage (Vqj). When (Vqj−Vgpj) is smaller than the amplitude of the threshold voltage (Vtp) of the p-channel transistor (MPj), the transistor is turned off. When (Vqj−Vgpj) is larger than Vtp, the channel current (Isp) of the p-channel pull down transistor (MPj) can be described by a text book equation as
Isp=Kp(Wp/Lp)(Vqj−Vgpj−Vtp)2Kp(Wp/Lp)(Vqj−Vqtp)2 (EQ2)
where (Wp/Lp) is the width/length ratio of the transistor, and Kp is a parameter dependent on hole mobility. In other words, the p-channel pull down transistor (MPj) will pull down the output voltage Vqj toward the target voltage Vqtp if its gate voltage is set as Vgpj˜Vqtp−Vtp. The driving current increase rapidly with (Vqj−Vqtp) but the driving current is very small once the output voltage Vqj is pulled near the target voltage Vqtp. This circuit configuration has an automatic negative feedback mechanism.
For most of applications, the target voltage (Vqtn) for the n-channel pull up transistor and the target voltage (Vqtp) for the p-channel pull down transistor are set to be about the same as Vqtp˜Vqtn˜Vqt so that both transistors will drive the output voltage toward the same voltage, but there are exceptions.
c) shows the current-voltage relationship of the output driver (DRj1) when Vqtp˜Vqtn˜Vqt. The actual current-voltage (I-V) relationships of modern transistors are more complicated than those simplified equations (EQ1, EQ2). The threshold voltages (Vtp, Vtn) are also complex functions of bias voltages due to body effects. However, the general principles are correct. By setting gate voltages Vgpj˜Vqt−Vtp and Vgnj˜Vqt+Vtn, the output driver (DRj1) will pull the output voltage (Vqj) toward the target voltage (Vqt). The driving currents of the output driver increase rapidly with the difference between Vqj and Vqt, and the driver consumes little power once Vqj is pulled close to target voltage Vqt. In other words, an output driver of the present invention can pull its output voltage to an analog voltage with strong driving power, while holding the output voltage at the target voltage without consuming much power.
An output driver, by definition, is the last-stage circuit used to drive output signals from an IC to external components. A high performance output driver defined in this patent disclosure is the last-stage circuit used to drive high performance switching signals from an IC to external components while it is designed to support output signal switching rate higher than thousands, millions, or even billions of cycles per second. Prior art reference voltage generators have used similar negative feedback mechanism to generate reference voltages at fixed levels. A typical example would be the bit line pre-charge voltage generator for memory devices as discussed in U.S. Pat. No. 6,216,246. Reference voltage generators are designed to drive constant or near-constant target voltages; the output voltages of reference voltage generators may be adjustable, but reference voltage generators are not designed to support frequent switching output voltages. The present invention discloses methods to use n-channel pull up transistors in combination with p-channel pull down transistors to drive high performance synchronized switching interface signals so that the structures and design considerations in our circuits are optimized to reduce switching noises and to improve switching performances.
Based on the above principles, we can use the output driver (DRj1) shown in
b) shows example timing waveforms to illustrate the operation principles of the output driver in
Similar to the example in
The above example shows that output drivers of the present invention can drive output signals at voltage levels fully compatible with existing SAI systems while achieving better performance and consuming less power.
We also can turn off the output driver (DRj1) of the present invention by setting Vgpj=Vddq and Vgnj=Vssq so that the output driver is at high impedance state to allow other output drivers (DRj2, DRj3) to drive Qj. Another way is to set Vgpj=Vph and Vgnj=Vns to put the driver (DRj1) into high impedance state. Under this condition, the driver still allows other drivers to drive Qj, while it can help to confine the output voltage (Vqj) within SAI ranges (between Voh and Vos) even when no driver is activated. This is an example for the situations when the target voltage for the n-channel pull up transistor is different from the target voltage for the p-channel pull down transistor.
The above example shows that the output driver of the present invention has the following advantages over prior art SAI drivers:
(1) It can drive output voltages fully compatible with SAI standards (such as the HSTL or SSTL interface standards) without using a termination resistor, achieving significant power savings.
(2) The gate voltages of the output driver of the present invention also swing with small amplitudes, making it possible to achieve faster switching time.
(3) The gate voltages switch in the same direction as the output voltage so that capacitor coupling noises are not causing problems.
(4) The pull up transistor and the pull down transistor of an output driver of the present invention are never turned on simultaneously at normal operations. Therefore, we do not need to worry about “flow through current prevention delay time”. The switching time is faster, and the control circuit is simpler.
(5) The output driver of the present invention has strong driving power when the output voltage is far from the target voltage, while the driving power decreases as the output voltage approaches the target voltage. This automatic adjustment in driving power minimizes the switching noise while achieving fast switching time.
(6) The output driver of the present invention can be biased into high impedance state while stabilizing the output voltage to stay within SAI range without using a termination resistor.
The most significant disadvantage for output driver of the present invention is that its driving currents are smaller than prior art drivers of equivalent size due to smaller gate to source bias voltages and body effects. This disadvantage can be overcome by using larger or faster transistors. Another solution is to reduce the threshold voltages of the driving transistors.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The basic structure for an output driver of the present invention comprises an n-channel pull up transistor and a p-channel pull down transistor. A circuit designer can use many kinds of equivalent circuits to build the same driver. We will discuss a few more examples in the following sections. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.
d) shows a common modification where a serial termination resistor (Rq) or a current limiting device is placed between the internal signal line (Qd) of an output driver and an external signal line (Qj). Placing a serial termination resistor (Rq) or other types of current limiting devices this way can help to reduce signal reflections on the external signal line (Qj). The serial termination resistor (Rq) or current limiting devices can be placed inside or outside of IC chips. For example, DDR (double data rate) DRAM place such serial termination resistors outside while DDRII (second generation DDR) DRAM have the option to place the serial termination resistors inside the DRAM chips.
e) shows another type of current limiting method for output drivers of the present invention. The source electrode of the n-channel pull up transistor (MNj) is connected to a current source (Ih) that is connected to power line at voltage Vddq. The source electrode of the p-channel pull down transistor (MPj) is also connected to another current source (Ib) that is connected to power line at voltage Vssq, where Vssq<Vddq. This modification assures that the driving current of the driver can never shoot higher than the currents provided by the current sources (Ih, Ib). This method is very effective in reducing switching noises, especially for inductance induced noises. Replacing the current sources (Ih, Ib) with resistors or other type of current limiting devices can have similar effects.
d) represents current sources by symbols instead of actual transistor level schematics. A “current source” here can be one transistor that is biased into saturation conditions, a current limiting device such as a simple resistor, and it also can be a much more complicated circuit. The current sources referred in the present invention also do not need to be ideal current sources. Basically we call current limiting devices as current sources in our discussions. For all the circuit examples in our discussions, the current sources can be replaced by simple resistors or biased transistors and those circuits will still work. The most common circuits used as current sources are “current mirrors” that are well known to circuit designers. Methods to design current sources are well known to most of circuit designers so we will not describe in further details about the transistor level circuits for current sources. For simplicity, we will represent current limiting devices by an arrow in a circle as Ih or Ib in
For the examples described in
The major advantage of the driver in
We certainly can combine multiple methods illustrated in
i) shows a variation design that is more intuitive for prior art circuit designers. This circuit uses a driver (DRvoh) of the present invention that is configured to drive an internal line (Qvoh) at upper SAI voltage (Voh). This line (Qvoh) is connected to the source electrode(s) of one or a plurality of p-channel pull up transistors (MPw1, MPw2, MPw3). It also uses another driver (DRvos) of the present invention that is configured to drive an internal line (Qvos) at lower SAI voltage (Vos). This line (Qvos) is connected to the source electrode(s) of one or a plurality of n-channel pull down transistors (MNw1, MNw2, MNw3). The drain electrode(s) of p-channel pull up transistors (MPw1, MPw2, MPw3) and the drain electrode(s) of n-channel pull down transistors (MNw1, MNw2, MNw3) are connected to one or a plurality of external signal lines (Qj1, Qj2, Qj3) as shown in
One of the requirements to use the output driver of the present invention is to provide gate voltages about one threshold voltage away from target voltages. The transistor threshold voltages (Vtn, Vtp) can be a complex function of manufacture procedures, substrate voltages, temperature, and device geometry. It is therefore a good practice to provide supporting circuits to generate proper gate voltages for the output drivers of the present invention.
Iin=Kn(Wnm/Lnm)(Vgnj−Vdj−Vtn)2 (EQ3)
Where (Wnm/Lnm) is the width/length ratio of the n-channel matching transistor (MNm), and Kn is a parameter related to electron mobility. If there is a good match between MNm and MNj, the parameter Kn in EQ1 and in EQ3 should be the same, and their threshold voltage should be the same. When the current (Iin) of the current source (In) is small, we have (Vgnj−Vdj)˜Vtn, meeting the requirement to provide gate bias voltage close to one threshold voltage above the target voltage (Vdj). Using EQ1 and EQ3, when Vqj>Vdj, the driver current (Isn) of the n-channel pull up transistor can be written as
Isn˜Iin[(Wn/Ln)/(Wnm/Lnm)](Vqj−Vdj)2 (EQ4),
meaning that the n-channel pull up transistor (MNj) will try to pull Vqj toward Vdj, and that the channel current of the n-channel pull up transistor is proportional to the current (Iin) of the current source (In) in the gate voltage generation circuit (GCj).
Similarly, the gate electrode of the p-channel pull down transistor (MPj) is connected to the gate electrode and the source electrode of a matching p-channel transistor (MPm), and to one terminal of a current source (Ip). The other terminal of the current source (Ip) is connected to lower voltage supply line at voltage Vss, where Vss<Vdd. Vss can be the same as Vssq; it also can be different. The drain electrode of the matching transistor (MPm) is connected to the input line (Dj) as shown in
Iip=Kp(Wpm/Lpm)(Vdj−Vgpj−Vtp)2 (EQ5)
Where (Wpm/Lpm) is the width/length ratio of the p-channel matching transistor (MPm), and Kp is a parameter related to hole mobility. If there is a good match between MPm and MPj, the parameter Kp in EQ2 and EQ5 should be identical, and they should have the same threshold voltage. When the current (Iip) of the current source (Ip) is small, we have (Vdj−Vgpj)˜Vtp, meeting the requirement to provide gate bias voltage close to one threshold voltage below the target voltage (Vdj). Using EQ2 and EQ5, when Vdj>Vqj, the driver current (Isp) of the p-channel pull down transistor can be written as
Isp˜Iip[(Wp/Lp)/(Wpm/Lpm)](Vdj−Vqj)2 (EQ6),
meaning that the p-channel pull down transistor will try to pull Vqj toward Vdj, and the channel current of the p-channel pull down resistor (MPj) is proportional to the current (Iip) of the current source (Ip) in the gate voltage generation circuit (GCj).
If we let the two current sources (In, Ip) provide the same currents (Iin=Iip), and let [(Wn/Ln)/(Wnm/Lnm)]=[(Wp/Lp)/(Wpm/Lpm)], at steady state we will have Vqj˜Vdj. In other words, the output voltage (Vqj) will automatically follow the input voltage (Vdj) when we use the gate voltage generator (GCj) in
b) shows another circuit example that has the same gate voltage generation circuits (CGj) as that in
As shown by EQ3-EQ6, the driving power as well as the steady state leakage current of the driver in
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. For example, we can replace the current sources in the above examples with other current limiting circuits such as resistors while the circuits will still work. The currents of the current sources certainly can be changed in analog methods instead of using switches. It is therefore to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed in this patent disclosure.
d) shows one example of design variation for a circuit that is nearly identical to the circuit in
e) shows another example of design variation for a circuit that is nearly identical to the circuit in
Multiple activated drivers of the present invention can drive the same output; it is even possible to have other types of drivers driving the same output line in parallel.
The examples in
Prior art output drivers typically use enhance mode transistors with high threshold voltage in order to reduce leakage currents. Output drivers of the present invention have natural feedback mechanism to control leakage current. To have better driving power for the same size of transistors, it is desirable to use transistors with low threshold voltage, native transistors, or even depletion mode transistors for output drivers of the present invention. Most of current art IC technologies already provide native transistors. We also can add additional threshold adjusting masking steps to manufacture transistors with desired threshold voltages for applications of the present invention. Another interesting method is to use floating gate devices as the driver transistors because the threshold voltages of floating gate devices are programmable.
Most of current art IC technologies provide options for n-channel native transistors but few of them provide p-channel native transistors.
Due to body effects, the effective threshold voltage of a native transistor may not stay around 0 volts at different operations conditions.
Prior art SAI drivers only can switch between two voltage levels (Voh and Vos) to represent one binary data per phase. The output drivers of the present invention have the accuracy to switch between multiple levels of analog voltages. It can easily support four-level data format to represent two binary bits per phase, or 16-level data format to represent 4 binary bits per phase. In other words, output drivers of the present invention will be able to improve data bandwidth while running at the same clock rate. When it is designed carefully, a driver of the present invention can support the functions of a high speed digital to analog (D/A) converter, providing output voltages switching between hundreds or thousands of analogy levels. Prior art high performance D/A converters consume large power. A D/A converter equipped with analog switching output driver of the present invention consume very little power while it can operate at high switching rate providing accurate outputs.
The numbers listed in table 2 are for references only; the actual numbers will change with detailed applications.
Current art HSTL SRAM interface is a two level small signal switching interface. Currently HSTL interface supports 333 MHZ DDR operations achieving 666 Mbits/second per data line. Output drivers of the present invention can support the same standard at higher switching rate without using termination resistors.
Current art SSTL DRAM interface is a two level small signal switching interface. Currently SSTL interface supports 226 MHZ DDRII operations achieving 533 Mbits/second per data line. Output drivers of the present invention can support the same standard at higher switching rate without using termination resistors.
Output drivers of the present invention can easily support 4-level switching at 500 MHZ clock rate to replace HSTL or SSTL interfaces. With careful design, 8-level or 16-level high speed switching are also possible.
Liquid crystal display (LCD) drivers come with many configurations. For example, an LCD driver can send out 132 RGB signals (total 396 digital-to-analogy converter output signals) with 6 bit accuracy (64 levels) switching at a relative low clock rate around 12 KHZ. For battery powered portable devices, power consumption is a major concern. Most of prior art digital-to-analog converters use operation amplifiers with negative feedback to provide high accuracy output signals, but operation amplifiers typically consume a lot of power and have poor switching speed. Tsuchi disclosed an LCD driver design in U.S. Pat. No. 6,124,997 that does not use operation amplifiers; the method requires pre-charging each output line before driving a new data. The pre-charge operation will consume power no matter the data is changed or not. Since Tsuchi only use pull down driver, the method is sensitive to noises that cause the output signal to drop below targeted voltages. Output drivers of the present invention have much better accuracy; they can hold the data at targeted value with little power; and they consume no power when the data is not changed. LCD drivers using output drivers of the present invention are therefore better than prior art products.
High resolution graphic display output 1024×900 pixels of RGB (red-green-blue) data with 8 bit resolution (256 levels) on each data. That requires outputting ˜60 M 256-level data per second. Drivers of the present invention can support both the accuracy and the data rate.
The most popular high performance interfaces for current art memory devices are the “small amplitude interfaces” (SAI), including the HSTL interface commonly used by SRAM devices and the SSTL interface commonly used by DRAM devices. As discussed previously, the output drivers of the present invention can be fully compatible with existing SAI without using termination resistors—achieving lower power consumption at higher speed. For many memory devices, cost efficiency is considered more important than power saving. The sizes of the output drivers discussed previously are about the same as prior art output drivers. It is therefore desirable to provide cost saving methods for SAI memory devices.
a-d) illustrate cost saving structures/methods of the present invention using single-transistor output drivers driving against complemented termination transistors. The applications for these single-transistor drivers of the present invention are limited to partial-voltage memory interface (PVMI) circuits. A PVMI use partial-voltages that are between the pull up voltage supply source (Vddq) and the pull down voltage supply source (Vssq) of the output drivers to represent data values on IC external signals in order to support memory input/output operations. Typical examples of PVMI are the HSTL interface for SRAM and the SSTL interface for DRAM. A single-transistor output driver uses one transistor to provide the majority of the switching current that drives the value of an IC external PVMI signal according to the value of its switching gate voltage. A single-transistor output driver can have many supporting circuits such as bias circuits, timing circuits, control circuits, electro-static protection circuits, and so on, but the majority of the output driving power is provided by one transistor. Such “single-transistor” certainly can comprise many legs of transistors connected in parallel to function as one transistor in order to provide the driving current. A complemented termination transistor (CTT) provides the driving power against single-transistor output driver(s). When the single-transistor drivers are pull up transistors, the CTT would be a p-channel pull down termination transistor. When the single-transistor drivers are pull down transistors, the CTT would be an n-channel pull up termination transistor. An n-channel pull up termination transistor is defined as an n-channel pull up transistor that is configured to hold the steady-state voltage of an IC external PVMI signal near a pre-defined partial-voltage. Unlike the n-channel pull up transistors used in an output driver, the gate voltage of an n-channel pull up termination transistor is not switched when the output signal is switched—the gate voltage of termination transistor is typically held at a constant level during signal switching events; said constant level may have variations due to the influence of noise. A p-channel pull down termination transistor is defined as a p-channel pull down transistor that is configured to hold the steady-state voltage of an IC external PVMI signal near a pre-defined partial-voltage. Unlike the p-channel pull down transistors used in an output driver, the gate voltage of a p-channel pull down termination transistor is not switched during data switching events—the gate voltage of termination transistor is typically held at a constant level during signal switching events; said constant level may have variations due to the influence of noise.
a) is a schematic diagram showing simplified structures for output drivers of the present invention that is designed to achieve low cost at high performance. To achieve optimum cost efficiency, each output driver is simplified to be a single-transistor driver. For the example in
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The present invention is not limited to particular implementation discussed in specific examples. For example,
For the example in
For the example in
For the example in
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The present invention is not limited to particular implementation discussed in specific examples. For example, the above examples are all single-ended signal drivers while output drivers of the present invention are excellent in driving differential signals.
Differential signaling is a method of transmitting information electrically by means of two complementary signals sent on two separated wires with matched properties.
The most important advantage of differential signaling is noise tolerance. The differential sense amplifiers (DSA) are typically designed to have excellent common mode noise rejection. Differential signal transfer systems are therefore capable of transferring data under noisy conditions if the major noise sources are common mode noises such as coupling noises or shifting in power/ground voltages. However, prior art differential signal transfer systems are sensitive to resistance/inductance on the signal lines (Q+, Q−) or differential mode noises; they also have problems in driving signal lines with heavy capacitance loading because of the constraint in driving current.
Drivers of the present invention are excellent in driving differential signals.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The present invention is not limited to particular implementation discussed in specific examples. There are wide varieties of methods to design differential signal output drivers of the present invention. For example,
Using output drivers of the present invention, it is possible to remove the loading resistor (RL) while the voltages on the differential signal lines (Q+, Q−) still meets the requirements of differential signal interface specifications.
Differential signal output drivers of the present invention have many advantages over prior art differential signal output drivers. The driving power of prior art differential signal output drivers are limited by the loading resistor (RL) because IL*RL must be equal to the voltage drop limited by the specification of signal transfer protocols. This limitation in driving power limits the performance of prior art differential signal drivers. The output voltages of the drivers of the present invention are weakly dependent on RL so that we can scale the driving capability to achieve better performance. The prior art current mode differential signal output drivers are consuming power even when the outputs are not switching. The differential output drivers of the present invention provide the option to remove loading resistors to save power. Prior art differential signal output drivers can not support large fan-out configurations that require multiple termination resistors. A Differential output driver of the present invention can support large fan-out because its output voltage is not sensitive to the size of termination resistors. Prior art differential signal output drivers are sensitive to parasitic resistance or leakage current on the signal lines, while differential signal output drivers of the present invention is not sensitive to parasitic resistance or leakage current. Differential signal output drivers of the present invention have the same common mode noise rejection as prior art different output drivers, while the present invention provides better tolerance in differential noises.
There are wide varieties of applications for differential signal output drivers of the present invention. Typical examples for the application of differential signal output drivers of the present invention are listed in Table 3.
The Stub Series Terminated Logic (SSTL) interfaces commonly used for DRAM interfaces had gone through three generations of evolution. The SSTL2 standard is commonly used for double data rate version 1 (DDRI) DRAM's with power supply voltage at 2.5 volts. The SSTL—18 standard is commonly used for double data rate version 2 (DDRII) DRAM's with power supply voltage at 1.8 volts. The SSTL—15 standard is commonly used for double data rate version 3 (DDR3) DRAM's with power supply voltage at 1.5 volts. As discussed previously, for SSTL interfaces the data and control signals are single-ended signals centered at a reference voltage at half of the power supply voltage. However, the clock signals for SSTL interface are differential signals. Drivers of the present invention are not only ideal to drive SSTL data/control signals but also ideal to drive SSTL clock signals. These and future generations of SSTL interfaces can achieve significant power savings and performance improvements using output drivers of the present invention.
The Low Voltage Differential Signal (LVDS) interfaces are developed for signal transfers at a distance up to 30 feet. Original generation of LVDS supports one-to-one signal transfers. Latter generations of LVDS support many-to-many data transfers. The LVDS interfaces are widely used for applications such as graphic interface for large flat panel display, automobile signal transfers, and communication back panel signal transfers. Drivers of the present invention can save power, increase fan-in/fan-out and improve performance of LVDS interface devices.
The Mobile Industry Processor Interface (MIPI) and the Mobile Display Digital Interface (MDDI) are similar interface protocols developed for mobile devices. The major purpose for MIPI/MDDI interfaces is to simplify routing for circuit boards used for mobile devices such as cellular phones. Interface signals between different IC chips used by mobile devices are serialized by the drivers then de-serialized by the receivers. The operation principles of MIPI/MDDI interfaces are similar to LVDS while they typically support short distance signal transfers. Power saving is certainly one of the most important design considerations for mobile devices. Differential signal output drivers of the present invention are very helpful in saving power while improving performance for the MIPI/MDDI output drivers.
A differential signal output driver, by definition, is the last-stage circuit providing the majority of the driving force (while turned on) to drive a pair of differential signals external to integrated circuits. Differential signal output drivers of the present invention drive switching partial voltages to external differential signal lines. Signal lines internal to integrated chips have different design constraints so that they are not within the scope of the present invention. Although the output voltages driven by differential signal output drivers of the present invention are partial voltages with amplitude between the power supply voltage (Vddq) and ground voltage (Vssq) at the driver end, the voltage may be out of power supply ranges at receiver ends due to power/ground level shifting or coupling noises. We still define such signals as partial voltage signals as soon as the difference of the voltages on the differential signal lines is a partial voltage.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all modifications and changes as fall within the true spirit and scope of the invention.
This application is a continuation-in-part application of previous patent application with a Ser. No. 11/560,846 filed on Nov. 17, 2006. The Ser. No. 11/560,846 application was a continuation-in-part application of previous patent application with a Ser. No. 11/098,991 filed on Apr. 5, 2005 (latter granted as U.S. Pat. No. 7,180,338 on Jan. 31, 2007).
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11560846 | Nov 2006 | US |
| Child | 12029928 | US | |
| Parent | 11098991 | Apr 2005 | US |
| Child | 11560846 | US |
