The present invention relates to output drivers for integrated circuits (IC), and more particularly to low power, high performance output drivers capable of driving multiple-level switching and/or partial-voltage signals.
In this patent application, an “output driver” is defined as the last-stage circuit in an IC that drives output signals from the IC to external components. In most ICs, output drivers are manufactured and designed differently than the other circuitry internal to the IC. In this regard, general purpose drivers internal to an IC are not “output drivers.” A “high performance output driver” is a high performance last-stage circuit that drives high performance switching signals from an IC at a rate of hundreds of thousands of cycles per second or higher. A “pull up transistor” in an output driver is defined as a transistor that couples the output of the output driver to the higher of two reference voltages. A pull up transistor thus “pulls” the output “up” towards the higher reference voltage when the transistor is on. A “pull down transistor” in an output driver that couples the output of the output driver to the lower of two reference voltages. A pull down transistor thus “pulls” the output “down” towards the lower reference voltage when the transistor is on. An “n-channel transistor” is defined as a transistor that uses electrons as the majority charge carrier and includes an NMOS field effect transistor. A “p-channel transistor” is defined as a transistor that uses holes as the majority charge carrier and includes a PMOS field effect transistor. One transistor can comprise many legs of transistors connected in parallel. A “partial-voltage signal” is a signal with quiescent state voltage level lower than the pull up voltage supply of the output driver driving the signal, and higher than the pull down voltage supply of the output driver. “Quiescent state”, which is often called “steady state”, means the state when the output signal remains stable. A “partial voltage interface” is an integrated circuit interface that communicates with partial voltage signals, which is also referred to herein as a “small signal interface.”
Today, IC technologies involve patterning features having dimensions in the nanometer (nm) range, which allows for very fast transistor switching speeds. For example, current art 32 nm logic technologies provide transistors with switching times in the picosecond (ps)—i.e., 10−12 seconds—regime. Consequently, it has become a routine practice to design logic circuits internal to the IC that are capable of executing billions, or even trillions, of operations per second. To fully exploit such fast core circuits require high performance output drivers. Otherwise, input/output (I/O) bandwidth would become the performance bottleneck in high performance systems. It is therefore highly desirable to provide methods to improve the performance of I/O circuits, and in particular output drivers, for integrated circuits.
The performance of output drivers has significant impacts to overall system performance. The most common output drivers used by prior art ICs are CMOS (complementary metal-oxide-semiconductor) drivers. CMOS drivers consume little power at quiescent state, and provide signals that approach the full amplitude of the I/O voltage supply sources. However, noise related switching problems limits CMOS drivers in supporting high performance interfaces. It is therefore highly desirable to provide output drivers that can avoid switching noise problems to support high performance operations.
A common method used to improve the performance of CMOS output drivers is to reduce the amplitude of the output signals by introducing one or more termination resistor(s) to each signal line. The termination resistor is typically connected to a reference voltage (VREF) equal to half (or a fraction) of the I/O voltage supply source. We also use the term “termination voltage” (VTT) when the termination resistor also serves an anti-reflection purpose. The same reference voltage is typically also used for input data sensing. This is called a “high-speed transceiver logic” (HSTL) interface when it is used by high end SRAM (static random access memory). A nearly identical approach used by used by DRAM (dynamic random access memory) is called a “stub series terminated logic” (SSTL) interface. A DRAM “double data rate version 2” (DDR2) SSTL interface operates at between 400 to 800 million bits per second. A DRAM “double data rate version 3” (DDR3) SSTL interface operates between 800 to 1600 million bits per second. A partial voltage interface utilized for logic circuits is called “Gunning Transceiver Logic” (GTL). GTL typically has a voltage swing of between 0.4 volts and 1.2 volts. The maximum signalling frequency for GTL was originally specified to be 100 MHz. However, present day ICs typically use upgraded GTL interfaces (such as GTL+) operating at even higher frequencies. For example, present day Intel microprocessors and chip sets use GTL at a frequency of 1.6 GHz. Another method, similar to GTL, is called “Backplane Transceiver Logic” (BTL) that is commonly used for communication integrated circuits. This type of methods is called “partial voltage interfaces” or “small amplitude interfaces” (SAI) in our discussions because they all use signal amplitudes that are a fraction of full power supply voltages. SAI effectively improved interface performance relative to conventional CMOS interfaces. However, conventional SAI drivers consume power even when they are not switching data, and they still suffer from most of the noise problems common to conventional CMOS drivers. It is therefore highly desirable to provide further improvements in performance relative to conventional SAI while consuming little power at quiescent state.
Wireless devices such as cellular phones have progressed at an explosive pace. Battery powered portable devices always benefit from decreased power consumption. At the same time, the demand for higher performance increases dramatically with each generation of wireless products. For example, cellular phones used to have no or very simple displays; now they commonly implement colored liquid crystal display (LCD) at high resolution. A current art LCD output driver can send out 132 RGB signals (totaling 396 digital-to-analog converter output signals) with 6 bit accuracy (64 levels) switching at around 12 KHZ. Such IC devices require high accuracy, low power, digital-to-analog (D/A) output drivers. Most prior art digital-to-analog converters use operational amplifiers with negative feedback to provide high accuracy output signals, but operational amplifiers typically consume a lot of power and have poor switching speed. U.S. Pat. No. 6,124,997 discloses an LCD driver design that does not use operational amplifiers; instead, the method involves pre-charging each output line before driving new data. The pre-charge operation will consume power whether the data is changed or not. Because Tsuchi only uses pull down drivers, the method is sensitive to noises that cause the output signal to drop below targeted voltages. It is therefore highly desirable to provide low power output drivers that can support high accuracy switching signals.
U.S. Pat. No. 4,816,705 (the '705 patent) discloses methods to make the output voltages of Bi-MIS logic circuits almost equal to that of the voltage supply sources. These drivers drive internal signals so they are not output drivers. The non-inverting buffers disclosed in the '705 patent use n-channel pull up transistors and p-channel pull down transistors as the biasing circuits for the drivers to increase the range of output voltages; but these transistors are not used to drive the outputs. The '705 patent also discloses methods to make the output voltages of Bi-MIS logic circuits almost equal to that of the voltage supply sources. The patent discloses special kinds of output drivers that support multiple-level switching partial-voltage signals.
U.S. Pat. No. 6,958,632 (the '632 patent) discloses voltage follower buffers to reduce power line noise induced timing uncertainty, called “jitter”, on internal signal buffers such as clock buffers. The output of the buffer is driven by an n-channel pull up transistor that can pull the output up to Vcc−Vtn (where Vtn is the threshold voltage of the n-channel transistor), a p-channel pull down transistor that can pull the output up to Vss+Vtp (where Vtp is the threshold voltage of the p-channel transistor), and a CMOS buffer that drives the output to full scale voltages Vcc or Vss. These drivers are internal signal buffers, not output drivers. The '632 patent also discloses methods to make the output voltages of the buffers equal to that of the voltage supply sources instead of multiple-level switching partial-voltage signals.
U.S. Pat. No. 6,560,290 discloses CMOS output drivers and on-chip termination for high speed data communication such as for an Ethernet transmitter/receiver. N-channel pull up transistors and p-channel pull down transistors are used in the on-chip termination circuits but not in the output drivers. The function of a termination circuit is to imitate the functions of resistors for impedance matching purposes, and to hold the steady-state voltage of the signal bus near half that of the supply voltage.
U.S. Pat. No. 6,384,658 by Jex discloses circuits to generate non-inverting and inverting clock signals with balanced timing. Those circuits are clock signal generators, not output drivers. In Jex, n-channel pull up transistors and p-channel pull down transistors are used in the input stages of the clock circuits in order to balance the timing of the two inverted output signals. These transistors have no relationship to output drivers.
U.S. Pat. No. 6,091,656 discloses a method to generate sub-voltage source for conventional art CMOS drivers. N-channel pull up transistors and p-channel pull down transistors are used to generate the sub-voltage sources instead of providing driving currents for the drivers. The drivers are also not necessarily output drivers.
This patent application provides further understandings on the termination circuits and output drivers of the present invention.
One of the primary objectives of the preferred embodiments is, therefore, to provide output drivers that reduce power consumption at quiescent state. Another primary objective of the preferred embodiments is to provide output drivers that can switch between multiple levels of high accuracy output voltages while consuming less power. Another objective is to support small amplitude interface protocols without using termination resistors. Another objective is to provide termination circuits working with output drivers of the present invention to consume less power. Another objective is to reduce the cost of output drivers that drive memory interfaces such as HSTL or SSTL interfaces. Another objective is to improve the fan out of partial voltage output drivers. These and other objectives are achieved by using output drivers comprising n-channel pull up transistors and/or p-channel pull down transistors biased with proper gate voltages, and/or using RC termination circuits.
While the novel features of the invention are set forth with particularly in the appended claims, the invention, both as to organization and content, will be better understood and appreciated, along with other objects and features thereof, from the following detailed description taken in conjunction with the drawings.
a, b) illustrate the structures and operational principles of known CMOS drivers;
a, b) illustrate the structures and operational principles of known SAI drivers;
a, b) illustrate the structures and operational principles of a basic output driver of the present invention;
c) shows the current-voltage relationship of the output driver shown in
d-i) are schematic diagrams showing various output driver designs of the present invention;
a-f) are schematic diagrams showing different gate voltage generation circuits to support output drivers of the present invention;
a-c) illustrate methods to use native transistors in output drivers of the present invention;
a-d) are examples of cost efficient output drivers of the present invention;
a-b) illustrate the structures and operation principles of known differential signal drivers;
a-d) are examples of differential signal drivers of the present invention;
a-e) show examples of prior art partial voltage output drivers driving transmission lines terminated with resistors;
a-j) show examples of drivers and termination circuits of the present invention; and
a-k) illustrate various implementations of RC termination circuits supporting output drivers of the present invention.
The operation principles of prior art output drivers are first discussed to facilitate a clear understanding of the present invention.
a) is a schematic diagram showing the basic elements of a prior art CMOS output driver (DR1). This prior art output driver (DR1) comprises a p-channel pull up transistor (MP) and an n-channel pull down transistor (MN). One transistor shown in a schematic diagram can comprise many legs of transistors connected in parallel.
For the output driver (DR1) in
Although the structure of this CMOS output driver (DR1) may appear to be a simple CMOS inverter, the requirement that the output driver supply large electrical currents to heavy electrical loads necessitates special designs for these output drivers. Consequently, the design methods and the structures of CMOS output drivers are typically different from those of internal drivers.
b) shows example timing control waveforms to illustrate the operational principles of the prior art CMOS driver in
For a double data rate (DDR) protocol, the rising edge of the complementary clock signal (CK#) at time T5 triggers the output driver to send out another data.
We can turn off this output driver (DR1) by setting Vgp=Vddq and Vgn=Vssq so that the output driver is in a high impedance state to allow other output drivers (DR2, DR3) to drive the external signal line (Q).
The major advantages for prior art CMOS drivers are that they consume little power at quiescent state, and they provide nearly full scale voltage outputs from the voltage supply sources (e.g., Vddq, Vssq) that represent digital signals. These advantages make CMOS output drivers the most popular output drivers for integrated circuits. However, CMOS output drivers typically consume large amounts of power and cause severe noise problems during switching. The switching noise problems and the “flow through current prevention delay time” limit the applications of CMOS output drivers in high performance applications.
a, b) illustrate the most popular prior art method used to improve the performance of CMOS output drivers. This method employs a “high-speed transceiver logic” (HSTL) interface when used as a high end SRAM (static random access memory) interface. A nearly identical method employs a “stub series terminated logic” (SSTL) interface when used as a DRAM (dynamic random access memory) interface. Similar methods applied in logic circuitry are referred to as “Gunning Transceiver Logic” (GTL) or “Backplane Transceiver Logic” (BTL), which are commonly used for microprocessors, graphic controller, chipsets, communication chips or other integrated circuits. We will call those types of methods “small amplitude interfaces” (SAI) in our discussions. The major difference between the CMOS interface shown in
b) shows example timing waveforms to illustrate the operation principles of SAI in comparison with the traditional CMOS interface waveforms in
Similar to the example in
We can turn off this output driver (DR1) by setting Vgp=Vddq and Vgn=Vssq so that the output driver is in a high impedance state to allow other output drivers (DR2, DR3) to drive Q′.
SAI methods improve interface performance by reducing the amplitude of switching output signals. That is achieved by using a termination resistor to serve as a voltage divider; however, unlike the traditional CMOS output driver, the SAI circuits consume power at quiescent state. Typically, a SAI driver needs to provide a steady-state current of about 15 milli-Amps across the termination resistor. A 72-signal data bus will consume about 1 Amp of current even when there is no switching activity. This is a tremendous waste of energy, particularly for portable applications that are battery powered. In addition, SAI drivers still suffer from the same switching noise problems and the “flow through current prevention delay time” as CMOS output drivers. It is highly desirable to provide an output driver that has the advantages of small amplitude switching while removing the noise and power problems.
a) is a schematic diagram showing simplified structures for an output driver (DRj1) of the preferred embodiments of the present invention. This output driver (DRj1) also comprises a p-channel transistor (MPj) and an n-channel transistor (MNj). However, unlike the prior art CMOS output driver, the p-channel transistor (MPj) is configured as a pull down transistor and the n-channel transistor (MNj) is configured as a pull up transistor. The preferred embodiments of the present invention thus inverts the roles of the driving transistors in traditional CMOS output drivers by using n-channel transistors as pull up transistors and by using p-channel transistors as pull down transistors to drive external signals.
In
In this configuration, the channel current of the pull up n-channel transistor (MNj) is controlled by its gate voltage Vgnj relative to the output voltage (Vqj). When (Vgnj−Vqj) is smaller than the threshold voltage (Vtn) of the n-channel transistor (MNj), the transistor is turned off. When (Vgnj−Vqj) is larger than Vtn, the channel current (Isn) of the n-channel pull up transistor (MNj) can be described by a textbook equation as
Isn=Kn (Wn/Ln) (Vgnj−Vqj−Vtn)2˜Kn (Wn/Ln) (Vqtn−Vqj)2 (EQ1)
where (Wn/Ln) is the width/length ratio of the transistor, and Kn is a parameter dependent on electron mobility. In other words, the n-channel pull up transistor (MNj) will pull up the output voltage Vqj toward the target voltage Vqtn if its gate voltage is set as Vgnj˜Vqtn+Vtn. The driving channel current (Isn) increases rapidly as (Vqtn−Vqj) increases, but the driving current is very small when output voltage Vqj is pulled near the target voltage Vqtn. Consequently, this circuit configuration has an automatic negative feedback mechanism.
Similarly, the current driving capability of the pull down p-channel transistor (MPj) is controlled by its gate voltage Vgpj relative to the output voltage (Vqj). When (Vqj−Vgpj) is smaller than the amplitude of the threshold voltage (Vtp) of the p-channel transistor (MPj), the transistor is turned off. When (Vqj−Vgpj) is larger than Vtp, the channel current (Isp) of the p-channel pull down transistor (MPj) can be described by a textbook equation as
Isp=Kp (Wp/Lp) (Vqj−Vgpj−Vtp)2˜Kp (Wp/Lp) (Vqj−Vqtp)2 (EQ2)
where (Wp/Lp) is the width/length ratio of the transistor, and Kp is a parameter dependent on hole mobility. In other words, the p-channel pull down transistor (MPj) will pull down the output voltage Vqj toward the target voltage Vqtp if its gate voltage is set as Vgpj˜Vqtp−Vtp. The driving channel current increases rapidly with (Vqj−Vqtp) but the driving current is very small when output voltage Vqj is pulled near the target voltage Vqtp. Again, this circuit configuration has an automatic negative feedback mechanism.
For many applications according to the preferred embodiments, the target voltage (Vqtn) for the n-channel pull up transistor and the target voltage (Vqtp) for the p-channel pull down transistor are set to be about the same, at about Vqtp˜Vqtn˜Vqt. However, there are exceptions.
c) shows the current-voltage relationship of the output driver (DRj1) when Vqtp˜Vqtn˜Vqt according to Equations 1 and 2. The actual current-voltage (I-V) relationships of modern transistors are more complicated than those simplified equations (EQ1, EQ2). For example, the threshold voltages (Vtp, Vtn) are also complex functions of bias voltages due to body effects. Nevertheless, the general principles reflected in equations 1 and 2 and on
Known reference voltage generators have used similar negative feedback mechanisms to generate reference voltages at fixed levels. A typical example would be the bit line pre-charge voltage generator for memory devices as discussed in U.S. Pat. No. 6,216,246. Reference voltage generators are designed to drive constant or near-constant target voltages; the output voltages of reference voltage generators may be adjustable, but reference voltage generators are not designed to support frequent switching output voltages. The present invention discloses methods to use n-channel pull up transistors in combination with p-channel pull down transistors to drive high performance synchronized switching interface signals so that the circuit structures and designs are optimized to reduce switching noise and to improve switching performance.
Based on the above principles, the output driver (DRj1) shown in
b) shows exemplary timing waveforms to illustrate the operational principles of the output driver of
Similar to the example in
The above example shows that output drivers of the preferred embodiments can drive output signals at voltage levels fully compatible with existing SAI systems while achieving better performance and consuming less power.
The output driver (DRj1) of the preferred embodiments can be turned off by setting Vgpj=Vddq and Vgnj=Vssq so that the output driver is in a high impedance state to allow other output drivers (DRj2, DRj3) to drive Qj. Another method for placing the output driver (DRj1) into a high impedance state is to set Vgpj=Vph and Vgnj=Vns. Under these conditions, the output driver allows other drivers to drive Qj while at the same time tending to confine the output voltage (Vqj) to within SAI ranges (between Voh and Vos) even when no driver is activated. This is an example of the situation when the target voltage for the n-channel pull up transistor is different than the target voltage for the p-channel pull down transistor.
The above example shows that the output driver of the present invention has the following advantages over prior art SAI drivers:
(1) It can drive output voltages that are fully compatible with SAI standards (such as the HSTL, SSTL, GTL, or BTL interface standards) without using a termination resistor, thereby achieving significant power savings.
(2) The gate voltages of the output driver of the preferred embodiments also swing within relatively small amplitudes, making it possible to achieve faster switching times.
(3) The gate voltages switch in the same direction as the output voltage so that capacitor coupling noise problems are reduced.
(4) The pull up transistor and the pull down transistor of an output driver of the preferred embodiments are typically not turned on simultaneously at normal operations. Therefore, a “flow through current prevention delay time” is not required and accordingly the switching time is faster, and the control circuit is simpler.
(5) The output driver of the preferred embodiments has strong driving power when the output voltage is far from the target voltage, while the driving power decreases as the output voltage approaches the target voltage. This automatic adjustment in driving power minimizes the switching noise while at the same time achieving short switching times and high switching frequency.
(6) The output driver of the preferred embodiments can be biased into a high impedance state while at the same time stabilizing the output voltage within the SAI range without using a termination resistor.
Although some of the output drivers of the preferred embodiments generate smaller drive currents than some alternative output drivers of equivalent size (due to smaller gate to source bias voltages and body effects), the drive currents of the preferred embodiments can be improved by using larger or faster transistors, or alternatively by reducing the threshold voltages of the transistors.
While the preferred embodiments have been illustrated and described herein, other straightforward modifications and changes will be evident to those skilled in the art. The basic structure for an output driver of the present invention comprises an n-channel pull up transistor and/or a p-channel pull down transistor. A circuit designer can use many kinds of equivalent circuits to build the same output driver. We will discuss a few examples in the following sections. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein.
d) shows a modification to the previously described output driver in which a series termination resistor (Rq) or other current limiting device is placed between the internal signal line (Qd) of an output driver and an external signal line (Qj). Utilized in this manner, such a series termination resistor (Rq) or other type of current limiting device can reduce signal reflections on the external signal line (Qj). The series termination resistor (Rq) or other current limiting device can be integrated into the IC chip or implemented as a discrete circuit component. For example, DDR (double data rate) DRAMs utilize discrete series termination resistors while DDR2 and DDR3 DRAMs provide the option to implement the series termination resistors as part of the monolithic DRAM IC chip.
e) shows another type of current limiting method for output drivers of the preferred embodiments. The source electrode of the n-channel pull up transistor (MNj) is connected to a current source (Ih) that is connected to a power line at voltage Vddq. The source electrode of the p-channel pull down transistor (MPj) is also connected to another current source (Ib) that is connected to power line at voltage Vssq, where Vssq<Vddq. This modification is designed to avoid current overshoot. This method is effective in reducing switching noise, especially for inductance induced noise. Replacing the current sources (Ih, Ib) with resistors or other types of current limiting devices can provide a similar effect.
e) represents current sources as symbols instead of as actual transistor level schematics. A “current source” here includes any circuit element that provides for current control including, but not limited to, (1) a transistor that is biased into saturation conditions, (2) a current limiting device such as a simple resistor, and (3) a much more complicated circuit. The current sources referred to in the preferred embodiments also do not need to be ideal current sources. For example, as used herein, current sources include current limiting devices. The most common circuits used as current sources are “current mirrors,” which are well known to circuit designers. Methods to design current sources are well known to most circuit designers and will not be described in further detail here. For simplicity, current limiting devices are represented generically herein by an arrow in a circle as Ih or Ib in
For the examples described in
A major advantage of the output driver in
It is also possible to combine multiple methods such as those illustrated in
i) shows yet another design variation. This circuit uses a driver (DRvoh) of the preferred embodiments configured to drive an internal line (Qvoh) at upper SAI voltage (Voh). This line (Qvoh) is connected to the source electrode(s) of one or a plurality of p-channel pull up transistors (MPw1, MPw2, MPw3). It also uses another driver (DRvos) of the preferred embodiments configured to drive an internal line (Qvos) at lower SAI voltage (Vos). This line (Qvos) is connected to the source electrode(s) of one or a plurality of n-channel pull down transistors (MNw1, MNw2, MNw3). The drain electrode(s) of p-channel pull up transistors (MPw1, MPw2, MPw3) and the drain electrode(s) of n-channel pull down transistors (MNw1, MNw2, MNw3) are connected to one or a plurality of external signal lines (Qj1, Qj2, Qj3) as shown in
The output driver of the preferred embodiments of the present invention utilizes gate voltages about one threshold voltage away from target output voltages. The transistor threshold voltages (Vtn, Vtp) can be a complex function of, e.g., manufacturing procedures, substrate voltages, temperature, and device geometry. It is therefore good practice to provide adequate support circuitry to generate appropriate gate voltages for the output drivers of the preferred embodiments of the present invention.
Iin=Kn (Wnm/Lnm) (Vgnj−Vdj−Vtn)2 (EQ3)
where (Wnm/Lnm) is the width/length ratio of the n-channel matching transistor (MNm), and Kn is a parameter related to electron mobility. If there is a good match between MNm and MNj, the parameter Kn in EQ1 and in EQ3 should be the same, and their threshold voltages should therefore be the same. When the current (Iin) of the current source (In) is small, (Vgnj−Vdj)˜Vtn and the gate bias voltage is approximately one threshold voltage above the target voltage (Vdj). Using EQ1 and EQ3, when Vqj>Vdj, the driver current (Isn) of the n-channel pull up transistor can be approximated as
Isn˜Iin[(Wn/Ln)/(Wnm/Lnm)](Vqj−Vdj)2 (EQ4),
meaning that the n-channel pull up transistor (MNj) will try to pull Vqj toward Vdj, and that the channel current of the n-channel pull up transistor is proportional to the current (Iin) of the current source (In) in the gate voltage generation circuit (GCj).
Similarly, the gate electrode of the p-channel pull down transistor (MPj) is connected to the gate electrode and the source electrode of a matching p-channel transistor (MPm), and to one terminal of a current source (Ip). The other terminal of the current source (Ip) is connected to a lower voltage supply line at voltage Vss, where Vss<Vdd. Vss can be the same as Vssq; it also can be different. The drain electrode of the matching transistor (MPm) is connected to the input line (Dj) as shown in
Iip=Kp (Wpm/Lpm) (Vdj−Vgpj−Vtp)2 (EQ5)
where (Wpm/Lpm) is the width/length ratio of the p-channel matching transistor (MPm), and Kp is a parameter related to hole mobility. If there is a good match between MPm and MPj, the parameter Kp in EQ2 and EQ5 should be identical, and they should have approximately the same threshold voltage. When the current (Iip) of the current source (Ip) is small, (Vdj−Vgpj)˜Vtp and the gate bias voltage is approximately one threshold voltage below the target voltage (Vdj). Using EQ2 and EQ5, when Vdj>Vqj, the driver current (Isp) of the p-channel pull down transistor can be approximated as
Isp˜Iip [(Wp/Lp)/(Wpm/Lpm)](Vdj−Vqj)2 (EQ6),
meaning that the p-channel pull down transistor will try to pull Vqj toward Vdj, and the channel current of the p-channel pull down resistor (MPj) is proportional to the current (Iip) of the current source (Ip) in the gate voltage generation circuit (GCj).
If the two current sources (In, Ip) provide the same currents (Iin=Iip), and if [(Wn/Ln)/(Wnm/Lnm)]=[(Wp/Lp)/(Wpm/Lpm)], then at quiescent state Vqj˜Vdj. In other words, the output voltage (Vqj) will automatically follow the input voltage (Vdj) when the gate voltage generator (GCj) in
b) shows another circuit example of the preferred embodiments of the present invention that has the same gate voltage generation circuits (CGj) as those in
As shown by EQ3-EQ6, the driving power as well as the quiescent state leakage current of the driver in
While specific embodiments of the invention have been illustrated and described herein, other modifications and changes will occur to those skilled in the art. For example, the current sources in the above examples can be replaced with other current limiting circuits such as resistors and the circuits will still work. The currents of the current sources certainly can be changed using analog methods instead of using switches. It is therefore to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed in this patent disclosure.
d) shows one example of design variation for a circuit that is nearly identical to the circuit in
e) shows another example of a circuit that is nearly identical to the circuit in
Multiple activated output drivers of the present invention can drive the same external load; it is even possible to have other types of output drivers driving the same external load in parallel.
The examples in
Prior art output drivers typically use enhancement mode transistors with high threshold voltages to reduce leakage currents. The output drivers of the preferred embodiments of the present invention have a natural feedback mechanism to reduce leakage current. To achieve better driving power for the same size transistors, it is often desirable to use transistors with lower threshold voltages, native transistors, or even depletion mode transistors for output drivers of the preferred embodiments of the present invention. Many current IC manufacturing technologies make available native transistors. Alternatively, additional threshold adjustment masking steps can be added to current manufacturing technologies to manufacture transistors with desired threshold voltages for applications of the preferred embodiments present invention. As such techniques are well known, they are not further described herein. Another alternative is to use floating gate transistors in the output driver because the threshold voltages of such floating gate transistors are programmable.
Many current IC manufacturing technologies provide options for n-channel native transistors but few of them provide p-channel native transistors.
Due to body effects, the effective threshold voltage of a native transistor may vary from 0 volts at different operations conditions.
Prior art SAI drivers can only switch between two voltage levels (Voh and Vos) to represent one binary data per phase. The output drivers of the preferred embodiments of the present invention have the accuracy to switch between multiple levels of analog voltages. They can easily support four-level data format to represent two binary bits per phase, or 16-level data format to represent 4 binary bits per phase. In other words, the output drivers of the preferred embodiments of the present invention can improve data bandwidth while running at the same clock rate. When designed carefully, an output driver of the preferred embodiments of the present invention can support the functions of a high speed digital to analog (D/A) converter, providing output voltages switching between hundreds or even thousands of analog levels. Prior art high performance D/A converters consume significant power. A D/A converter equipped with an analog switching output driver of the preferred embodiments of the present invention will consume very little power, but can operate at a high switching rate while at the same time providing accurate outputs.
Output drivers of the preferred embodiments of the present invention can easily support 4-level switching at 500 MHz clock rate to replace HSTL or SSTL interfaces. With careful design, 8-level or 16-level high speed switching is also possible.
Liquid crystal display (LCD) output drivers come with many configurations. For example, an LCD output driver can send out 132 RGB signals (total 396 digital-to-analogy converter output signals) with 6 bit accuracy (64 levels) switching at a relatively low clock rate around 12 kHz. For battery powered portable devices, power consumption is a major concern. Most prior art digital-to-analog converters use operational amplifiers with negative feedback to provide high accuracy output signals, but operational amplifiers typically consume a lot of power and have poor switching speed. Tsuchi disclosed an LCD driver design in US. Pat. No. 6,124,997 that does not use operational amplifiers; the method requires pre-charging each output line before driving the next piece of data. The pre-charge operation will consume power whether the data is changed or not. Since Tsuchi only uses pull down drivers, the method is sensitive to noises that cause the output signal to drop below targeted voltages. Output drivers of the preferred embodiments of the present invention have much better accuracy; they can hold the data at targeted value with little power; and they consume little or no power when the data is not changed. LCD drivers using output drivers of the preferred embodiments of the present invention are therefore better than prior art products.
High resolution graphic displays output 1024×900 pixels of RGB (red-green-blue) data with 8 bit resolution (256 levels) on each data. That requires outputting ˜60 M 256-level data per second. Output drivers of the preferred embodiments of the present invention can support both the accuracy and the data rate.
The most popular high performance interfaces for current art memory devices are “small amplitude interfaces” (SAI), including the HSTL interface commonly used by SRAM devices and the SSTL interface commonly used by DRAM devices. As discussed previously, the output drivers of the preferred embodiments of the present invention can be designed to be fully compatible with existing SAI with or without using termination resistors, thereby achieving lower power consumption at higher speed. For many memory devices, cost efficiency is considered more important than power saving. The sizes of the output drivers discussed previously are about the same as prior art output drivers. It is therefore desirable to provide cost saving methods for SAI memory devices.
a-d) illustrate cost saving structures/methods of the preferred embodiments of the present invention using single-transistor output drivers driving against complementary termination transistors. The applications for these single-transistor output drivers of the preferred embodiments of the present invention encompass partial-voltage memory interface (PVMI) circuits. PVMI circuits use partial-voltages that are between the pull up voltage supply source (Vddq) and the pull down voltage supply source (Vssq) of the output drivers to represent data values on IC external signals in order to support memory input/output operations. Typical examples of PVMI are the HSTL interface for SRAM and the SSTL interface for DRAM. A single-transistor output driver uses one transistor to provide the majority of the switching current that drives the value of an IC external PVMI signal according to the value of its switching gate voltage. A single-transistor output driver can have many supporting circuits such as bias circuits, timing circuits, control circuits, electro-static protection circuits, and so on, but the majority of the output driving power is provided by one transistor. Such “single-transistor” certainly can comprise many legs of transistors connected in parallel to function as “one” transistor in order to provide the driving current. A complementary termination transistor (CTT) provides the driving power against single-transistor output driver(s). When the single-transistor output drivers are pull up transistors, the CTT would be a p-channel pull down termination transistor. When the single-transistor drivers are pull down transistors, the CTT would be an n-channel pull up termination transistor. An n-channel pull up termination transistor is defined as an n-channel pull up transistor that is configured to hold the steady-state voltage of an IC external PVMI signal near a pre-defined partial-voltage. Unlike the n-channel pull up transistors used in an output driver, the gate voltage of an n-channel pull up termination transistor typically is not switched when the output signal is switched. The gate voltage of termination transistor is typically held at an approximately constant level during signal switching events; said constant level may have variations due to the influence of noise. A p-channel pull down termination transistor is defined as a p-channel pull down transistor that is configured to hold the steady-state voltage of an IC external PVMI signal near a pre-defined partial-voltage. Unlike the p-channel pull down transistors used in an output driver, the gate voltage of a p-channel pull down termination transistor typically is not switched when the output signal is switched. The gate voltage of termination transistors is typically held at an approximately constant level during signal switching events; said constant level may have variations due to the influence of noise.
a) is a schematic diagram showing simplified structures for output drivers of the preferred embodiments of the present invention that are designed to achieve low cost at high performance. To achieve optimum cost efficiency, each output driver is simplified to be a single-transistor driver (i.e., ignoring the termination transistor). For the example in
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The present invention is not limited to particular implementation discussed in the exemplary embodiments. For example,
For the example in
For the example in
For the example in
The output drivers of the preferred embodiments of the present invention, including but not limited to the examples illustrated in
The numbers listed in table 2 are exemplary only; the actual characteristics will change with based upon the application.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The present invention is not limited to particular implementation discussed in specific examples. For example, the immediately above examples are all single-ended signal drivers while output drivers of the present invention are excellent in driving differential signals.
Differential signaling is a method of transmitting information electrically using two complementary signals sent on two separated conductors with matched properties.
The most important advantage of differential signaling is noise tolerance. Differential sense amplifiers (DSA) are typically designed to have excellent common mode noise rejection. Differential signal transfer systems are therefore capable of transferring data under noisy conditions if the major noise sources are common mode noises such as coupling noises or shifting in power/ground voltages. However, differential signal transfer systems are typically sensitive to resistance/inductance on the signal lines (Q+, Q−) or differential mode noises; they also have problems in driving signal lines with heavy capacitance loading because of the constraint in driving current.
Output drivers of the preferred embodiments of the present invention are excellent at driving differential signals.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The present invention is not limited to particular implementations discussed in specific examples. There are wide varieties of methods to design differential signal output drivers. For example,
Using output drivers of the preferred embodiments of the present invention, it is possible to remove the loading resistor (RL) while the voltages on the differential signal lines (Q+, Q−) still meet the requirements of differential signal interface specifications.
Differential signal output drivers of the preferred embodiments of the present invention have many advantages over typical differential signal output drivers. The driving power of typical differential signal output drivers are limited by the loading resistor (RL) because IL*RL equals the voltage drop limited by the specification of signal transfer protocols. This limitation in driving power limits the performance of prior differential signal drivers. The output voltages of the drivers of the preferred embodiments of the present invention are weakly dependent on RL so the driving capability can be scaled to achieve better performance. Typical current mode differential signal output drivers consume power even when the outputs are not switching. The differential output drivers of the preferred embodiments of the present invention provide the option to remove loading resistors to save power. Typical differential signal output drivers can not support large fan-out configurations that require multiple termination resistors. A differential output driver of the preferred embodiments of the present invention can support large fan-out because its output voltage is not sensitive to the size of termination resistors. Likewise, typical differential signal output drivers are sensitive to parasitic resistance or leakage current on the signal lines, while differential signal output drivers of the preferred embodiments of the present invention are not sensitive to parasitic resistance or leakage current. Differential signal output drivers of the preferred embodiments of the present invention have the same common mode noise rejection as typical different output drivers, while the preferred embodiments of the present invention provide better tolerance to differential noises.
There are wide varieties of applications for differential signal output drivers of the present invention, including but not limited to the examples shown in
The Stub Series Terminated Logic (SSTL) interfaces commonly used for DRAM interfaces have gone through three generations of evolution. The SSTL2 standard is commonly used for double data rate version 1 (DDRI) DRAM's with power supply voltage at 2.5 volts. The SSTL—18 standard is commonly used for double data rate version 2 (DDRII) DRAM's with power supply voltage at 1.8 volts. The SSTL—15 standard is commonly used for double data rate version 3 (DDR3) DRAM's with power supply voltage at 1.5 volts. As discussed previously, for SSTL interfaces the data and control signals are single-ended signals centered at a reference voltage at half of the power supply voltage. However, the clock signals for SSTL interface are differential signals. Drivers of the preferred embodiments of the present invention are not only ideal to drive SSTL data/control signals but also ideal to drive SSTL clock signals. These and future generations of SSTL interfaces can achieve significant power savings and performance improvements using output drivers of the preferred embodiments of the present invention.
The “Serial Advanced Technology Attachment” (SATA) computer bus, is a storage-interface for connecting host bus adapters to mass storage devices such as hard disk drives and optical drives. The SATA host adapter is integrated into almost all modern consumer laptop computers and desktop motherboards. The first generation of SATA interface supports 1.5 billion bits per second (GBPS), the second generation SATA interface supports 3 GBPS, and the third generation supports 6 GBPS.
The “Peripheral Component Interconnect Express” (PCIe) interface is a computer expansion card standard. The PCIe interface is used in consumer, server, and industrial applications, as a motherboard-level interconnect (to link motherboard-mounted peripherals) and as an expansion card interface for add-in boards. A key difference between PCIe and earlier buses is a topology based on point-to-point serial links, rather than a shared parallel-bus architecture.
The Low Voltage Differential Signal (LVDS) interfaces are developed for signal transfers at a distance up to 30 feet. The original generation of LVDS supports one-to-one signal transfers. Latter generations of LVDS support many-to-many data transfers. The LVDS interfaces are widely used for applications such as graphic interfaces for large flat panel display, automobile signal transfers, and communication back panel signal transfers. Output drivers of the preferred embodiments of the present invention can save power, increase fan-in/fan-out and improve performance of LVDS interface devices.
The Mobile Industry Processor Interface (MIPI) and the Mobile Display Digital Interface (MDDI) are similar interface protocols developed for mobile devices. The major purpose for MIPI/MDDI interfaces is to simplify routing for circuit boards used for mobile devices such as cellular phones. Interface signals between different IC chips used by mobile devices are serialized by the drivers then de-serialized by the receivers. The operational principles of MIPI/MDDI interfaces are similar to LVDS while they typically support short distance signal transfers. Power saving is certainly one of the most important design considerations for mobile devices. Differential signal output drivers of the preferred embodiments of the present invention can help in saving power while also improving performance for the MIPI/MDDI output drivers.
A differential signal output driver, by definition, is the last-stage circuit in an IC that provide the majority of the current driving force (while turned on) to drive a pair of external differential signals. Differential signal output drivers of the preferred embodiments of the present invention drive switching partial voltages to external differential signal lines. Although the output voltages driven by differential signal output drivers of the preferred embodiments of the present invention are partial voltages with amplitude between the power supply voltage (Vddq) and ground voltage (Vssq) at the driver end, the voltage may be out of power supply ranges at receiver ends due to power/ground level shifting or coupling noises. For purposes of the present invention, such signals are still partial voltage signals as long as the difference of the voltages on the differential signal lines is a partial voltage.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The scope of the present invention is not limited by specific examples.
Typical output drivers rely on termination resistors to generate partial voltage signals. Output drivers of the preferred embodiments of the present invention can support the same signal voltage levels following HSTL, SSTL, GTL, BTL, SATA, PCIe, LVDS, MIPI, MDDI, or other standards without using termination resistors, thereby achieving better performance while consuming less power. Driving without termination circuits by using output drivers of the present invention works very well when the signal lines are short. However, when the signal line is long, drivers of the preferred embodiments of the present invention may need termination circuits to reduce reflection induced signal distortion. It is well known to the art of circuit design that when the propagation delay time along an electrical line is comparable to the rise/fall time of the electrical signals driven on it, the electrical line behaves as a transmission line and electrical signals behave as waves. The reflection of the signal waveform near the end of a transmission line can cause significant signal distortion. It is also well known to the art that termination circuits with impedance equivalent to the characteristic impedance (Zo) of the transmission line can reduce reflection effects.
a) is a simplified symbolic view showing a typical output driver (CDV) driving a signal (QDD) on a transmission line (TL1) that has characteristic impedance Zo. For simplicity, the output driver (CDV) in
Typical small signal output drivers have problems driving more than one transmission lines.
Commonly used differential output drivers also have a similar fan out problem.
The last stage transistors in known output drivers often operate in the saturation region at fixed gate-to-source voltage. That means the driving strength of such output drivers remain about the same when the load is changed. To solve the fan out problem, it has proved necessary in the past to increase the size of (or use multiple of) these output drivers to drive multiple transmission lines. For example, one could use two output drivers to drive two transmission lines, or use four output drivers to drive four transmission lines.
The last stage transistors in the output drivers of the preferred embodiments of the present invention are n-channel pull up transistor(s) and/or p-channel pull down transistor(s). Those transistors typically follow the square rules shown in EQ1 and/or EQ2. In other words, output drivers of the preferred embodiments of the present invention will automatically increase driving current to approach target voltage amplitude when the load changes. Therefore, output drivers of the preferred embodiments of the present invention are capable of solving the fan out problem.
a) is a simplified symbolic view showing an output driver (JDV) of the present invention driving the same signal (QDD), transmission line (TL1), and termination resistor (RR1) as those in
Similar principles are applicable to differential output drivers of the preferred embodiments of the present invention.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. The scope of the present invention is not limited by specific examples. The simplified examples in
The circuits shown in
The numbers listed in Table 4 and Table 5 are simplified examples. The exact numbers of course vary in different applications.
An RC termination circuit of the preferred embodiments of the present invention, by definition, is (1) an anti-refection circuit, (2) an equivalent circuit with impedance near the characteristic impedance (Zo) of the transmission line at specified operation frequencies of target small signal interface, and (3)an equivalent circuit with high impedance at low frequencies. Examples of RC termination circuits are shown by the symbolic views in
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. It is to be understood that there are many other possible modifications and implementations so that the scope of the invention is not limited by the specific embodiments discussed herein. An RC termination circuit of the preferred embodiments of the present invention can be implemented by a combination of discrete components, integrated into packaged components, embedded in printed circuit boards, or implemented as on-chip circuits inside integrated chips.
Using the technology described herein, output drivers have been implemented on prototype integrated circuits to support DDR2 SSTL interface operations of DRAM registered dual in line memory modules (RDIMM). The prototype comprises 28 single-ended output drivers for driving DDR2 address and control signals; each output driver drives two termination circuits in a configuration illustrated by
Output drivers of the present invention provide significant advantages over known output drivers in propagation delay time, fan out, and power consumption. Preferably, the output drivers of the present invention have a propagation delay less than 5 nanoseconds, more preferably less than 1 nanosecond, and most preferably less than 0.1 nanosecond. Preferably the output drivers of the present invention to drive one, two, four, or more termination circuits simultaneously. Preferably the output drivers of the present invention consume quiescent current less than 1000 microamperes, more preferably less than 100 microamperes, even more preferably less than 10 microamperes, and most preferable less than 1 microampere, or smaller.
While specific embodiments of the invention have been illustrated and described herein, it is realized that other modifications and changes will occur to those skilled in the art. It is therefore to be understood that the appended claims are intended to cover all modifications and changes as fall within the true spirit and scope of the invention.