Patent Application
20070058309
1. Field of the Invention
The present invention relates to electrical and electronic circuits and systems. More specifically, the present invention relates to microwave switches.
2. Description of the Related Art
Microwave switches are used in a wide variety of applications such as communications and active phased array radar systems. For example, switches may be used to control the direction of a radio frequency (RF) or microwave signal or to provide phase and amplitude control functions in a transmit/receive (T/R) module.
Silicon-germanium (SiGe) technology permits the integration of advanced MMICs, low power VLSI digital electronics, and low frequency analog circuits in a single high yield process. The availability of several high performance microwave passive and active devices on the same wafer, including SiGe HBTs, MOS FETs, PINs, and Varactors, etc., render the SiGe technology a new and exciting paradigm for innovative circuit designs suitable for the realization of “system-on-chip” circuits.
In conventional microwave circuits, switches are commonly implemented using SiGe PIN diodes. However, PIN devices consume DC power and need complex bias supply circuits, both of which negatively impact system efficiency, prime power, size and thereby cost.
Switches implemented using SiGe NMOS devices consume little or no DC power, but are typically limited in bandwidth. For example, prior silicon (Si) based (0.18 um NMOS) RF switching devices offered by the IBM 7-HP process have a maximum useful frequency of less than 5 GHz. Above this frequency, unwanted parasitics associated with the NMOS device become a significant factor in rapidly detracting the switch performance.
Hence, a need exists in the art for an improved microwave switch offering lower power consumption and increased frequency range.
The need in the art is addressed by the switching circuit of the present invention. The novel switching circuit includes an active device and a first circuit for providing a reactive inductive load in shunt with the active device. In an illustrative embodiment, the first circuit is implemented using a transmission line coupled between an output of the active device and ground, in parallel with the device, to minimize the parasitic effects of the device drain to source capacitance. In a preferred embodiment, the active device includes a silicon-germanium n-channel field effect transistor (NFET) optimized for operation at high frequencies (e.g. up to 20 GHz). In the illustrative embodiment, the optimization process includes coupling a compact, low-parasitic polysilicon resistor to a gate of the NFET to provide gate RF isolation, and designing the gate manifold, drain manifold, and drain to source spacing of the NFET for optimal high frequency operation.
a is a layout of a parallel configuration implementation of the series-shunt switching device of
b is a layout of a 90 degree configuration implementation of the series-shunt switching device of
Illustrative embodiments and exemplary applications will now be described with reference to the accompanying drawings to disclose the advantageous teachings of the present invention.
While the present invention is described herein with reference to illustrative embodiments for particular applications, it should be understood that the invention is not limited thereto. Those having ordinary skill in the art and access to the teachings provided herein will recognize additional modifications, applications, and embodiments within the scope thereof and additional fields in which the present invention would be of significant utility.
Inasmuch as capacitance of current large gate periphery SiGe NFETs (particularly 0.18 um devices) provides a low capacitive reactive impedance on the order of 50 ohms at around 20 GHz and beyond, it is useful to provide a suitable reactive inductive load in shunt with the device drain to source capacitance (Cds) to increase the impedance at the device output reference plane and thereby minimize the switch insertion loss. The circuit shown in
By this approach, the useful frequency range of the switch can be extended to 20 GHz. For example, the present teachings should provide good KU band switching performance over 15.0 to 17.0 GHz having an insertion loss of less than 1.0 dB and isolation of greater than 20 dB across the frequency band of interest. By adjusting the dimensions of the NFET device as well as the shunt distributed transmission line 22, it should be possible to move the center of the resonance frequency to high mm-wave frequencies.
In a preferred embodiment, the active device 12 is implemented using an N-Channel-Metal-Oxide Semiconductor (NMOS) switching device optimized for high frequency operation.
In accordance with the teachings of the present invention, a compact, low-parasitic integrated resistor R is coupled to the gate of the device 32 to provide gate RF isolation and gate-tie-down configuration to minimize undesirable Si substrate effects at microwave frequencies. In an illustrative embodiment, the resistor R is a compact polysilicon resistor, and the value of the resistor R is designed to minimize parasitic contributions. The resistor R is connected between the gate of the device 32 and a voltage supply V1 having an associated capacitance C1.
In addition, the substrate (body) of the NFET 32 is coupled to a DC voltage V2 having a capacitance C2 to minimize the parasitics associated with the substrate and enhance the performance of the switch.
When designing the NFET 32, the parameters of the device can also be optimized for high frequency operation. In particular, the gate manifold, drain manifold, and drain to source spacing of the device contribute significantly to high frequency performance. In the preferred embodiment, these parameters are optimized during the design process to reduce the extrinsic parasitic elements of the device 32.
In accordance with the teachings of the present invention, a compact polysilicon resistor R is coupled to the gate of the device 32′ to provide gate RF isolation. The resistor R is connected between the gate of the device 32′ and a voltage supply V1 having an associated capacitance C1. The substrate (body) of the NFET 32′ is coupled to a DC voltage V2 having a capacitance C2.
The switching device 50 also includes a second NFET 54 connected in shunt to the source of the first NFET 52. The drain of the shunt NFET 54 is coupled to the source of the series NFET 52 and the source of the shunt NFET 54 is coupled to ground. A compact polysilicon resistor R2 is coupled between the gate of the device 54 and a voltage supply V3 having an associated capacitance C3. The substrates of the devices 52 and 54 are coupled to a voltage supply V2 having a capacitance C2.
a is a layout of a parallel configuration implementation of the series-shunt switching device 50 of
By optimizing the parameters of the devices 52 and 54 as described above, and optimizing the interconnections between the two devices 52 and 54 to minimize parasitics, the series-shunt configuration shown in
The switching circuits discussed above have been single pole single throw (SPST) switches. However, the invention is not limited thereto. The teachings of the present invention can also be applied to other switch configurations including multiple pole multiple throw switches. For example,
The SPDT switch 60 includes two active devices 62 and 64. The first device 62 is coupled between an input terminal 60 having an impedance ZIN and a first output terminal 68 having an impedance ZOUT1. The second device 64 is coupled between the input terminal 60 and a second output terminal 68 having an impedance ZOUT2. The output (drain) of the first device 62 is coupled to the input terminal 60 by a transmission line 72, and to the output terminal 68. The output (drain) of the second device 64 is coupled to the input terminal 60 by a transmission line 74, and to the output terminal 70.
In accordance with the teachings of the present invention, a transmission line is connected to the output of each device to provide a reactive inductive load in shunt with the device drain to source capacitance. As shown in
Thus, the present invention has been described herein with reference to a particular embodiment for a particular application. Those having ordinary skill in the art and access to the present teachings will recognize additional modifications, applications and embodiments within the scope thereof.
It is therefore intended by the appended claims to cover any and all such applications, modifications and embodiments within the scope of the present invention.
Accordingly,
