Claims
- 1. A method of fabricating a one-gate thin film transistor, having an active region and a gate, wherein said active region comprises a poly-Si1−xGex alloy material and channel layer of silicon, in which the channel layer of silicon is interposed between the poly-Si1−xGex alloy material and the gate, comprising:depositing a gate, depositing an active region comprising a poly-Si1−xGex alloy material layer and a channel layer of silicon, to form a composite, and treating the composite with at least one method selected from the group consisting of crystallization and excimer laser annealing, wherein said depositing a gate occurs subsequent to said depositing an active region and said treating the composite, wherein x ranges from 0.05 to 0.4 atomic %.
- 2. The method according to claim 1, wherein said depositing an active region comprises depositing a Si1−xGex alloy material on an insulating substrate to form a poly-Si1−xGex layer and subsequently depositing a silicon layer upon said poly-Si1−xGex layer to form a composite.
- 3. The method according to claim 2, wherein said depositing an active region is accomplished by treating the insulating substrate with a source of silicon and a source of germanium.
- 4. The method according to claim 3, wherein said source of silicon and said source of germanium are initially applied simultaneously and subsequently the insulating substrate is treated with a source of silicon.
- 5. The method according to claim 3, wherein said source of silicon and said source of germanium are initially applied simultaneously and, subsequently after a finite, non-zero time, the source of germanium is discontinued while the source of silicon is continued.
- 6. The method according to claim 1, wherein said treatment of the composite comprises solid phase crystallization.
- 7. The method according to claim 1, wherein said treatment of the composite comprises excimer laser annealing.
- 8. The method according to claim 1, wherein the thickness of the channel layer of silicon is 100 Å or less.
- 9. The method according to claim 8, wherein the thickness of the channel layer of silicon is 50 Å or less.
- 10. The method according to claim 1, wherein the thickness of the poly-Si1−xGex layer ranges from 100 Å to 1500 Å.
- 11. The method according to claim 10, wherein the thickness of the poly-Si1−xGex layer ranges from 100 Å to 1000 Å.
- 12. The method according to claim 1, wherein x ranges from 0.10 to 0.30 atomic %.
- 13. The method according to claim 12, wherein x is 0.20 atomic %.
Parent Case Info
This application is a divisional of application Ser. No 08/411,203 filed Mar. 27, 1995 now U.S. Pat. No. 5,828,084.
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