Claims
- 1. A method of minimizing a circuit element interference and stabilizing a performance of a circuit element within a Time Division Duplex (TDD) transceiver, which comprises:
providing a medium for a communication signal propagating back and forth through the medium; constructing an analog circuit for receiving and transmitting the communication signal through the medium at a time, and for modulating and demodulating the communication signal during a communication signal receiving and transmitting process; constructing a digital circuit for digital signal processing; constructing an analog-to-digital (A/D) interface and a digital-to-analog (D/A) interface so that the interfaces couples the analog circuit and the digital circuit together; providing a first ground reference so that all ground references of circuit elements in the analog circuit, in the A/D interface, and in the D/A interface are connected to the first ground reference; providing a second ground reference so that all ground references of circuit elements in the digital circuit are grounded to the second ground reference; providing a joint clock source for supplying clock pulses to the analog circuit, the digital circuit, the A/D interface, and the D/A interface; and connecting a ground reference of the joint clock source to the first ground reference.
- 2. The method of claim 1, wherein the medium is an antenna and the communication signal propagates through the air.
- 3. The method of claim 1, wherein the medium is a communication wire where the communication signal propagates through the wire.
- 4. The method of claim 1, wherein the joint clock source is a crystal oscillator.
- 5. The method of claim 1, where in the constructing analog circuit step further comprises:
providing a switch for transmitting or receiving the communication signal in different time periods; providing a down-convertor for converting the received communication signal to a baseband signal; providing an up-convertor for converting a baseband signal to a radio frequency signal; and constructing a synthesizer to provide the down-convertor and the up-convertor with a base frequency of signal so that the received and baseband communication signals are demodulated and modulated respectively.
- 6. The method of claim 1, where in the constructing digital circuit step further comprises:
providing baseband processor for digital signal processing; and providing a media access control (MAC) unit.
- 7. The method of claim 1, wherein the A/D interface is an analog-to-digital convertor.
- 8. The method of claim 1, wherein the D/A interface is a digital-to-analog convertor.
- 9. A circuit architecture for minimizing a circuit element interference and stabilizing a performance of a circuit element within a TDD transceiver, which comprises:
a medium within which a communication signal propagates through; an analog circuit for receiving and transmitting the communication signal in different time periods, and for modulating and demodulating the communication signal during a communication signal transmitting and receiving process; a digital circuit for digital signal processing; an A/D interface circuit and a D/A interface circuit for coupling the analog circuit and the digital circuit together; a first ground reference on which all ground references of circuit elements of the analog circuit, the A/D interface circuit, and the D/A interface circuit are connected together; a second ground reference on which all ground references of circuit elements of the digital circuit are connected together; and a joint clock source to supply clock pluses to the analog circuit, the digital circuit, the A/D interface circuit, and the D/A interface circuit, and to have a ground reference of the joint clock source connected to the first ground reference.
- 10. The circuit architecture of claim 9, wherein the medium is an antenna and the communication signal propagates through the air.
- 11. The circuit architecture of claim 9, wherein the medium is a communication wire where the communication signal propagates through the wire.
- 12. The circuit architecture of claim 9, wherein the joint lock source is a crystal oscillator.
- 13. The circuit architecture of claim 9, wherein the analog circuit further comprises:
a switch for transmitting or receiving the communication signal in different time periods; a down-convertor for converting the received communication signal to a baseband signal; an up-convertor for converting a baseband signal to a radio frequency signal; and a synthesizer for providing the down-convertor and the up-convertor with a base frequency of signal so that the received and baseband communication signals are demodulated and modulated respectively.
- 14. The circuit architecture of claim 9, wherein the digital circuit further comprises:
a baseband processor for digital signal processing; and a media access control (MAC) unit.
- 15. The circuit architecture of claim 9, wherein the A/D interface is an analog-to-digital convertor.
- 16. The circuit architecture of claim 9, wherein the D/A interface is a digital-to-analog convertor.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefits of U.S. provisional application titled “METHOD AND APPARATUS FOR IMPROVING PERFORMANCE OF A COMMUNICATION TRANSCEIVER” filed on Apr. 25. 2003, Ser. No. 60/466,008. All disclosure of this application is incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60466008 |
Apr 2003 |
US |