This invention relates to the implementation of high-rate interpolation or decimation filters on integrated circuit devices, especially programmable integrated circuit devices such as programmable logic devices (PLDs).
Finite impulse response (FIR) filters are commonly used in digital signal processing. FIR filters include interpolation and decimation filters, in which, in order to add or remove samples, respectively, by a certain factor N, each input sample has to be held while calculations for the N−1 interpolated samples are made, or each output sample has to be held while calculations for the N−1 decimated samples are made. If the filter is to operate in real time, the portion of the filter that performs those calculations has to run at N times the input sample rate (in the interpolation case) or the output sample rate (in the decimation case).
However, the filter cannot run faster than the clock rate of the device on which the filter is built. This becomes more of an issue as data rates of signals to be processed increase. If the filter is built in fixed logic, it may be possible to design the device speed to take the data rate into account. But on a programmable device, such as a PLD, one cannot know, when designing the programmable device itself, what kind of logic a user may want to program onto the device, so the device clock rate cannot be designed with a particular data rate in mind. And even with a fixed device, the ability to design to any clock rate may be limited.
In addition, the number of filter taps is directly proportional to the ratio of sample rate to transition bandwidth. Each filter tap requires at least one multiplier. Again, on a fixed device, one may be able to provide whatever number of multipliers one needs (although again, there may be reasons why there are limits to the number of multipliers), but on a programmable device, a certain number of multipliers will be provided but it is not possible to predict how many a user may need. One solution that a user may resort to is to break the filter down into stages, thereby limiting the number of multipliers required. However, the data rate increases with each stage, so the problem of the input rate for later stages (in the interpolation case), or the output rate for earlier stages (in the decimation case), exceeding the device rate may arise for this reason as well.
In accordance with the present invention, an interpolation filter not only may be broken into stages, but each stage may be broken into subfilters, which divides the output into phases. The number of subfilters or phases in the final stage is equal to the factor by which the data rate would otherwise increase. Thus, in one example, for an interpolation factor of M, the output data rate can be kept within the device rate by providing M subfilters, yielding M output phases each having an output rate equal to the input rate. The effective, or synthesized, output rate in such a case is M times the input rate.
Moreover, the number of input phases will increase with each stage. For stages after the first stage, the number of input phases would be the number of output phases of the previous stage. However, even for the first stage, the number of input phases may be greater than one. To generalize, for each stage, there may be any number of input phases (Pi), and a stage interpolation factor (Ms ), yielding a number of output phases (Po), where Po=Pi Ms. Each output phase is produced by a subfilter, so there are Po subfilters. Each subfilter has Pi branches to accept the Pi input phases.
For the filter as a whole, having n stages, the overall effective interpolation factor is:
However, while the effective output data rate is M times the input data rate Ri, the actual data rate of each output phase is only MRi/Pof where Pof is the number of final output phases.
The case of a decimation filter is similar. For an overall decimation factor of M, there can be more than one stage. Because in decimation, the number of samples is decreased by the filter, the number of input phases exceeds the number of output phases. Thus the earlier stages have the larger number of subfilters sampling the respective input phases. The output phases of the subfilters in the earlier stage are combined for input to corresponding taps of the subfilters in the later stage. While the effective input data rate is M times the output data rate Ro, the actual data rate of each input phase is only MRo/Pif where Pif is the number of initial input phases.
Therefore, in accordance with the present invention, there is provided a FIR filter structure on an integrated circuit device for processing data samples and a set of a number of coefficients at an effective data rate that exceeds a maximum data rate of said device by a factor. The FIR filter structure includes a plurality of FIR filter stages including at a least an initial filter stage and a final filter stage. Each of the filter stages has one or more subfilters. A first one of the initial and final filter stages has a number of subfilters that exceeds a number of subfilters in a second of the initial and final filter stages by the aforementioned factor. Each subfilter in each respective filter stage convolves input data with a subset of coefficients whose number is related to a number of subfilters in an adjacent filter stage.
A method of configuring such circuitry on a programmable device, a programmable device so configurable, and a machine-readable data storage medium encoded with software for performing the method, are also provided.
Further features of the invention, its nature and various advantages will be apparent upon consideration of the following detailed description, taken in conjunction with the accompanying drawings, in which like reference characters refer to like parts throughout, and in which:
A FIR filter calculates a weighted sum of a finite number of inputs, summing a number of multiplication results, where each multiplication is between a sample and a coefficient. Each such multiplication may be referred to as a “tap.” Mathematically, a FIR filter may be described as:
where Yk is the kth output term, ci is the ith coefficient, sk-i is the (k−i)th sample, and Taps is the number of taps in the filter.
One example of a digital signal processing block for a programmable device, that may be configured as different types of filters, including an interpolation FIR filter and a decimation FIR filter, is shown in copending, commonly-assigned U.S. patent application Ser. No. 11/447,370, filed Jun. 5, 2006, which is hereby incorporated by reference herein in its entirety, although the present invention may be used with other types of devices.
In the case of interpolation, one inserts outputs between the outputs that are generated based on input samples. In the case, for example, of interpolation by two, one must create one output between each output based on an input sample. Therefore, the FIR filter circuitry must generate two outputs in the time interval occupied by one input—i.e., it must run at twice the input clock rate. For interpolation by a higher factor M, the circuitry must generate M−1 outputs between the outputs that are generated based on input samples, or a total of M outputs in the time interval occupied by one input—i.e., in a conventional interpolation filter, the circuitry must run at M times the input clock rate.
Similarly in the case of decimation, only one output is generated for every M inputs. In the case, for example, of decimation by two, one must accept two inputs for each output sample generated per output clock. Therefore, the FIR filter circuitry must generate an output in the time interval occupied by two inputs—i.e., it must run at twice the output clock rate. For decimation by a higher factor M, the circuitry must generate an output in the time interval occupied by M inputs—i.e., in a conventional interpolation filter, the circuitry must run at M times the output clock rate.
The invention will now be described with reference to
Many gigabit serial data standards now support synthesized output sample rates at or exceeding one billion samples per second (1 Gsps), but device clock rates have not kept pace, resulting in ever-higher interpolation factors M. Because the input data rate cannot exceed the device clock rate, sampling is performed with a narrow transition bandwidth. According to the filter design theory, the number of filter taps is proportional to the ratio of sample frequency to transition bandwidth. The use of ever-higher interpolation factors increases this ratio by both increasing the numerator and decreasing the denominator, thereby greatly increasing the number of filter taps. Each filter tap requires at least one multiplier, and if the number of multipliers on the device is limited, as it would be on a programmable device such as an FPGA that is not manufactured with a particular filter implementation in mind (and as might be the case even in a fixed logic device for other manufacturing reasons) the required number of taps could exceed the available number of multipliers on the device.
One known solution is to break down the 1:M interpolation into a number of cascaded filter stages to reduce the total number of multipliers.
Therefore, in accordance with an embodiment of the present invention, filter 300 may be provided, as shown in
The output rate of each subfilter 305 may be the same as the original input rate of the first stage 301, and the full multiplication of the input rate by M to achieve the final output rate is accomplished by having M subfilters 305 in the final stage 304. Alternatively, the output rate of each subfilter 305 may be the more or less than the original input rate of the first stage 301, as long as it does not exceed the device rate, and the number of subfilters 305 in final stage 304 can be adjusted accordingly.
Thus, as seen in
More generally, each of n subfilters picks a consistent pattern of coefficients—e.g., every nth coefficient, with the starting point and rotation determined by the user as a function of the particular application when the filter is designed. Over all of the subfilters, each of the coefficients is selected Ms times.
Although in the example shown in
Another example 610 of interpolation-by-6, in two filter stages, is shown in
These arrangements can be proven mathematically. A regular interpolation-by-two filter can be represented by
y=Hx
More specifically,
where N=length of the original filter, and h(0) . . . h(N−1)=the coefficients of the original filter.
Because the output data rate can not actually be faster than clock rate of the device, the interpolation-by-2 can be performed with 1-to-2 polyphase filter.
To simplify the notation, the above can be written as:
However, the foregoing notation assumes the input data rate is lower or equal to the clock rate in the device. When the input data rate is faster than clock rate, the input can be separated into different phases as well. For example, an interpolation-by-2 filter can be designed as a 2 phase input/4 phase output system:
Hp is the filter matrix of the pth phase of an M-phase polyphase decomposition of the original filter H, where M is the number of output phases. For example:
H*p is the delayed version of the pth phase of an M-phase polyphase decomposition of the original filter H. For example:
The {tilde over (H)} matrix includes subfilter matrices (derived from polyphase decomposition) and the indices of the subfilter matrices have a regular structure and can be created by the following algorithm:
Ĥ=toeplitz(H[0:1:M−1],H*[M:−1):1]).
And {tilde over (H)}=Ĥ(:,1:f:end)
Where f is the interpolation factor and M is the number of outputs phases.
For example, the {tilde over (H)} filter for a 4-to-8 interpolator is:
Also, the output phases can be computed by:
As an example, the first output phase can be computed by the following:
y0=H0x0+H6*x1+H4*x2+H2*x3
where:
The invention also applies to interpolation filters with interpolation factors greater than 2. For example, a interpolate-by-3 filter can be implemented as a 3-to-9 phase interpolator:
From the foregoing, one can derive the following applications:
1. Single-rate filtering (n phases in and n phases out) at rates above the device rate:
Ĥ=toeplitz(H[0:1:n−1],H[n:(−1):1]*);
y=Ĥ*x;
For example: 4 phases in and 4 phases out:
2. Decimation filtering (↓M: n phases in and n/M phases out):
Ĥ=toeplitz(H[0:1:n−1],H[n:(−1):1]*);
y=Ĥ(1:M:end,:)*x;
For example: 4 phases in and 2 phases out (decimate-by-2):
3. Interpolation filtering (↑M: n phases in and nM phases out):
Ĥ=toeplitz(H[0:1:nM−1],H[nM:(−1):1]*);
y=Ĥ(:,1:M:end)*x;
For example: 2 phases in and 4 phases out (interpolate-by-2):
4. Fractional filtering (↑M/N: n phase in and nM/N phases out):
For example: 4 phase input→decimate-by-2→interpolate by 3→6 phase output
A PLD 280 configured according to the present invention may be used in many kinds of electronic devices. One possible use is in a data processing system 900 shown in
System 900 can be used in a wide variety of applications, such as computer networking, data networking, instrumentation, video processing, digital signal processing, or any other application where the advantage of using programmable or reprogrammable logic is desirable. PLD 280 can be used to perform a variety of different logic functions. For example, PLD 280 can be configured as a processor or controller that works in cooperation with processor 281. PLD 280 may also be used as an arbiter for arbitrating access to a shared resources in system 900. In yet another example, PLD 280 can be configured as an interface between processor 281 and one of the other components in system 900. It should be noted that system 900 is only exemplary, and that the true scope and spirit of the invention should be indicated by the following claims.
Various technologies can be used to implement PLDs 280 as described above and incorporating this invention.
Instructions for carrying out the method according to this invention may be encoded on a machine-readable medium, to be executed by a suitable computer or similar device to implement the method of the invention for programming PLDs. For example, a personal computer may be equipped with an interface to which a PLD can be connected, and the personal computer can be used by a user to program the PLD using a suitable software tool, such as the QUARTUS® II software available from Altera Corporation, of San Jose, Calif.
The magnetic domains of coating 602 of medium 600 are polarized or oriented so as to encode, in manner which may be conventional, a machine-executable program, for execution by a programming system such as a personal computer or other computer or similar system, having a socket or peripheral attachment into which the PLD to be programmed may be inserted, to configure appropriate portions of the PLD, including its specialized processing blocks, if any, as a filter in accordance with the invention.
In the case of a CD-based or DVD-based medium, as is well known, coating 702 is reflective and is impressed with a plurality of pits 703, arranged on one or more layers, to encode the machine-executable program. The arrangement of pits is read by reflecting laser light off the surface of coating 702. A protective coating 704, which preferably is substantially transparent, is provided on top of coating 702.
In the case of magneto-optical disk, as is well known, coating 702 has no pits 703, but has a plurality of magnetic domains whose polarity or orientation can be changed magnetically when heated above a certain temperature, as by a laser (not shown). The orientation of the domains can be read by measuring the polarization of laser light reflected from coating 702. The arrangement of the domains encodes the program as described above.
It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. For example, the various elements of this invention can be provided on a PLD in any desired number and/or arrangement. One skilled in the art will appreciate that the present invention can be practiced by other than the described embodiments, which are presented for purposes of illustration and not of limitation, and the present invention is limited only by the claims that follow.
Number | Name | Date | Kind |
---|---|---|---|
3473160 | Wahlstrom | Oct 1969 | A |
3800130 | Martinson et al. | Mar 1974 | A |
3814924 | Tate | Jun 1974 | A |
4156927 | McElroy et al. | May 1979 | A |
4179746 | Tubbs | Dec 1979 | A |
4212076 | Conners | Jul 1980 | A |
4215406 | Gomola et al. | Jul 1980 | A |
4215407 | Gomola et al. | Jul 1980 | A |
4422155 | Amir et al. | Dec 1983 | A |
4484259 | Palmer et al. | Nov 1984 | A |
4521907 | Amir et al. | Jun 1985 | A |
4575812 | Kloker et al. | Mar 1986 | A |
4597053 | Chamberlin | Jun 1986 | A |
4616330 | Betz | Oct 1986 | A |
4623961 | Mackiewicz | Nov 1986 | A |
4682302 | Williams | Jul 1987 | A |
4718057 | Venkitakrishnan et al. | Jan 1988 | A |
4727508 | Williams | Feb 1988 | A |
4736335 | Barkan | Apr 1988 | A |
4754421 | Bosshart | Jun 1988 | A |
4791590 | Ku et al. | Dec 1988 | A |
4799004 | Mori | Jan 1989 | A |
4823295 | Mader | Apr 1989 | A |
4839847 | Laprade | Jun 1989 | A |
4871930 | Wong et al. | Oct 1989 | A |
4912345 | Steele et al. | Mar 1990 | A |
4918637 | Morton | Apr 1990 | A |
4967160 | Quievy et al. | Oct 1990 | A |
4982354 | Takeuchi et al. | Jan 1991 | A |
4991010 | Hailey et al. | Feb 1991 | A |
4994997 | Martin et al. | Feb 1991 | A |
5068813 | Thoen | Nov 1991 | A |
5073863 | Zhang | Dec 1991 | A |
5081604 | Tanaka | Jan 1992 | A |
5122685 | Chan et al. | Jun 1992 | A |
5128559 | Steele | Jul 1992 | A |
5175702 | Beraud et al. | Dec 1992 | A |
5208491 | Ebeling et al. | May 1993 | A |
RE34363 | Freeman | Aug 1993 | E |
5267187 | Hsieh et al. | Nov 1993 | A |
5296759 | Sutherland et al. | Mar 1994 | A |
5338983 | Agarwala | Aug 1994 | A |
5339263 | White | Aug 1994 | A |
5349250 | New | Sep 1994 | A |
5357152 | Jennings, III et al. | Oct 1994 | A |
5371422 | Patel et al. | Dec 1994 | A |
5375079 | Uramoto et al. | Dec 1994 | A |
5381357 | Wedgwood et al. | Jan 1995 | A |
5404324 | Colon-Benet | Apr 1995 | A |
5416799 | Currivan et al. | May 1995 | A |
5424589 | Dobbelaere et al. | Jun 1995 | A |
5446651 | Moyse et al. | Aug 1995 | A |
5451948 | Jekel | Sep 1995 | A |
5452231 | Butts et al. | Sep 1995 | A |
5452375 | Rousseau et al. | Sep 1995 | A |
5457644 | McCollum | Oct 1995 | A |
5465226 | Goto | Nov 1995 | A |
5465375 | Thepaut et al. | Nov 1995 | A |
5483178 | Costello et al. | Jan 1996 | A |
5497498 | Taylor | Mar 1996 | A |
5500812 | Saishi et al. | Mar 1996 | A |
5500828 | Doddington et al. | Mar 1996 | A |
5523963 | Hsieh et al. | Jun 1996 | A |
5528550 | Pawate et al. | Jun 1996 | A |
5537601 | Kimura et al. | Jul 1996 | A |
5541864 | Van Bavel et al. | Jul 1996 | A |
5546018 | New et al. | Aug 1996 | A |
5550993 | Ehlig et al. | Aug 1996 | A |
5559450 | Ngai et al. | Sep 1996 | A |
5563526 | Hastings et al. | Oct 1996 | A |
5563819 | Nelson | Oct 1996 | A |
5570039 | Oswald et al. | Oct 1996 | A |
5570040 | Lytle et al. | Oct 1996 | A |
5572148 | Lytle et al. | Nov 1996 | A |
5581501 | Sansbury et al. | Dec 1996 | A |
5590350 | Guttag et al. | Dec 1996 | A |
5594366 | Khong et al. | Jan 1997 | A |
5594912 | Brueckmann et al. | Jan 1997 | A |
5596763 | Guttag et al. | Jan 1997 | A |
5606266 | Pedersen | Feb 1997 | A |
5617058 | Adrian et al. | Apr 1997 | A |
5623377 | Behrens et al. | Apr 1997 | A |
5631848 | Laczko et al. | May 1997 | A |
5633601 | Nagaraj | May 1997 | A |
5636150 | Okamoto | Jun 1997 | A |
5636368 | Harrison et al. | Jun 1997 | A |
5640578 | Balmer et al. | Jun 1997 | A |
5644519 | Yatim | Jul 1997 | A |
5644522 | Moyse et al. | Jul 1997 | A |
5646545 | Trimberger et al. | Jul 1997 | A |
5646875 | Taborn et al. | Jul 1997 | A |
5648732 | Duncan | Jul 1997 | A |
5652903 | Weng et al. | Jul 1997 | A |
5655069 | Ogawara et al. | Aug 1997 | A |
5664192 | Lloyd et al. | Sep 1997 | A |
5689195 | Cliff et al. | Nov 1997 | A |
5696708 | Leung | Dec 1997 | A |
5729495 | Madurawe | Mar 1998 | A |
5740404 | Baji | Apr 1998 | A |
5744980 | McGowan et al. | Apr 1998 | A |
5744991 | Jefferson et al. | Apr 1998 | A |
5754459 | Telikepalli | May 1998 | A |
5761483 | Trimberger | Jun 1998 | A |
5764555 | McPherson et al. | Jun 1998 | A |
5768613 | Asghar | Jun 1998 | A |
5771186 | Kodali et al. | Jun 1998 | A |
5777912 | Leung et al. | Jul 1998 | A |
5784636 | Rupp | Jul 1998 | A |
5790446 | Yu et al. | Aug 1998 | A |
5794067 | Kadowaki | Aug 1998 | A |
5801546 | Pierce et al. | Sep 1998 | A |
5805477 | Perner | Sep 1998 | A |
5805913 | Guttag et al. | Sep 1998 | A |
5808926 | Gorshtein et al. | Sep 1998 | A |
5812479 | Cliff et al. | Sep 1998 | A |
5812562 | Baeg | Sep 1998 | A |
5815422 | Dockser | Sep 1998 | A |
5821776 | McGowan | Oct 1998 | A |
5825202 | Tavana et al. | Oct 1998 | A |
5838165 | Chatter | Nov 1998 | A |
5841684 | Dockser | Nov 1998 | A |
5847579 | Trimberger | Dec 1998 | A |
5847978 | Ogura et al. | Dec 1998 | A |
5847981 | Kelley et al. | Dec 1998 | A |
5859878 | Phillips et al. | Jan 1999 | A |
5869979 | Bocchino | Feb 1999 | A |
5872380 | Rostoker et al. | Feb 1999 | A |
5874834 | New | Feb 1999 | A |
5878250 | LeBlanc | Mar 1999 | A |
5880981 | Kojima et al. | Mar 1999 | A |
5892962 | Cloutier | Apr 1999 | A |
5894228 | Reddy et al. | Apr 1999 | A |
5898602 | Rothman et al. | Apr 1999 | A |
5931898 | Khoury | Aug 1999 | A |
5935197 | Aldworth | Aug 1999 | A |
5942914 | Reddy et al. | Aug 1999 | A |
5944774 | Dent | Aug 1999 | A |
5949710 | Pass et al. | Sep 1999 | A |
5951673 | Miyata | Sep 1999 | A |
5956265 | Lewis | Sep 1999 | A |
5959871 | Pierzchala et al. | Sep 1999 | A |
5960193 | Guttag et al. | Sep 1999 | A |
5961635 | Guttag et al. | Oct 1999 | A |
5963048 | Harrison et al. | Oct 1999 | A |
5963050 | Young et al. | Oct 1999 | A |
5968196 | Ramamurthy et al. | Oct 1999 | A |
5970254 | Cooke et al. | Oct 1999 | A |
5978260 | Trimberger et al. | Nov 1999 | A |
5982195 | Cliff et al. | Nov 1999 | A |
5986465 | Mendel | Nov 1999 | A |
5991788 | Mintzer | Nov 1999 | A |
5991898 | Rajski et al. | Nov 1999 | A |
5995748 | Guttag et al. | Nov 1999 | A |
5999015 | Cliff et al. | Dec 1999 | A |
5999990 | Sharrit et al. | Dec 1999 | A |
6005806 | Madurawe et al. | Dec 1999 | A |
6006321 | Abbott | Dec 1999 | A |
6009451 | Burns | Dec 1999 | A |
6018755 | Gonikberg et al. | Jan 2000 | A |
6020759 | Heile | Feb 2000 | A |
6021423 | Nag et al. | Feb 2000 | A |
6029187 | Verbauwhede | Feb 2000 | A |
6031763 | Sansbury | Feb 2000 | A |
6041339 | Yu et al. | Mar 2000 | A |
6041340 | Mintzer | Mar 2000 | A |
6052327 | Reddy et al. | Apr 2000 | A |
6052755 | Terrill et al. | Apr 2000 | A |
6055555 | Boswell et al. | Apr 2000 | A |
6064614 | Khoury | May 2000 | A |
6065131 | Andrews et al. | May 2000 | A |
6066960 | Pedersen | May 2000 | A |
6069487 | Lane et al. | May 2000 | A |
6072994 | Phillips et al. | Jun 2000 | A |
6073154 | Dick | Jun 2000 | A |
6075381 | LaBerge | Jun 2000 | A |
6084429 | Trimberger | Jul 2000 | A |
6085317 | Smith | Jul 2000 | A |
6091261 | DeLange | Jul 2000 | A |
6091765 | Pietzold, III et al. | Jul 2000 | A |
6094726 | Gonion et al. | Jul 2000 | A |
6097988 | Tobias | Aug 2000 | A |
6098163 | Guttag et al. | Aug 2000 | A |
6107820 | Jefferson et al. | Aug 2000 | A |
6107821 | Kelem et al. | Aug 2000 | A |
6107824 | Reddy et al. | Aug 2000 | A |
6130554 | Kolze et al. | Oct 2000 | A |
6140839 | Kaviani et al. | Oct 2000 | A |
6144980 | Oberman | Nov 2000 | A |
6154049 | New | Nov 2000 | A |
6157210 | Zaveri et al. | Dec 2000 | A |
6163788 | Chen et al. | Dec 2000 | A |
6167415 | Fischer et al. | Dec 2000 | A |
6175849 | Smith | Jan 2001 | B1 |
6215326 | Jefferson et al. | Apr 2001 | B1 |
6226735 | Mirsky | May 2001 | B1 |
6242947 | Trimberger | Jun 2001 | B1 |
6243729 | Staszewski | Jun 2001 | B1 |
6246258 | Lesea | Jun 2001 | B1 |
6260053 | Maulik et al. | Jul 2001 | B1 |
6279021 | Takano et al. | Aug 2001 | B1 |
6286024 | Yano et al. | Sep 2001 | B1 |
6314442 | Suzuki | Nov 2001 | B1 |
6314551 | Borland | Nov 2001 | B1 |
6321246 | Page et al. | Nov 2001 | B1 |
6323680 | Pedersen et al. | Nov 2001 | B1 |
6327605 | Arakawa et al. | Dec 2001 | B2 |
6351142 | Abbott | Feb 2002 | B1 |
6353843 | Chehrazi et al. | Mar 2002 | B1 |
6359468 | Park et al. | Mar 2002 | B1 |
6360240 | Takano et al. | Mar 2002 | B1 |
6362650 | New et al. | Mar 2002 | B1 |
6366944 | Hossain et al. | Apr 2002 | B1 |
6367003 | Davis | Apr 2002 | B1 |
6369610 | Cheung et al. | Apr 2002 | B1 |
6377970 | Abdallah et al. | Apr 2002 | B1 |
6407576 | Ngai et al. | Jun 2002 | B1 |
6407694 | Cox et al. | Jun 2002 | B1 |
6427157 | Webb | Jul 2002 | B1 |
6434587 | Liao et al. | Aug 2002 | B1 |
6438569 | Abbott | Aug 2002 | B1 |
6438570 | Miller | Aug 2002 | B1 |
6446107 | Knowles | Sep 2002 | B1 |
6453382 | Heile | Sep 2002 | B1 |
6467017 | Ngai et al. | Oct 2002 | B1 |
6480980 | Koe | Nov 2002 | B2 |
6483343 | Faith et al. | Nov 2002 | B1 |
6487575 | Oberman | Nov 2002 | B1 |
6523055 | Yu et al. | Feb 2003 | B1 |
6523057 | Savo et al. | Feb 2003 | B1 |
6531888 | Abbott | Mar 2003 | B2 |
6538470 | Langhammer et al. | Mar 2003 | B1 |
6542000 | Black et al. | Apr 2003 | B1 |
6556044 | Langhammer et al. | Apr 2003 | B2 |
6557092 | Callen | Apr 2003 | B1 |
6571268 | Giacalone et al. | May 2003 | B1 |
6573749 | New et al. | Jun 2003 | B2 |
6574762 | Karimi et al. | Jun 2003 | B1 |
6591283 | Conway et al. | Jul 2003 | B1 |
6591357 | Mirsky | Jul 2003 | B2 |
6600495 | Boland et al. | Jul 2003 | B1 |
6600788 | Dick et al. | Jul 2003 | B1 |
6628140 | Langhammer et al. | Sep 2003 | B2 |
6687722 | Larsson et al. | Feb 2004 | B1 |
6692534 | Wang et al. | Feb 2004 | B1 |
6700581 | Baldwin et al. | Mar 2004 | B2 |
6725441 | Keller et al. | Apr 2004 | B1 |
6728901 | Rajski et al. | Apr 2004 | B1 |
6731133 | Feng et al. | May 2004 | B1 |
6732134 | Rosenberg et al. | May 2004 | B1 |
6744278 | Liu et al. | Jun 2004 | B1 |
6745254 | Boggs et al. | Jun 2004 | B2 |
6763367 | Kwon et al. | Jul 2004 | B2 |
6771094 | Langhammer et al. | Aug 2004 | B1 |
6774669 | Liu et al. | Aug 2004 | B1 |
6781408 | Langhammer | Aug 2004 | B1 |
6781410 | Pani et al. | Aug 2004 | B2 |
6788104 | Singh et al. | Sep 2004 | B2 |
6801924 | Green et al. | Oct 2004 | B1 |
6806733 | Pan et al. | Oct 2004 | B1 |
6836839 | Master et al. | Dec 2004 | B2 |
6874079 | Hogenauer | Mar 2005 | B2 |
6889238 | Johnson | May 2005 | B2 |
6904471 | Boggs et al. | Jun 2005 | B2 |
6917955 | Botchev | Jul 2005 | B1 |
6924663 | Masui et al. | Aug 2005 | B2 |
6959316 | Parviainen | Oct 2005 | B2 |
6963890 | Dutta et al. | Nov 2005 | B2 |
6971083 | Farrugia et al. | Nov 2005 | B1 |
6978287 | Langhammer | Dec 2005 | B1 |
6983300 | Ferroussat | Jan 2006 | B2 |
7020673 | Ozawa | Mar 2006 | B2 |
7047272 | Giacalone et al. | May 2006 | B2 |
7062526 | Hoyle | Jun 2006 | B1 |
7093204 | Oktem et al. | Aug 2006 | B2 |
7107305 | Deng et al. | Sep 2006 | B2 |
7113969 | Green et al. | Sep 2006 | B1 |
7181484 | Stribaek et al. | Feb 2007 | B2 |
7313585 | Winterrowd | Dec 2007 | B2 |
7395298 | Debes et al. | Jul 2008 | B2 |
7401109 | Koc et al. | Jul 2008 | B2 |
7409417 | Lou | Aug 2008 | B2 |
7415542 | Hennedy et al. | Aug 2008 | B2 |
7421465 | Rarick et al. | Sep 2008 | B1 |
7428565 | Fujimori | Sep 2008 | B2 |
7428566 | Siu et al. | Sep 2008 | B2 |
7430578 | Debes et al. | Sep 2008 | B2 |
7430656 | Sperber et al. | Sep 2008 | B2 |
7447310 | Koc et al. | Nov 2008 | B2 |
7472155 | Simkins et al. | Dec 2008 | B2 |
7508936 | Eberle et al. | Mar 2009 | B2 |
7519646 | Kaul et al. | Apr 2009 | B2 |
7536430 | Guevokian et al. | May 2009 | B2 |
7567997 | Simkins et al. | Jul 2009 | B2 |
7587443 | Langhammer | Sep 2009 | B1 |
7590676 | Langhammer | Sep 2009 | B1 |
7646430 | Brown Elliott et al. | Jan 2010 | B2 |
7668896 | Lutz et al. | Feb 2010 | B2 |
7719446 | Rosenthal et al. | May 2010 | B2 |
7769797 | Cho et al. | Aug 2010 | B2 |
7822799 | Langhammer et al. | Oct 2010 | B1 |
7836117 | Langhammer et al. | Nov 2010 | B1 |
7930335 | Gura | Apr 2011 | B2 |
7930336 | Langhammer | Apr 2011 | B2 |
8041759 | Langhammer et al. | Oct 2011 | B1 |
20010023425 | Oberman et al. | Sep 2001 | A1 |
20010029515 | Mirsky | Oct 2001 | A1 |
20010037351 | Hellberg | Nov 2001 | A1 |
20010037352 | Hong | Nov 2001 | A1 |
20020002573 | Landers et al. | Jan 2002 | A1 |
20020038324 | Page et al. | Mar 2002 | A1 |
20020049798 | Wang et al. | Apr 2002 | A1 |
20020078114 | Wang et al. | Jun 2002 | A1 |
20020089348 | Langhammer | Jul 2002 | A1 |
20020116434 | Nancekievill | Aug 2002 | A1 |
20030088757 | Lindner et al. | May 2003 | A1 |
20040064770 | Xin | Apr 2004 | A1 |
20040078403 | Scheuermann et al. | Apr 2004 | A1 |
20040083412 | Corbin et al. | Apr 2004 | A1 |
20040103133 | Gurney | May 2004 | A1 |
20040122882 | Zakharov et al. | Jun 2004 | A1 |
20040148321 | Guevorkian et al. | Jul 2004 | A1 |
20040172439 | Lin | Sep 2004 | A1 |
20040178818 | Crotty et al. | Sep 2004 | A1 |
20040193981 | Clark et al. | Sep 2004 | A1 |
20040267857 | Abel et al. | Dec 2004 | A1 |
20040267863 | Bhushan et al. | Dec 2004 | A1 |
20050038842 | Stoye | Feb 2005 | A1 |
20050144212 | Simkins et al. | Jun 2005 | A1 |
20050144215 | Simkins et al. | Jun 2005 | A1 |
20050144216 | Simkins et al. | Jun 2005 | A1 |
20050166038 | Wang et al. | Jul 2005 | A1 |
20050187997 | Zheng et al. | Aug 2005 | A1 |
20050187999 | Zheng et al. | Aug 2005 | A1 |
20050262175 | Iino et al. | Nov 2005 | A1 |
20060020655 | Lin | Jan 2006 | A1 |
20070083585 | St. Denis et al. | Apr 2007 | A1 |
20070185951 | Lee et al. | Aug 2007 | A1 |
20070185952 | Langhammer et al. | Aug 2007 | A1 |
20070241773 | Hutchings et al. | Oct 2007 | A1 |
20080133627 | Langhammer et al. | Jun 2008 | A1 |
20080183783 | Tubbs | Jul 2008 | A1 |
20090172052 | DeLaquil et al. | Jul 2009 | A1 |
20090187615 | Abe et al. | Jul 2009 | A1 |
20090300088 | Michaels et al. | Dec 2009 | A1 |
20100098189 | Oketani | Apr 2010 | A1 |
Number | Date | Country |
---|---|---|
0 158 430 | Oct 1985 | EP |
0 326 415 | Aug 1989 | EP |
0 380 456 | Aug 1990 | EP |
0 411 491 | Feb 1991 | EP |
0 461 798 | Dec 1991 | EP |
0 498 066 | Aug 1992 | EP |
0 555 092 | Aug 1993 | EP |
0 606 653 | Jul 1994 | EP |
0 657 803 | Jun 1995 | EP |
0 660 227 | Jun 1995 | EP |
0 668 659 | Aug 1995 | EP |
0 721 159 | Jul 1996 | EP |
0 905 906 | Mar 1999 | EP |
0 909 028 | Apr 1999 | EP |
0 927 393 | Jul 1999 | EP |
0 992 885 | Apr 2000 | EP |
1 031 934 | Aug 2000 | EP |
1 049 025 | Nov 2000 | EP |
1 058 185 | Dec 2000 | EP |
1 220 108 | Jul 2002 | EP |
2 283 602 | May 1995 | GB |
2 286 737 | Aug 1995 | GB |
2 318 198 | Apr 1998 | GB |
61-237133 | Oct 1986 | JP |
63-216131 | Aug 1988 | JP |
4-068709 | Mar 1992 | JP |
4-332036 | Nov 1992 | JP |
5-134851 | Jun 1993 | JP |
06-187129 | Jul 1994 | JP |
7-135447 | May 1995 | JP |
9-327000 | Dec 1997 | JP |
11-296345 | Oct 1999 | JP |
2000-259394 | Sep 2000 | JP |
2002-108606 | Apr 2002 | JP |
2002-251281 | Sep 2002 | JP |
WO9527243 | Oct 1995 | WO |
WO9628774 | Sep 1996 | WO |
WO9708606 | Mar 1997 | WO |
WO9812629 | Mar 1998 | WO |
WO9832071 | Jul 1998 | WO |
WO9838741 | Sep 1998 | WO |
WO9922292 | May 1999 | WO |
WO9931574 | Jun 1999 | WO |
WO9956394 | Nov 1999 | WO |
WO0051239 | Aug 2000 | WO |
WO0052824 | Sep 2000 | WO |
WO0113562 | Feb 2001 | WO |
WO 2005066832 | Jul 2005 | WO |
WO2005101190 | Oct 2005 | WO |
WO 2010102007 | Sep 2010 | WO |
Entry |
---|
Altera Corporation, “FIR Compiler: MegaCore® Function User Guide,” version 3.3.0, rev. 1, pp. 3 11 through 3 15 (Oct. 2005). |
Govindu, G. et al., “A Library of Parameterizable Floating-Point Cores for FPGAs and Their Application to Scientific Computing,” Proc Int'l Conf. Eng. Reconfigurable Systems and Algorithms (ERSA'05) Jun. 2005. |
Govindu, G. et al., “Analysis of High-performance Floating-point Arithmetic on FPGAs,” Proceedings of the 18th International Parallel and Distributed Processing Symposium (PDPS'04), pp. 149-156, Apr. 2004. |
Nakasato, N., et al., “Acceleration of Hydrosynamical Simulations using a FPGA board”, The Institute of Electronics Information and Communication Technical Report CPSY2005-47, vol. 105, No. 515, Jan. 17, 2006. |
Osana, Y., et al., “Hardware-resource Utilization Analysis on an FPGA-Based Biochemical Simulator ReCSiP”, The Institute of Electronics Information and Communication Technical Report CPSY2005-63, vol. 105, No. 516, Jan. 18, 2006. |
Vladimirova, T. et al., “Floating-Point Mathematical Co-Processor for a Single-Chip On-Board Computer,” MAPLD'03 Conference, D5, Sep. 2003. |
Altera Corporation, “Digital Signal Processing (DSP),” Stratix Device Handbook, vol. 2, Chapter 6 and Chapter 7, v1.1 (Sep. 2004). |
Altera Corporation, “DSP Blocks in Stratix II and Stratix II GX Devices ” Stratix II Device Handbook, vol. 2, Chapter 6, v4.0 (Oct. 2005). |
Underwood, K. “FPGAs vs. CPUs: Trends in Peak Floating-Point Performance,” Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, pp. 171-180, Feb. 22-24, 2004. |
Xilinx Inc., “XtremeDSP Design Considerations User Guide,” v 1.2, Feb. 4, 2005. |
Altera Corporation, “Advanced Synthesis Cookbook: A Design Guide for Stratix II, Stratix III and Stratix IV Devices,” Document Version 3.0, 112 pgs., May 2008. |
deDinechin, F. et al., “Large multipliers with less DSP blocks,” retrieved from http://hal-ens-lyon.archives-ouvertes.fr/ensl-00356421/en/, 9 pgs., available online Jan. 2009. |
Wajih, E.-H.Y. et al., “Efficient Hardware Architecture of Recursive Karatsuba-Ofman Multiplier,” 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 6 pgs., Mar. 2008. |
Zhou, G. et al., “Efficient and High-Throughput Implementations of AES-GCM on FPGAs,” International Conference on Field-Programmable Technology, 8 pgs., Dec. 2007. |
Altera Corporation, “Statix II Device Handbook, Chapter 6—DSP Blocks in Stratix II Devices,” v1.1, Jul. 2004. |
Xilinx Inc., “Complex Multiplier v2.0”, DS291 Product Specification/Datasheet, Nov. 2004. |
Martinson, L. et al., “Digital Matched Filtering with Pipelined Floating Point Fast Fourier Transforms (FFT's),” IEEE Transactions on Acoustics, Speech, and Signal Processing, vol. ASSP-23, No. 2, pp. 222-234, Apr. 1975. |
Amos, D., “PLD architectures match DSP algorithms,” Electronic Product Design, vol. 17, No. 7, Jul. 1996, pp. 30, 32. |
Analog Devices, Inc., The Applications Engineering Staff of Analog Devices, DSP Division, Digital Signal Processing Applications Using the ADSP-2100 Family (edited by Amy Mar), 1990, pp. 141-192). |
Andrejas, J., et al., “Reusable DSP functions in FPGAs,” Field-Programmable Logic and Applications. Roadmap to Reconfigurable Computing. 10th International Conference, FPL 2000. Proceedings (Lecture Notes in Computer Science vol. 1896), Aug. 27-30, 2000, pp. 456-461. |
Aoki, T., “Signed-weight arithmetic and its application to a field-programmable digital filter architecture,” IEICE Transactions on Electronics, 1999 , vol. E82C, No. 9, Sep. 1999, pp. 1687-1698. |
Ashour, M.A., et al., “An FPGA implementation guide for some different types of serial-parallel multiplier-structures,” Microelectronics Journal, vol. 31, No. 3, 2000, pp. 161-168. |
Berg. B.L., et al.“Designing Power and Area Efficient Multistage FIR Decimators with Economical Low Order Filters,” ChipCenter Technical Note, Dec. 2001. |
Bursky, D., “Programmable Logic Challenges Traditional ASIC SoC Designs”, Electronic Design, Apr. 15, 2002. |
Chhabra, A. et al., Texas Instruments Inc., “A Block Floating Point Implementation on the TMS320C54x DSP”, Application Report SPRA610, Dec. 1999, pp. 1-10. |
Colet, p., “When DSPs and FPGAs meet: Optimizing image processing architectures,” Advanced Imaging, vol. 12, No. 9, Sep. 1997, pp. 14, 16, 18. |
Crookes, D., et al., “Design and implementation of a high level programming environment for FPGA-based image processing,” IEE Proceedings-Vision, Image and Signal Processing, vol. 147, No. 4, Aug. 2000, pp. 377-384. |
Debowski, L., et al., “A new flexible architecture of digital control systems based on DSP and complex CPLD technology for power conversion applications,” PCIM 2000: Europe Official Proceedings of the Thirty-Seventh International Intelligent Motion Conference, Jun. 6-8, 2000, pp. 281-286. |
Dick, C., et al., “Configurable logic for digital communications: some signal processing perspectives,” IEEE Communications Magazine, vol. 37, No. 8, Aug. 1999, pp. 107-111. |
Do, T.-T., et al., “A flexible implementation of high-performance FIR filters on Xilinx FPGAs,” Field-Programmable Logic and Applications: From FPGAs to Computing Paradigm. 8th International Workshop, FPL'98. Proceedings, Hartenstein, R.W., et al., eds., Aug. 31-Sep. 3, 1998, pp. 441-445. |
Gaffer, A.A., et al., “Floating-Point Bitwidth Analysis via Automatic Differentiation,” IEEE Conference on Field Programmable Technology, Hong Kong, Dec. 2002. |
Guccione, S.A.,“Run-time Reconfiguration at Xilinx,” Parallel and distributed processing: 15 IPDPS 2000 workshops, Rolim, J., ed., May 1-5, 2000, p. 873. |
Hauck, S., “The Future of Reconfigurable Systems,” Keynote Address, 5th Canadian Conference on Field Programmable Devices, Jun. 1998, http://www.ee.washington.edu/people/faculty/hauck/publications/ReconfigFuture.PDF. |
Heysters, P.M., et al., “Mapping of DSP algorithms on field programmable function arrays,” Field-Programmable Logic and Applications. Roadmap to Reconfigurable Computing. 10th International Conference, FPL 2000 Proceedings (Lecture Notes in Computer Science vol. 1896) Aug. 27-30, 2000, pp. 400-411. |
Huang, J., et al., “Simulated Performance of 1000BASE-T Receiver with Different Analog Front End Designs,” Proceedings of the 35th Asilomar Conference on Signals, Systems, and Computers, Nov. 4-7, 2001. |
Lattice Semiconductor Corp, ORCA® FPGA Express™ Interface Manual: ispLEVER® Version 3.0, 2002. |
Lucent Technologies, Microelectronics Group,“Implementing and Optimizing Multipliers in ORCA™ FPGAs,”, Application Note.AP97-008FGPA, Feb. 1997. |
“Implementing Multipliers in FLEX 10K EABs”, Altera, Mar. 1996. |
“Implementing Logic with the Embedded Array in FLEX 10K Devices”, Altera, May 2001, ver. 2.1. |
Jinghua Li, “Design a pocket multi-bit multiplier in FPGA,” 1996 2nd International Conference on ASIC Proceedings (IEEE Cat. No. 96TH8140) Oct. 21-24, 1996, pp. 275-279. |
Jones, G., “Field-programmable digital signal conditioning,” Electronic Product Design, vol. 21, No. 6, Jun. 2000, pp. C36-C38. |
Kiefer, R., et al., “Performance comparison of software/FPGA hardware partitions for a DSP application,” 14th Australian Microelectronics Conference Microelectronics: Technology Today for the Future. MICRO '97 Proceedings, Sep. 28-Oct. 1, 1997, pp. 88-93. |
Kramberger, I., “DSP acceleration using a reconfigurable FPGA,” ISIE '99. Proceedings of the IEEE International Symposium on Industrial Electronics (Cat. No. 99TH8465), vol. 3 , Jul. 12-16, 1999, pp. 1522-1525. |
Langhammer, M., “How to implement DSP in programmable logic,” Elettronica Oggi, No. 266 , Dec. 1998, pp. 113-115. |
Langhammer, M., “Implementing a DSP in Programmable Logic,” Online EE Times, May 1998, http://www.eetimes.com/editorial/1998/coverstory9805.html. |
Lazaravich, B.V., “Function block oriented field programmable logic arrays,” Motorola, Inc. Technical Developments, vol. 18, Mar. 1993, pp. 10-11. |
Lund, D., et al., “A new development system for reconfigurable digital signal processing,” First International Conference on 3G Mobile Communication Technologies (Conf. Publ. No. 471), Mar. 27-29, 2000, pp. 306-310. |
Miller, N.L., et al., “Reconfigurable integrated circuit for high performance computer arithmetic,” Proceedings of the 1998 IEE Colloquium on Evolvable Hardware Systems (Digest) No. 233, 1998, pp. 2/1-2/4. |
Mintzer, L., “Xilinx FPGA as an FFT processor,” Electronic Engineering, vol. 69, No. 845, May 1997, pp. 81, 82, 84. |
Faura et al., “A Novel Mixed Signal Programmable Device With On-Chip Microprocessor,” Custom Integrated Circuits Conference, 1997. Proceedings of the IEEE 1997 Santa Clara, CA, USA, May 5, 1997, pp. 103-106. |
Nozal, L., et al., “A new vision system: programmable logic devices and digital signal processor architecture (PLD+DSP),” Proceedings IECON '91. 1991 International Conference on Industrial Electronics, Control and Instrumentation (Cat. No. 91CH2976-9) vol. 3, Oct. 28-Nov. 1, 1991, pp. 2014-2018. |
Papenfuss, J.R, et al., “Implementation of a real-time, frequency selective, RF channel simulator using a hybrid DSP-FPGA architecture,” RAWCON 2000: 2000 IEEE Radio and Wireless Conference (Cat. No. 00EX404), Sep. 10-13, 2000, pp. 135-138. |
Parhami, B., “Configurable arithmetic arrays with data-driven control,” 34th Asilomar Conference on Signals, Systems and Computers, vol. 1, 2000, pp. 89-93. |
“The QuickDSP Design Guide”, Quicklogic, Aug. 2001, revision B. |
“QuickDSP™ Family Data Sheet”, Quicklogic, Aug. 7, 2001, revision B. |
Rangasayee, K., “Complex PLDs let you produce efficient arithmetic designs,” EDN (European Edition), vol. 41, No. 13, Jun. 20, 1996, pp. 109, 110, 112, 114, 116. |
Rosado, A., et al., “A high-speed multiplier coprocessor unit based on FPGA,” Journal of Electrical Engineering, vol. 48, No. 11-12, 1997, pp. 298-302. |
Santillan-Q., G.F., et al., “Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices,” Proceedings of the Third International Workshop on Design of Mixed-Mode Integrated Circuits and Applications (Cat. No.99EX303), Jul. 26-28, 1999, pp. 147-150. |
Texas Instruments Inc., “TMS320C54x DSP Reference Set, vol. 1: CPU and Peripherals”, Literature No. SPRU131F, Apr. 1999, pp. 2-1 through 2-16 and 4-1 through 4-29. |
Tisserand, A., et al., “An on-line arithmetic based FPGA for low power custom computing,” Field Programmable Logic and Applications, 9th International Workshop, FPL'99, Proceedings (Lecture Notes in Computer Science vol. 1673), Lysaght, P., et al., eds., Aug. 30-Sep. 1, 1999, pp. 264-273. |
Tralka, C., “Symbiosis of DSP and PLD,” Elektronik, vol. 49, No. 14 , Jul. 11, 2000, pp. 84-96. |
Valls, J., et al., “A Study About FPGA-Based Digital Filters,” Signal Processing Systems, 1998, SIPS 98, 1998 IEEE Workshop, Oct. 10, 1998, pp. 192-201. |
“Virtex-II 1.5V Field-Programmable Gate Arrays”, Xilinx, Jan. 25, 2001, module 2 of 4. |
“Virtex-II 1.5V Field-Programmable Gate Arrays”, Xilinx, Apr. 2, 2001, module 1 of 4. |
“Virtex-II 1.5V Field-Programmable Gate Arrays”, Xilinx, Apr. 2, 2001, module 2 of 4. |
Walters, A.L., “A Scaleable FIR Filter Implementation Using 32-bit Floating-Point Complex Arithmetic on ,a FPGA Based Custom Computing Platform,” Allison L. Walters, Thesis Submitted to the Faculty of Virginia Polytechnic Institute and State University, Jan. 30, 1998. |
Weisstein, E.W., “Karatsuba Multiplication,” MathWorld—A Wolfram Web Resource (Dec. 9, 2007), accessed Dec. 11, 2007 at http://mathworld.wolfram.com/KaratsubaMultiplication.html. |
Wenzel, L., “Field programmable gate arrays (FPGAs) to replace digital signal processor integrated circuits,” Elektronik, vol. 49, No. 5, Mar. 7, 2000, pp. 78-86. |
“Xilinx Unveils New FPGA Architecture to Enable High-Performance, 10 Million System Gate Designs”, Xilinx, Jun. 22, 2000. |
“Xilinx Announces DSP Algorithms, Tools and Features for Virtex-II Architecture”, Xilinx, Nov. 21, 2000. |
Xilinx Inc., “Virtex-II 1.5V Field-Programmable Gate Arrays”, Advance Product Specification, DS031-2 (v1.9), Nov. 29, 2001, Module 2 of 4, pp. 1-39. |
Xilinx Inc., “Using Embedded Multipliers”, Virtex-II Platform FPGA Handbook, UG002 (v1.3), Dec. 3, 2001, pp. 251-257. |
Xilinx, Inc., “A 1D Systolic FIR,” copyright 1994-2002, downloaded from http://www.iro.umontreal.ca/˜aboulham/F6221/Xilinx%20A%201D%20systolic%20FIR.htm. |
Xilinx, Inc., “The Future of FPGA's,” White Paper, available Nov. 14, 2005 for download from http://www.xilinx.com/prs—rls,5yrwhite.htm. |
Farooqui, A., et al., “General Data-Path Organization of a MAC unit for VLSI Implementation of DSP Processors,” ISCAS '98, Part 2, May 31, 1998-Jun. 3, 1998, pp. 260-263. |
Haynes, S.D., et al., “Configurable multiplier blocks for embedding in FPGAs,” Electronics Letters, vol. 34, No. 7, pp. 638-639 (Apr. 2, 1998). |
Kim, Y., et al., “Fast GPU Implementation for the Solution of Tridiagonal Matrix Systems,” Journal of Korean Institute of Information Scientists and Engineers, vol. 32, No. 12, pp. 692-704, Dec. 2005. |