Patent Grant
7002492
The present invention relates to communicating digital signals through a communication channel. In particular, the present invention relates to a method and apparatus for encoding and decoding data in a communication channel.
In the field of digital communications, digital information is typically prepared for transmission through a channel by encoding it. The encoded data is then used to modulate a transmission to the channel. A transmission received from the channel is then demodulated and decoded to recover the original information.
Encoding the digital data serves to improve communication performance so that the transmitted signals are less corrupted by noise, fading, or other interference associated with the channel. The term “channel” can include media such as transmission lines, wireless communication and information storage devices such as magnetic, optical or magneto-optical disc drives. In the case of information storage devices, the signal is stored in the channel for a period of time before it is accessed or received. In digital magnetic recording systems, data is recorded in a magnetic layer of the storage media by a transducer. Information is written to the media by switching the direction of write current, which flows through a winding of the transducer. Each transition of the write current will result in a reversal of magnetization in the magnetic layer. In recording systems where magnetic orientation is aligned perpendicularly to the media surface, a binary digit “1” can be represented by the magnetic alignment in one direction, and a binary digit “0” can be represented by an alignment in the opposite direction. When data is to be recovered from the media, a read transducer travels over the media. Each flux reversal induces a voltage change in the read transducer.
Encoding can reduce the probability of noise being introduced into a recovered digital signal when the encoding is adapted to the known characteristics of the data and its interaction with known noise characteristics of the channel. In typical encoding arrangements, data words of m data bits are encoded into larger code words of n code bits, and the ratio m/n is known as the code rate of the encoder. Usually, the code imposes certain constraints on the code words such that the performance of data recovery from the channel is enhanced. For example, the variation of rotational speed of the motor that drives the media in digital recording systems results in non-uniform time intervals between read signal voltage pulses. Instead of using absolute time, the read back signal itself is used to generate the timing signal. A phase lock oscillator (PLO) is used to lock the phase of the timing clock to the phase of the read back voltage. As stated above, a magnetic transition will induce a read back voltage change. To ensure that the PLO is updated frequently, the code limits the run length of strings of either binary digit “0” or “1”.
In certain applications, such as in perpendicular recording within digital recording systems, it is desirable for encoded channel sequences to have a spectral null at low frequency. A data sequence of low DC content may avoid DC wandering in the digital receiver and minimize intersymbol interference due to the low frequency cutoff introduced by AC coupled preamplifiers. In other words, sequences with low DC content are desirable. Given a sequence of binary digits, if each binary digit “1” is translated into a plus one (+1) and each binary digit “0” is translated into a minus one (−1), the sequence will be DC-restricted if the running digital sum of the bipolar sequence is bounded. The running digital sum is the sum of all values (+1 and −1) in the bipolar sequence. When the variation of the running digital sum is kept to a small value, the sequence is known to have a tight bound. A tighter bound can improve the performance of the channel.
There is a need for DC-restricted codes that are amenable to practical implementations. It has been found that the mapping of binary input strings into code words having a bounded running digital sum tends to be complex. This complexity can result in considerable engineering effort being consumed to define the encoding and decoding rules and can require complex software or hardware to implement. A DC-restricted code is desired that has limited complexity and a higher code rate.
Various embodiments of the present invention address these problems, and offer other advantages over the prior art.
One embodiment of the present invention is directed to a method of encoding successive user data words into respective code words. Each data word is mapped into data segments that are constrained to a first number of bit patterns, which is less than a second number of bit patterns that satisfy a first constraint. The data segments are encoded into intermediate code word segments selected from a first set of the bit patterns that satisfy the first constraint. At least some of the bit patterns in the first set violate a second constraint. The intermediate code word segments are encoded into respective code word segments by encoding the intermediate code word segments that violate the second constraint with code word segments selected from a second, different set of the bit patterns that satisfy the first constraint and the second constraint.
Another embodiment of the present invention is directed to an encoder having a user data word input for receiving a user data word and a code word output for producing a respective code word. A mapping block maps the user data word to a plurality of data segments that are constrained to a first number of bit patterns, which is less than a second number of bit patterns that satisfy a first constraint. A first encoder encodes each data segment into an intermediate code word segment selected from a first set of the bit patterns that satisfy the first constraint. At least some of the bit patterns in the first set violate a second constraint. A second encoder encodes the intermediate code word segments into respective code word segments by encoding the intermediate code word segments that violate the second constraint into code word segments selected from a second, different set of the bit patterns that satisfy the first constraint and the second constraint.
Another embodiment of the present invention is directed to a DC-limited code in which successive m-bit unconstrained user data words are encoded into successive, corresponding n-bit code words, wherein m and n are positive integer values. The n-bit code words are constrained such that a running digital sum of segments of the n-bit code words is limited to a range from a positive value to a negative value. The positive and negative values have different absolute values.
Other features and benefits that characterize embodiments of the present invention will be apparent upon reading the following detailed description and review of the associated drawings.
Embodiments of the present invention relate to a DC-restricted code for use in encoding and decoding digital data for transmission through communication channels. The present invention can be used in any communication channel in which DC-restricted codes are useful, such as in information storage systems.
Disc drive 100 further includes a disc pack 106, which is mounted on a spindle motor (not shown), by a disc clamp 108. Disc pack 106 includes a plurality of individual discs, which are mounted for co-rotation about central axis 109. Each disc surface has an associated head, which is mounted to disc drive 100 for communication with the disc surface. In the example shown in
The heads 110 and rotating disc pack 106 define a communications channel that can receive digital data and reproduce the digital data at a later time. In one embodiment, an encoder within internal circuitry 128 receives unconstrained user data, typically from a digital computer, and then encodes the data into successive code words according to a code. The encoded data is then used to modulate a write current provided to a write transducer in the head 110. The write transducer causes the modulated code words to be encoded on a magnetic layer in disc pack 106. At a later time, a read transducer in the head 110 recovers the successive modulated code words from the magnetic layer as a serial modulated read signal. Read circuitry within internal circuitry 128 demodulates the read signal into successive parallel code words. The demodulated code words are then decoded by a decoder within circuitry 128, which recovers the original user data for use by host system 101. The read and write transducers in head 110 can be configured for longitudinal or perpendicular recording, for example.
According to one embodiment of the present invention, each (n-1)-bit word of the unconstrained user data is encoded into an n-bit code word, according to a DC-restricted code, where n is any positive integer value such as a multiple of 10. For example, if n=70, the code will have a code rate of 69/70. Other code rates can also be used in alternative embodiments of the present invention. In order to generate each 70-bit code word, the corresponding 69-bit user data word is broken down into smaller fragments. The fragments are rearranged and mapped into multiple code word segments, which are then concatenated to form the output code word. In one embodiment, the code selects the code word segments such that the running digital sum (RDS) of each code word segment is −4, −2, 0, 2, 4 or 6 only. However, other RDS ranges can also be used, such as a range in which the RDS value is the absolute value of 6 or less. As the modulated code words are read from the channel, the decoder applies the same coding rules as were used by the encoder, but in reverse order to render the original sequence of user data bits.
The RDS of a binary string can be defined as follows. Given a bit string a=a1a2 . . . an of length n, a corresponding bipolar string A=A1A2 . . . An can be obtained by replacing all “0's” in a by “−1”. The RDS of A is the algebraic sum of A1A2 . . . An. For example, if a=1001001, then A=1 −1 −1 1 −1 −1 1, and the RDS of A=−1. If a given binary string a1a2 . . . an is to be DC-limited, it is necessary for its RDS to be bounded. A bounded RDS ensures that the bit string a has a limited DC content.
The following description is divided into two sections. Section I is a general description of the design of a 69/70-rate DC-restricted code with RDS=4, −2, 0, 2, 4 or 6 at the boundaries between 14-bit segments of the code words. The description includes a process of breaking down the bits of the user data words and mapping the patterns that satisfy the RDS constraints. Section II provides a description of an implementation of an encoder and decoder. Block diagrams are included to illustrate the data flow in a hardware setting. The function of each block is described by logical equations. The block descriptions are similar to a VHDL format with input and output signals listed. However, the logical equations describing the signals are similar to a C language program. Hence, they should be applied in sequence as they are listed.
I. Procedure of Code Construction
In this embodiment, the encoder and decoder limit the RDS of code words such that the performance of data recovery in channels, such as channels with perpendicular magnetic recording media, is enhanced. The RDS-limited code can be used in a system with a Reed Solomon Error Correcting Code (ECC) having 10 bits per symbol, for example. With 10 bits per ECC symbol, the code word size “n” is chosen to be a multiple of 10. To keep the code rate as high as possible, it has been found that a rate 69/70 code can be designed to keep the DC-content of the code words to about 28%.
1. Encoder
The user data word input I68:0 is divided into a 14-bit mapping segment I13:0 (labeled 208) and five 11-bit passthrough segments I24:14, I35:25, I46:36, I57:47, and I68:58 (labeled 210). Mapping segment I13:0 is coupled to the input of mapping block 202, and passthrough segments I24:14, I35:25, I46:36, I57:47, and I68:58 are coupled to the inputs of respective segment encoder blocks 204-1 through 204-5 as the least significant 11 bits of data segments DSa through DSe, respectively. The number of passthrough segments equals the number of data segments. Bit mapping block 202 encodes each 14-bit mapping segment I13:0 into a set of five 3-bit mapped segments W2:0, W5:3, W8:6, W11:9, and W14:12 (labeled 212) according to pre-defined coding rules, which are described in more detail below. The number of mapped segments equals the number of data segments. The 3-bit mapped segments 212 are combined with respective 11-bit passthrough segments 210 to form 14-bit data segments DSa through DSe. Data segments DSa through DSe are coupled to the data inputs, D13:0, of segment encoders 24-1 through 24-5, respectively. Segment encoders 204-1 through 205-1 encode the 14-bit data segments DSa–DSe into corresponding 14-bit code word segments Y13:0, Y27:14, Y41:28, Y55:42, Y69:56, respectively, on outputs C13:0 of segment encoders 204-1 through 204-5. The 14 bit code word segments are combined to form the 70-bit code word output Y69:0.
As described in more detail below, bit mapping block 202 constrains the bit patterns formed by the 3-bit mapped segments 212 such that the number of possible bit patterns formed by data segments DSa through DSe is less than the number of bit patterns that satisfy a first constraint, such as an RDS constraint, which is enforced by segment encoders 204. Each data segment DSa–DSe has 14 bits. If the bit patterns were unconstrained by bit mapping block 202, each data segment could form one of a possible 16,384 bit patterns. However, only a subset of those bit patterns satisfy the desired RDS constraint. Bit mapping block 202 encodes mapped segments 212 such that the data segments DSa–DSe have a number of possible bit patterns that is less than the number of bit patterns that satisfy the RDS constraint. Segment encoders 204-1 through 204-5 can then encode the data segments so as to satisfy the desired RDS constraint without adding any additional bits to the code words. Any unused bit patterns (that also satisfy the RDS constraint) can then be used by segment encoders 204 to further encode the data segments so as to satisfy a second constraint, such as a “k” constraint. A “k” constraint limits the distance between transitions in the bit patterns within the code word segments to no greater than a maximum number “k”. However, any other type of “second” constraint can also be used in alternative embodiments of the present invention.
1.1 14-bit to 15-bit Mapping Block 202
In one embodiment, the 14-bit to 15-bit mapping block 202 maps a 14-bit mapping segment I13:0 of the user data word data into five groups of 3-bit patterns of mapped segments W2:0, W5:3, W8:6, W11:9, and W14:12, such that none of the 3-bit groups will be “111”. Any other bit pattern or patterns can be eliminated in alternative embodiments of the present invention. The purpose of mapping block 202 is to limit the number of bit patterns in mapped segments 212 and thus in data segments DSa–DSe such that these segments can be easily encoded in encoders 204 to satisfy desired constraints.
Assume the 14 bits of data on mapping segment I13:0 is (I13, I12, I11, I10, I9, I8, I7, I6, I5, I4, I3, I2, I1, I0) and the five groups of mapped segments on W14:0 is (W14,W13,W12) (W11,W10,W9) (W8,W7,W6) (W5,W4,W3) and (W2,W1,W0). If none of the following four groups (I11,I10,I9) (I8,I7,I6) (I5,I4,I3) (I2,I1,I0) contains “111”, mapping block 202 maps the input data bits I13:10 directly to the mapped bits W13:W0. Bit W14 is mapped to “0”. Bit W14 flags the decoder as to which type of mapping is used, direct or encoded. This mapping is shown in Table 2 below:
If one of the groups (I11,I10,I9) (I8,I7,I6) (I5,I4,I3) (I2,I1,I0) contains “111”, W14 is mapped to “1”. The remaining bits W13:W0 are encoded through the following logic:
Define
When one of the four groups contains “111”, we have one of the following four cases:
When two of the four groups contain “111”, we have one of the following six cases:
When three of the four groups contain “111”, we have one of the following four cases:
Finally, if all four groups contain “111”, we define:
If G4 is not true, i.e., (I13, I12)≠(1,1), we may encode the above mentioned cases as follows:
If G4 is true, the mapping will be as follows:
In Tables 3 and 4, the particular manner in which the bits are encoded can be altered in alternative embodiments of the present invention. The manner shown in Tables 3 and 4 are used to simplify the decoding process as the mapped 3-bit groups can be used to identify which case has occurred. For example, if the bits in group (W11, W10, W9) are “000”, Table 3 was used and the case H0 has occurred. The original bits I13:0 can then be recovered by identifying the pattern formed by W11:W9.
1.2 Segment Encoder 204
As described above, each 3-bit mapped segment 212 is combined with an unconstrained 11-bit passthrough segment 210 to form one of the five 14-bit data segments DSa–DSe. The function of each segment encoder 204 shown in
Each 3-bit mapping segment 212 is mapped to avoid the bit pattern “lil” and therefore can have one of 7 values. Each unconstrained passthrough segment 210 has 11 bits. Since 211=2048 and the 3-bit pattern represents 7 values, the 14-bit data segments represent a total of 7*2048=14,336 patterns. To simplify the encoder mapping, we choose to exclude the pattern “000” instead of the pattern “111”. Therefore, the five 3-bit mapped segments 212 are inverted before entering the segment encoders 204. In order to keep the RDS value of each code word segment C13:0 close to zero, segment encoders 204 map the 14-bit data segments into 14-bit code word segments having RDS values equal to −4, −2, 0, 2, 4 or 6 only. There are a total of 14,443 14-bit patterns that satisfy this RDS constraint. Since 14,336<14,443, it is possible to use only a subset of the 14-bit patterns that have the desired RDS values as the 14-bit code words. The remaining unused 14-bit patterns that satisfy the RDS constraint can be used to further encode the code words so as to satisfy a further constraint, such as the “k” constraint.
To avoid the cumulative RDS values being increased too fast, segment encoders 204 keep track of the RDS=6 patterns and reverse their polarity alternately. That means every other code word having RDS=6 is inverted. These inverted code words can be recovered because words with RDS=−6 are not valid code words so their identities can be restored by simple inversion.
In this example, every 69 (14+5*11) input bits are used to generate five 14-bit code words. These five 14-bit codeword segments from segment encoders 204 form a 70-bit code word. These bits are already in NRZ format and can be sent directly to the write head in embodiments in which the communication channel includes a data storage device. These bits can also be sent to an encoder of a Reed Solomon Error Correcting Code Encoder (not shown) in order to generate redundancy that can be used to correct errors during read back.
2. Decoder
Just as in the encoder, decoding of the five code word segments can be done in five cycles with a single segment decoder 406 and five 3-bit latches 422, as shown in
II. Descriptions of Encoder and Decoder
The following section provides an implementation of encoder 200 and decoder 400 according to one embodiment of the present invention. The details of the circuits and operations described below are examples only and can be performed in hardware, software, firmware and/or combinations thereof. Block diagrams are shown to illustrate the data flow in an example of a hardware setting. The function of each block is described by logical equations. The block descriptions are similar to a VHDL format with input and output signals listed. However, the logical equations describing the signals are similar to a C language program. Hence, they should be applied in sequence as they are listed.
Table 6 provides definitions for the symbols and logic operations used below to describe the functions of each block.
1. Encoder
The following subsections 1.1 and 1.2 provide implementations of 14-bit to 15-bit mapping block 202 and segment encoders 204 shown in
1.1 14-bit to 15-bit Mapping Block 202
The 14-bit to 15-bit mapping block 202 has the following inputs and outputs:
Input:
The following logical equations describe the function performed by mapping block 202 according to one embodiment of the present invention:
1.2 Segment Encoder 204
Segment encoder 204 has the following inputs and outputs:
Input:
As mentioned above, for simplicity of encoding, the 3-bit mapped segments received from mapping block 202 are inverted prior to being applied to the inputs of segment encoders 204 while the passthrough segments of the input data word are left unchanged as shown below:
Segment encoder “B” receives the successive intermediate code word segments CA13:0 and encodes those segments into code word segments CB13:0, which satisfy a second constraint. In one example, the code word segments CB13:0 are encoded so as to satisfy the “k” constraint, which limits the distance between transitions in the bit patterns to a selected value, such as 14.
Inverter block 454 performs a selective inversion for those code word segments CD13:0 that have an RDS of +6. Every other code word segment CD13:0 having RDS=+6 is inverted such that these code word segments do not cause the total RDS to increase too fast. As described in more detail with respect to
1.2.1 Segment Encoder “A” 450
Segment encoder “A” has the following inputs and outputs:
Input:
1.2.1.1 Hamming Weight Calculator 460
Hamming weight calculator 460 calculates the RDS of the incoming data segment D13:0. If the RDS is −4, −2, 0, 2, 4, or 6, the data segment already satisfies the RDS constraint and hamming weight calculator 460 sets flag output “tt” to a true value. If flag “tt” is true, multiplexer 470 routes the data segment D13:0 (through multiplexer input A13:0) directly to multiplexer output C13:0.
The following logical equations describe the function of hamming weight calculator 460:
Input:
1.2.1.2 Pattern Check Circuit 462
Pattern check circuit 462 receives the data segment D13:0 on input A13:0 and determines which of three groups, group “a”, group “b” or group “c” the pattern belongs. Also, group “a” has 6 subgroups, group “b” has 7 subgroups and group “c” has 10 subgroups. Based on the input pattern of A13:0, pattern check circuit 462 generates a corresponding group select signal ga, gb, or gc that identifies the corresponding group and generates a corresponding subgroup select word gas5:0, gbs6:0, or gcs9:0 that identifies the corresponding subgroup.
The group select signals ga, gb and gc are provided to multiplexer 470 as multiplexer select signals, which are used to select the output of the appropriate group encoder, group “a”, group “b” or group “c”.
The following logical equations describe the function of pattern check circuit 462:
Input:
1.2.1.3 Group “a” Encoder 464
Group “a” encoder 464 encodes the 14-bit data segments provided on input A13:0 into corresponding 14-bit code word segments on output cwa13:0. These code word segments have bit patterns that are selected from a subset of the bit patterns that satisfy the desired RDS constraint.
The following logical equations describe the function of group A encoder 464:
Inputs:
1.2.1.4 Group “b” Encoder 466
Group “b” encoder 466 encodes the 14-bit data segments provided on input A13:0 into corresponding 14-bit code word segments on output cwb13:0. These code word segments have bit patterns that are selected from a different subset of the bit patterns that satisfy the desired RDS constraint.
The following logical equations describe the function of group “b” encoder 466:
Input: A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0
1.2.1.5 Group “c” Encoder 468
Group “c” encoder 468 encodes the 14-bit data segments provided on input A13:0 into corresponding 14-bit code word segments on output cwc13:0. These code word segments have bit patterns that are selected from a different subset of the bit patterns that satisfy the desired RDS constraint than were used by the group “a” and “b” encoders.
The following logical equations describe the function of group “c” encoder 468:
Input:
1.2.1.6 Multiplexer 470
The following logical equations describe the function of multiplexer 470:
Input: A13:0, cwa13:0, cwb13:0, cwc13:0, tt, ga, gb, gc
Output: CW13:0
1.2.2 Segment Encoder “B” 452
Referring back to
Input:
Segment encoder “B” includes pattern check circuit 500 and HA encoder 502.
1.2.2.1 Pattern Check Circuit 500
Pattern check circuit 500 checks the pattern formed by the incoming intermediate code word segment CA13:0 and determines whether that pattern already satisfies the k-constraint. In this example, the k-constraint limits the distance between transitions to fourteen bit positions. If the incoming bit pattern already satisfies the k-constraint (and therefore is not a member of a group to be further encoded), pattern check circuit 450 sets output flag ha to “false”. If the incoming bit pattern does not satisfy the k-constraint, pattern check circuit 500 divides the input bit pattern into nine groups, for example, and determines which of the nine groups is a problem. Group select word has8:0 identifies the corresponding group.
The following logical equations describe the function performed by pattern check circuit 500.
Input:
1.2.2.2 HA Encoder 502
HA encoder 502 receives the intermediate code word segment CA13:0 on input A13:0 and further encodes the segments so as to satisfy the k-constraint, based on which group has8:0 has been identified by pattern check circuit 500. The code word segments CW13:0 are encoded with the remaining, unused 14-bit code words that satisfy the RDS constraint and also satisfy the desired k-constraint.
If flag “ha” is false, the incoming code word segment CA13:0 requires no further encoding.
The following logical equations describe the function performed by HA Encoder 502:
Input:
1.2.3 Inverter for Hamming Weight=10
Referring back to
The following logical equations describe the function performed by inverter 454:
Input:
The digital signal “st” is initialized to 0 at the beginning of a sector.
if(Hamming weight of A13:0==10)
2. Decoder 400
The following subsections provide implementations of the segment decoders 406 and 15-bit to 14-bit decoder 408 shown in
2.1 Segment Decoder 406
Each segment decoder 406 has the following inputs and outputs:
Input:
Each segment decoder 406 includes an inverter circuit 600, a segment decoder “B” 602 and a segment decoder “A” 604, which are described in the following subsections.
2.1.1 Inverter Circuit 600
Each code word segment C13:0 is applied to inverter circuit 600, which checks the bit pattern for a hamming weight of 4. A hamming weight of 4 represents a code word segment having an invalid RDS of −6. This invalid RDS represents the code word with an RDS=+6 that was selectively inverted by inverter circuit 454 in the segment encoder 204 shown in
The following logical equations define the function performed by inverter 600 according to one embodiment of the present invention:
Input:
2.1.2 Segment Decoder “B” 602
Segment decoder “B” has the following inputs and outputs:
Input:
Segment decoder “B” 602 applies the inverse of the coding rules applied by segment encoder “B” 452 shown in
2.1.2.1 Pattern Check Circuit 610
Pattern check circuit 610 checks the bit pattern of word segment DH13:0 received on input A13:0 and identifies whether that pattern corresponds to one of nine groups of patterns used by segment encoder “B”. If so, pattern check circuit 610 asserts flag “ha” and asserts the corresponding bit in has8:0.
The following logical equations describe the function performed by pattern check circuit 610.
Input:
2.1.2.2 HA Decoder 612
HA decoder 612 performs the inverse of the coding rules applied by HA encoder 502 shown in
The following logical equations describe the function performed by HA decoder 612:
Input:
2.1.3 Segment Decoder “A” 604
Referring back to
Segment decoder “A” includes the following inputs and outputs.
Input:
Segment decoder “A” includes pattern check circuit 620, group “a” decoder 622, group “b” decoder 624, group “c” decoder 626 and multiplexer 628.
2.1.3.1 Pattern Check Circuit 620
Pattern check circuit 620 receives the data segments DB13:0 from segment decoder “B” and checks its bit pattern to identify the group in which the pattern belongs. If the pattern corresponds to an original data segment that satisfied the RDS constraints without encoding, pattern check circuit 620 sets flag “tt”, and multiplexer 628 routes input A13:0 directly to multiplexer output D13:0 without decoding. If not, pattern check circuit 620 identifies whether the incoming bit pattern corresponds to group “a”, group “b” or group “c” and sets the corresponding flag, ga, gb or gc. Pattern check circuit 620 also identifies the subgroup in which the incoming pattern belongs through outputs gas5:0, gbs6:0 and gcs9:0. Group “a” has six subgroups, group “b” has seven subgroups and group “c” has ten subgroups.
The following logical equations describe the function performed by pattern check circuit 620:
Input:
2.1.3.2 Group “a” Decoder 622
Group “a” decoder 622 decodes input A13:0 according to which of the six subgroups is identified by gas5:0 to produce decoded word segment dwa13:0. The following logical equations describe the function performed by group “a” decoder 622:
Input:
2.1.3.3 Group “b” Decoder 624
Similarly, group “b” decoder 624 decodes input A13:0 according to which subgroup is identified by gbs6:0 to produce decoded word segment dwb13:0. The following logical equations define the function performed by group “b” decoder 624:
Input:
2.1.3.4 Group “c” Decoder 626
Group “c” decoder 626 decodes input A13:0 according to which subgroup is identified by gcs9:0 to produce decoded word segment dwc13:0. The following logical equations define the function performed by group “c” decoder 626:
Input:
2.1.3.5 Multiplexer 628
Multiplexer 628 routes either A13:0, dwa13:0, dwb13:0, or dwc13:0 to multiplexer output D13:0 depending on the values of select inputs tt, ga, gb and gc. The following logical equations define the function performed by multiplexer 628:
Input: A13:0, dwa13:0, dwb13:0, dwc13:0, tt, ga, gb, gc
Output: D13:0
2.2 Output Mapping from Segment Decoders 406
Referring back to
The mapped segments W2:0, W5:3, W8:6, W11:9 and W14:12 are applied to the 15-bit to 14-bit decoder 408 as W14:0.
2.3 15-bit to 14-bit Decoder 408
Decoder 408 applies the inverse of the coding rules applied by 14-bit to 15-bit mapping block 202 shown in
The following logical equations define the function performed by decoder 408 according to one embodiment of the present invention:
Input:
It is to be understood that even though numerous characteristics and advantages of various embodiments of the invention have been set forth in the foregoing description, together with details of the structure and function of various embodiments of the invention, this disclosure is illustrative only, and changes may be made in detail, especially in matters of structure and arrangement of parts within the principles of the present invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed. For example, the particular elements may vary depending on the particular application for the communication system while maintaining substantially the same functionality without departing from the scope and spirit of the present invention. In addition, it will be appreciated by those skilled in the art that the teachings of the present invention can be applied to any communication channel in which DC-limited codes are useful, such as in data storage devices, satellite communications, telecommunications, and wire-based communications without departing from the scope and spirit of the present invention. Also, a digital “word”, “block” or “segment” can have any number of bits, and the division of bits between segments and the number of segments can vary in alternative embodiments of the present invention. In addition, computing the RDS of a given data word is considered equivalent to computing the RDS of the corresponding code word when the comparison is made to the running RDS of the code word sequence. The RDS of the code word is a function of the RDS of the data word and a similar effect is achieved. The block diagrams shown in the attached figures are intended as examples only and can be modified in alternative embodiments.
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