Patent Application
20080024347
Signal 102 is sampled at an interval sufficient to preserve the integrity of the signal. The sampling rate should always exceed twice the bandwidth of the input signal. This ensures that the signal can be accurately recreated from the digital data. If the sampling rate is too slow, the digital data may show a signal with a much smaller frequency. This is known as aliasing and can be very problematic when recreating the original signal. Therefore, it is important to sample at a rate higher than twice the input bandwidth.
By sampling signal 102 at the front end, any error associated with dynamic mismatch of sampling circuits is removed, resulting in a static sampled signal which can then be fed into a plurality of ADCs 110. The timing signal from clock 106 is fed via clock distribution network 108 into each converter within ADCs 110. Each ADC converts a small segment of the sampled signal into a digital output. For example, the first ADC converts a segment of the sampled signal responding to a clock pulse. Then, the second ADC converts the next segment of the sampled signal in response to a clock pulse. This process continues until each ADC has converted a segment of the sampled signal, and then the process begins again with the first ADC.
The result is a digital output where each ADC is outputting a signal that is representative of the input signal over a specific time period of that signal. Such an output is known in the art as time-interleaved signals.
The sampled signal is then distributed to a second tier of decimating sampling circuits 210. Sampling circuits 210 are arranged in parallel such that the combination of front-end sampling circuit 204 and decimating sampling circuits 210 functions as a sample-and-hold (S/H) system. The parallel arrangement of decimating sampling circuits 210 allows for interleaving of the sampled signals prior to their conversion into digital form, permitting the system to perform the conversion operation more quickly without sacrificing resolution.
Normally the parallel arrangement of the decimating sampling circuits would be problematic as it would introduce dynamic error into the system due to the mismatch of the different sampling circuits. This dynamic error would then have to be corrected using additional digital signal processing (DSP) circuitry which adds complexity and cost to the system. However, because front-end sampling circuit 204 outputs a signal which can be regarded as static, the dynamic mismatch is effectively eliminated. Thus, the system must only compensate for any static error present in the sampling circuits. This is beneficial because static errors, non-linearities that are amplitude dependent, are relatively easy to correct using real-time or post-acquisition processing; whereas frequency-dependent dynamic errors are much more difficult and expensive to correct.
Decimating sampling circuits 210 output an interleaved sampled signal. This signal is fed into a plurality of ADCs 212 with each ADC connected to clock circuit 206 via the clock distribution network 208. ADCs 212 are arranged in groups 214 to handle all of the interleaved sampled signals from decimating sampling circuits 210. Similarly as discussed above, each ADC group 214 converts the output of one of the decimating sampling circuits 210 to an interleaved digital signal. This signal can then be converted to one or more serial digital signals.
Each ADC receives clock signal 314 from clock distribution network (shown in
Circuit components 404, 406, 408 and 410 are all synchronized with timing circuit 414. Timing circuit 414 should include a precision low-jitter clock and any necessary circuitry to distribute the signal to the components.
Whether a single-tier or a two-tier sampling design is used, a sampled signal is input into a plurality of high-resolution, low-speed (i.e., clock speed less than 100 MHz) ADCs for quantization. Each individual ADC converts a portion of the sampled signal with the plurality of ADCs outputting a quantized interleaved signal as shown in 506. The signal can then be serialized into a serial digital signal or output as interleaved digital signals as shown in 508.
Although the present invention has been described in detail with reference to certain preferred configurations thereof, other versions are possible. For example, the ADC systems described above can be constructed using any number of sampling circuits and individual ADCs as necessitated by the design. The ADC systems described above are only examples of the many different embodiments of ADC systems according to the present invention. Other modifications can be made without departing from the spirit and scope of the invention.
