Patent Grant
7119839
CMOS active pixel sensor cameras can produce a digital output.
While digital outputs are often relatively noise insensitive, the noise can couple to the analog part of the circuit and cause problems there. Different techniques of minimizing this noise are known in the art.
One way to address the noise is to use current mode transmission of voltages. The current mode transmission can be configured to operate with less noise in certain circuits. However, when current mode transmission is used, other problems can occur. One such problem is a so called ground bounce caused by surges in the power supply.
The present system teaches a new way of transmitting data from an image chip. This system can increase the signal-to-noise ratio to thereby increase the rate at which the digital data can be taken off the chip. This enables supporting higher frame rates with high special resolution.
These and other aspects will now be described in detail with the accompanying drawings, wherein:
a and 3b show the ground bounce in the CMOS I/O of
a and 7b show waveforms for the
a and 9b show waveforms of the circuit of
A disclosed active pixel sensor architecture is shown in
In the architecture shown, the data is digitized at the bottom of each pixel column. The digitized data is then serialized in the internal bus. Data is transmitted through digital output circuitry.
In this disclosed mode, the digitized data is transmitted at 100 megahertz and sent to the imager output pads. This data is then transmitted off the chip.
One bottleneck is caused by the rate at which this digital data can be taken off the imager chip. The design requirements for the I/O circuitry are often more stringent than those in the internal chip. This is because the I/O circuits must be able to drive loads that have large and often unknown parasitic components. The parasitic components can include both capacitive and inductive components. However, the combination of inductive and capacitive parasitics create second order systems that can have ringing oscillatory behavior at the high transmission frequencies.
The present inventor recognized that the output can be considered as a transmission line. Proper handling of the termination can minimize ringing and oscillatory behavior. The IC 99 shown in
Typical CMOS output circuitry, however, is often not suitable for this transmission line environment.
This system, while usable, has certain drawbacks. The output bandwidth is limited. Moreover, the transmitter must wait for the duration of the flight time before attempting another transition. Also note that the output buffer must supply a current during the entire flight time. This can increase the power consumption of the CMOS output.
b shows the voltage in the receiving IC 200. The ground level bounces to add a few hundred millivolts. This can add significant noise onto the voltage output.
Further complication is caused by the characteristic of CMOS that draws current only during the output voltage transitions. Because of the switching variation, there are large variations in current. These variations in current can cause ground bounce and can cause voltage glitches v on the line, of magnitude V=L di/dt where L is the inductance of the signal and/or ground bounce.
When several buffers switch in tandem, as often happens during digital transmission where multiple bits change state at once, the glitch energies could add. This noise in the power supply line can couple into the analog circuitry in the imager, and can corrupt the pixel outputs.
The problem is addressed by circuit of
The circuit of
The transmitting IC 400 in
The impedance can be set by adjusting the bias current through the transistors via the current source 420. Once set, the impedance becomes relatively independent of the input current through the configuration. Since the impedance is relatively constant, the reflected signal is minimized and hence transmission speed can be increased.
A more detailed schematic of the receiver circuit 410 is shown in
The circuit 410 shows a dual-ended differential input, with one part on line 503, and the other part on line 501 driving common source transistors 504, 506. Each of the current mirrors 510, 512 change the current to a conventional CMOS level. The circuit can also be used in a single ended mode, by sending only a single line of information.
The output drivers can operate in a current mode output driver mode.
The voltage VIN is again inverted by the second CMOS transistor pair 614 and input to a second follower 618. Hence, this first current design includes CMOS transistors to buffer and invert the signal as well as two differential followers arranged in a push-pull arrangement, driving a differential pair.
The second embodiment, shown in
This second embodiment has the additional advantage that is produces a CMOS compatible output voltage when connected to a CMOS IC with high gate impedance.
Although only a few embodiments have been described in detail above, other embodiments are contemplated by the inventor and are intended to be encompassed within the following claims. In addition, other modifications are contemplated and are also intended to be covered.
This application claims the benefit of the U.S. Provisional Application No. 60/093,835, filed on Jul. 22, 1998.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4441080 | Saari | Apr 1984 | A |
| 4719369 | Asano et al. | Jan 1988 | A |
| 4859880 | Chung et al. | Aug 1989 | A |
| 5050194 | Pickering et al. | Sep 1991 | A |
| 5264744 | Mizukami et al. | Nov 1993 | A |
| 5512853 | Ueno et al. | Apr 1996 | A |
| 5656952 | McCall et al. | Aug 1997 | A |
| 5739714 | Gabara | Apr 1998 | A |
| 5760601 | Frankeny | Jun 1998 | A |
| 5767699 | Bosnyak et al. | Jun 1998 | A |
| 5811984 | Long et al. | Sep 1998 | A |
| 5886659 | Pain et al. | Mar 1999 | A |
| 5898168 | Gowda et al. | Apr 1999 | A |
| 5933041 | Sessions et al. | Aug 1999 | A |
| 6075384 | Sim et al. | Jun 2000 | A |
| 6344765 | Taguchi | Feb 2002 | B1 |
| Number | Date | Country | |
|---|---|---|---|
| 60093835 | Jul 1998 | US |
