Claims
- 1. A method comprising the steps of:
(a) generating a plurality of digital code words, each of which has a most significant bits portion and a least significant bits portion; (b) generating a plurality of pulse width modulation (PWM) signals having prescribed time parameters respective thereof respectively defined in accordance with most significant bits portions of said digital code words; and (c) iteratively adjusting said prescribed time parameters of said PWM signals in accordance with least significant bits portions of said digital code words.
- 2. The method according to claim 1, wherein step (c) further comprises selectively adjusting switching times of said PWM signals.
- 3. The method according to claim 1, wherein step (c) comprises adjusting a prescribed time parameter of one PWM signal in accordance with the least significant bits portion of a digital code word used to generate another PWM signal.
- 4. The method according to claim 1, wherein step (c) comprises adjusting a prescribed time parameter of a PWM signal in accordance with the least significant bits portion of a digital code word used to generate a previously generated PWM signal.
- 5. The method according to claim 1, wherein step (a) comprises generating respective sequences of digital code words, each of which has a most significant bits portion and a least significant bits portion, step (b) comprises generating associated sequences of pulse width modulation (PWM) signals having prescribed time parameters thereof respectively defined in accordance with most significant bits portions of said respective sequences of digital code words, and step (c) comprises iteratively adjusting prescribed time parameters of PWM signals of a first of said respective sequences of PWM signals, in accordance with least significant bits portions of digital code words associated with PWM signals of a second of said respective sequences of PWM signals.
- 6. The method according to claim 5, wherein step (c) comprises iteratively adjusting prescribed time parameters of PWM signals of a given sequence of PWM signals in accordance with least significant bits portions of digital code words associated with PWM signals of a previously generated sequence of PWM signals.
- 7. The method according to claim 1, wherein step (a) comprises generating respective sequences of digital code words associated with respectively different phases of PWM signals, each of which has a most significant bits portion and a least significant bits portion, step (b) comprises generating associated sequences of pulse width modulation (PWM) signals for said respectively different phases having respective prescribed time parameters thereof respectively defined in accordance with most significant bits portions of said respective sequences of digital code words, and step (c) comprises iteratively adjusting prescribed time parameters of PWM signals of a first of said respectively different phases in accordance with least significant bits portions of digital code words associated with PWM signals of a second of said respectively different phases.
- 8. The method according to claim 1, wherein
a respective one of said PWM signals has a switching period comprised of a number D0 of system clock cycles, and a control loop command duty-cycle ηn for the nth pulse, the corrected nth pulse duty-cycle hn is defined as: 4hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ may be selected to be either 1 or the number of independent PWM signal channels (phases), the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=round(D0hn), and the nth period duty-cycle error εn is defined as: εn=Pn/D0−ηn
- 9. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D0 of system clock cycles, the initial period error δ0 of which is set to zero,
the initial duty-cycle error ε0 is set at zero, the control loop command duty-cycle is ηn for the nth pulse, the nth pulse switching cycle target value is defined as: 5Dn*=D0-∑k=1⌊nΦ⌋δn-k Φwhere Φ is the number of phases, the nth pulse corrected duty-cycle hn is defined as: 6hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ may be selected to be either 1 or the number of independent PWM signal channels (phases), the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=round(D*nhn), the final period length for the nth pulse is defined as: Dn=round(Pn/hn), the nth pulse duty-cycle error is defined as: εn=Pn/Dn−ηn, and the nth period length error δn is defined as: δn=Dn−D0.
- 10. The method according to claim 1, wherein
a respective one of said PWM signals has a switching period comprised of a number D0 of system clock cycles, and a control loop command duty-cycle ηn for the nth pulse, the corrected nth pulse duty-cycle hn is defined as: 7hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ may be selected to be either 1 or the number of independent PWM signal channels (phases), the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=floor(D0hn), and the nth period duty-cycle error εn is defined as: εn=Pn/D0−ηn
- 11. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D0 of system clock cycles, the initial period error ε0 of which is set to zero,
the initial duty-cycle error ε0 is set at zero, the control loop command duty-cycle is ηn for the nth pulse, the nth pulse switching cycle target value is defined as: 8Dn*=D0-∑k=1⌊nΦ⌋δn-k Φwhere Φ is the number of phases, the nth pulse corrected duty-cycle hn is defined as: 9hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ may be selected to be either 1 or the number of independent PWM signal channels (phases), the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=floor(D*nhn), the final period length for the nth pulse is defined as: Dn=floor(Pn/hn), the nth pulse duty-cycle error is defined as: εn=Pn/Dn−ηn, and the nth period length error δn is defined as: δn=Dn−D0.
- 12. The method according to claim 1, wherein
a respective one of said PWM signals has a switching period comprised of a number D0 of system clock cycles, and a control loop command duty-cycle ηn for the nth pulse, the corrected nth pulse duty-cycle hn is defined as: 10hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ may be selected to be either 1 or the number of independent PWM signal channels (phases), the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=ceiling(D0hn), and the nth period duty-cycle error εn is defined as: εn=Pn/D0−ηn
- 13. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D0 of system clock cycles, the initial period error ε0 of which is set to zero,
the initial duty-cycle error so is set at zero, the control loop command duty-cycle is ηn for the nth pulse, the nth pulse switching cycle target value is defined as: 11Dn*=D0-∑k=1⌊nΦ⌋δn-k Φwhere Φ is the number of phases, the nth pulse corrected duty-cycle hn is defined as: 12hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ may be selected to be either 1 or the number of independent PWM signal channels (phases), the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=ceiling(D*nhn) the final period length for the nth pulse is defined as: Dn=ceiling(Pn/hn), the nth pulse duty-cycle error is defined as: εn=Pn/Dn−ηn, and the nth period length error δn is defined as: δn=Dn−D0.
- 14. The method according to claim 1, further including the step of:
(d) controlling a DC-DC converter in accordance with said PWM signals, said DC-DC converter being coupled to receive a supply voltage, and being operative to generate a regulated DC output voltage derived from said supply voltage, said DC-DC converter including a switching circuit containing electronic power switching devices coupled between respective power supply terminals, and controllably switched in accordance with said PWM signals, and having a common node thereof coupled to an output voltage terminal providing said regulated output voltage.
- 15. The method according to claim 14, wherein step (c) further comprises selectively adjusting switching times of said PWM signals.
- 16. The method according to claim 15, wherein step (c) comprises selectively adjusting prescribed time parameters and switching times of said PWM signals as necessary to effectively maintain a variation of a prescribed time parameter within a prescribed error tolerance over plural PWM signals.
- 17. The method according to claim 15, wherein step (c) comprises selectively adjusting prescribed time parameters and switching times of said PWM signals as necessary to effectively produce a zero time average of the digital PWM quantization error of a prescribed time parameter over plural PWM signals.
- 18. The method according to claim 17, wherein step (a) comprises generating respective sequences of digital code words associated with respectively different phases of PWM signals, each of which has a most significant bits portion and a least significant bits portion, step (b) comprises generating associated sequences of pulse width modulation (PWM) signals for said respectively different phases having prescribed time parameters thereof respectively defined in accordance with most significant bits portions of said respective sequences of digital code words, and step (c) comprises adjusting prescribed time parameters of PWM signals of a respective one of said different phases in accordance with least significant bits portions of digital code words associated with previous PWM signals of said respective one of said different phases.
- 19. The method according to claim 18, further including the step of:
(d) controlling a DC-DC converter in accordance with said PWM signals, said DC-DC converter being coupled to receive a supply voltage, and being operative to generate a regulated output voltage derived from said supply voltage, said DC-DC converter including a switching circuit containing electronic power switching devices, that are coupled between respective power supply terminals, and are controllably switched in accordance with said PWM signals, and having a common node thereof coupled to an output voltage terminal providing said regulated output voltage.
- 20. The method according to claim 1, wherein
a respective one of said PWM signals has a fixed switching period comprised of a fixed number D0 of system clock cycles, and a control loop command duty-cycle ηn for the nth pulse, the corrected nth pulse duty-cycle hn is defined as: 13hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ=1, the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=round(D0hn), and the nth period duty-cycle error εn is defined as: εn=Pn/D0−ηn
- 21. The method according to claim 1, wherein
a respective one of said PWM signals has a variable switching period comprised of a variable number of system clock cycles.
- 22. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D0 of system clock cycles, the initial period error δ0 of which is set to zero,
the initial duty-cycle error ε0 is set at zero, the control loop command duty-cycle is ηn for the nth pulse, the nth pulse switching cycle target value is defined as: 14Dn*=D0-∑k=1⌊nΦ⌋δn-k Φwhere Φ is the number of phases, the nth pulse corrected duty-cycle hn is defined as: 15hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ=1, the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=round(D*nhn), the final period length for the nth pulse is defined as: Dn=round(Pn/hn), the nth pulse duty-cycle error is defined as: εn=Pn/Dn−ηn and the nth period length error δn is defined as: δn=Dn−D0.
- 23. The method according to claim 1, wherein
a respective one of said PWM signals has a fixed switching period comprised of a fixed, number D0 of system clock cycles, and a control loop command duty-cycle ηn for the nth pulse, the corrected nth pulse duty-cycle hn is defined as: 16hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ corresponds to the number of independent plural PWM signal channels (phases), the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=round(D0hn), and the nth period duty-cycle error εn is defined as: εn=Pn/D0−ηn
- 24. The method according to claim 1, wherein a respective one of said PWM signals has an initial frequency with a period equal to a number D0 of system clock cycles, the initial period error δ0 of which is set to zero,
the initial duty-cycle error ε0 is set at zero, the control loop command duty-cycle is ηn for the nth pulse, the nth pulse switching cycle target value is defined as: 17Dn*=D0-∑k=1⌊nΦ⌋δn-k Φwhere Φ is the number of phases, the nth pulse corrected duty-cycle hn is defined as: 18hn=ηn-∑k=1⌊nΓ⌋εn-k Γwhere Γ corresponds to the number of independent plural PWM signal channels (phases), the pulse width Pn, in system clock cycles, for the nth period is defined as: Pn=round(D*nhn) the final period length for the nth pulse is defined as: Dn=round(Pn/hn), the nth pulse duty-cycle error is defined as: εn=Pn/Dn−ηn, and the nth period length error δn is defined as: δn=Dn−D0.
- 25. A method according to claim 1, wherein said prescribed parameter corresponds to duty cycle.
- 26. A method of generating a regulated direct current (DC) output voltage comprising the steps of:
(a) coupling a supply voltage to a DC-DC converter that is operative to generate a regulated output voltage derived from said supply voltage, said DC-DC converter having a pulse width modulation (PWM) generator which generates a PWM switching signal that switchably controls operation of a switching circuit containing electronic power switching devices coupled between respective power supply terminals, a common node thereof being coupled to an output voltage terminal; and (b) controlling the operation of said PWM generator by
(b1) generating a plurality of digital code words, each of which has a most significant bits portion and a least significant bits portion, (b2) generating a plurality of pulse width modulation (PWM) signals having prescribed time parameters duty-cycles thereof respectively defined in accordance with most significant bits portions of said digital code words, and (b3) iteratively adjusting said prescribed time parameters of said PWM signals in accordance with least significant bits portions of said digital code words.
- 27. The method according to claim 26, wherein step (b1) comprises generating said plurality of digital code words in accordance with said supply voltage.
- 28. The method according to claim 26, wherein said prescribed parameter corresponds to duty cycle.
- 29. An apparatus for generating a regulated direct current (DC) output voltage comprising:
a DC-DC converter that is operative to generate a regulated output voltage derived from said supply voltage, said DC-DC converter including a pulse width modulation (PWM) generator which generates a PWM switching signal that switchably controls operation of a switching circuit containing electronic power switching devices coupled between respective power supply terminals, a common node thereof being coupled to an output voltage terminal; and a controller which is operative to control the operation of said PWM generator by generating a plurality of digital code words, each of which has a most significant bits portion and a least significant bits portion, generating a plurality of pulse width modulation (PWM) signals having prescribed time parameters thereof respectively defined in accordance with most significant bits portions of said digital code words, and iteratively adjusting the said prescribed time parameters of said PWM signals in accordance with least significant bits portions of said digital code words.
- 30. The apparatus according to claim 29, wherein said controller is operative to selectively adjust duty and switching cycles of said PWM signals as necessary to effectively maintain a variation of said duty-cycles within a prescribed error tolerance over plural PWM signals.
- 31. The apparatus according to claim 29, wherein said controller is operative to adjust the duty-cycle of one PWM signal in accordance with the least significant bits portion of a digital code word used to generate another PWM signal.
- 32. The apparatus according to claim 29, wherein said prescribed time parameter corresponds to duty cycle.
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present invention relates to subject matter disclosed in co-pending U.S. patent application Ser. No. 10/315,836 filed on Dec. 10, 2002, by L. Pearce et al, entitled: “Robust Fractional Clock-Based Pulse Generator for Digital Pulse Width Modulator” (hereinafter referred to as the '836 application), assigned to the assignee of the present application and the disclosure of which is incorporated herein.