The present invention relates to technical field of analog integrated circuit design and more particularly, relates to design of a COMS-TDI image sensor capable of realizing higher scanning frequency, that is, a high scanning frequency COMS-TDI image sensor.
An image sensor is able to transform optical signals acquired by a lens to electrical signals which are easy to be stored, transferred, and processed. In terms of operation manner, image sensors may be classified into area type and linear type. The working principle of area image sensor is as follows: photos of an object are taken according to pixel matrix of two dimensional area so as to obtain two dimensional image information, whereas the working principle of a linear image sensor is: photos of the object are taken according to pixel matrix of one dimension and by scanning the object to get the two dimensional image information. The working manner of a linear image sensor is demonstrated in
In early period, TDI technique is implemented by using charge coupled device (CCD) image sensor which is also an ideal device for implementing TDI technique. It can realize accumulation of signals without noise. Currently, TDI technique mostly applies to CCD image sensor. A widely used CCD-TDI image sensor has the structure similar to a rectangular area CCD image sensor and performs linear scanning. Shown as
However, as CCD image sensor has the disadvantages such as large power consumption and low integration, applications in various fields of CCD image sensor has been gradually replaced by CMOS (Complementary Metal Oxide Semiconductor) image sensor. If TDI function is able to be realized by CMOS image sensor (i.e., CMOS-TDI image sensor), cost of TDI camera will be decreased dramatically and find its wide application. In prior art, to realize TDI function using CMOS image sensor, analog signal accumulators are incorporated into the CMOS image sensor to work as a CMOS-TDI image sensor. That is, analog signals output by the pixels are in advance input into the analog signal accumulator to realize accumulation of the identically exposed signals, and the accumulated analog signals are sent to the ADC to be output quantitatively. Furthermore, prior art has also proposed to quantitatively output signals of the CMOS image sensor through the ADC at first and then, finish accumulation of identically exposed signals by a digital domain accumulator built in chip. These two kinds of techniques, either performing accumulation and then quantitative output or performing quantification and then accumulative output, are require reading out of exposure result of all pixels of the CMOS image sensor during a single exposure period. As a result, readout speed certainly will limit the shortest exposure period, i.e., the largest scanning frequency. To eliminate this problem, prior art has proposed integration of buffer cell into the pixels to realize signal delivery between adjacent pixels. Similar to CCD type TDI image sensor capable of realizing accumulation of signals in a pipelined manner, only the output of the last line of pixels during each exposure time needs to be read out quantitatively. Accordingly, limitation of the scanning frequency caused by readout speed is eliminated, thereby realizing faster scanning frequency. This technique, however, during pipelined accumulation of pixel output signal, will introduce a great deal of KT/C noise and offset voltage of the operational amplifier. In addition, fill factor of pixels is decreased due to integration of buffer cells into the pixels, hence limiting sensitivity of the sensor.
The present invention is intended to overcome drawbacks of prior art and to better realize TDI function of CMOS image sensor, improve scanning frequency of the CMOS-TDI image sensor, and extend application range of the TDI technique. To these ends, the present invention proposes a technical solution of high scanning frequency CMOS-TDI image sensor. It includes a photodiode, an operational amplifier, integration capacitors C1 and C2 of the same capacitance, an offset voltage removing capacitor C3, and plural switches S1-S10. The anode of the photodiode is connected to a zero voltage ground wire, while the cathode thereof is connected to one end of the switch S9. The other end of the switch S9 is connected to a reference voltage Vref. A left electrode plate of the offset voltage removing capacitor C3 is coupled to the cathode of the photodiode, whereas a right electrode thereof is coupled to a negative input end of the operational amplifier. The switch S10 is connected between the negative input end and an output end of the operational amplifier in series. A positive input end of the operational amplifier is coupled to the reference voltage Vref. The output end of the operational amplifier also works as the output end of entire pixels. The left electrode plate of the integration capacitor C1 is connected to one end of each switch S1 and S3. The other end of the switch S1 is connected to the reference voltage Vref, the other end of the switch S3 is connected to the cathode of the photodiode. The right electrode plate of the integration capacitor C1 is connected to one end of each switch S2 and S4. The other end of the switch S2 is connected to an input end of the pixel, and the other end of the switch S4 is connected to an output end of the pixel. The left electrode plate of the integration capacitor C2 is connected to one end of each switch S5 and S7. The other end of the switch S5 is connected to the reference voltage Vref, and the other end of the switch S7 is connected to the cathode of the photodiode. The right electrode plate of the integration capacitor C2 is connected to one end of each switch S6 and S8. The other end of the switch S6 is connected to an input end of the pixel, and the other end of the switch S8 is connected to an output end of the pixel. The cascading manner of above pixels is described as follows: an input end of pixel 1 is connected to the reference voltage Vref, an input end of pixel 2 is connected to an output end of pixel 1 and then cascading by the similar manner; an output end of the last pixel is connected to a column-parallel ADC through a readout switch Read.
The switches S1 and S2 are controlled by the clock clk1′, the switches S3 and S4 are controlled by the clock clk2, the switches S5 and S6 are controlled by the clock clk2′, the switches S7 and S8 are controlled by the clock clk1, while the switches S9 and S10 are controlled by the clock rst. When the clock Read is at high level, the pixel output is valid. The following operation of pixels is done in a pipelined manner: sample the input signal, and then add the sampled signal to photocurrent integration signal generated during an exposure period of the pixel, output the accumulation result and express the output Vint as:
Wherein V0 is signal collected during the previous exposure period of the pixel, and iph is photocurrent value of the photodiode.
The operating procedure of the pixel is described as follows:
In the initializing status, clk1=clk2=0, clk1′=clk2′=rst=1, the input and output voltage of all pixels are Vref by this time. After that, all the pixels are subject to a first exposure period, and here, clk1=clk1′=1, clk2=clk2′=rst=0, the integration capacitor C1 of each pixel begins to collect the output signal of its previous pixel and at the same time, the integration capacitor C2 begins to integrate photocurrent of the photodiode. When the first exposure period ends, the signal stored in the integration capacitor C2 of xth pixel is Vint(1,x), and the signal stored in the integration capacitor C1 thereof is Vint(1,x-1). And then, all the pixels are subject to a resetting status and here, clk1=clk1′=clk2=clk2′=0, rst=1, and the integration capacitors C1 and C2 of each pixel are in a floating status by this time and signals stored in these capacitors are kept unchanged. Resetting action is done to the photodiode. After that, all the pixels are subject to a second exposure period and here, clk1=clk1′=rst=0, clk2=clk2′=1, the integration capacitor C2 of each pixel begins to collect the output signal of its previous pixel and at the same time, the integration capacitor C1 begins to integrate photocurrent of the photodiode. When the second exposure period ends, the signal stored in the integration capacitor C1 of xth pixel is Vint(1,x-1)+Vint(2,x), and the signal stored in the integration capacitor C2 thereof is Vint(1,x-2)+Vint(2,x-1). By the similar manner, after exposure of N times, the output of the Nth pixel can be expressed as:
Vint_tot=Vint(1,1)+Vint(2,2)+Vint(3,3)+. . . +Vint(N,N) (2)
Wherein, from Vint(1,1)to Vint(N,N), each represents exposure result of the same object during a respective transit time from 1 to N by a respective pixel from 1 to N. Accordingly, the output of the Nth pixel is the result of N-leveled integration accumulation. This result is quantitatively output by a subsequent column-parallel ADC during high level period of the clock Read, thus completing the entire reading out process. During each exposure period, the output of the Nth pixel is the result of N times integration accumulation.
The layout is denoted below.
A square with a central distance P is a photosensitive region of the photodiode, and a laterally adjacent square with the same size is the location where the operational amplifier, switches and capacitor layout are disposed and it is called as circuitry region. Every two laterally adjacent square constitute a layout of a pixel. Pixels of odd column are not laterally adjacent to those of even column. The pixels of even column entirely locate below the pixels of odd column. The photosensitive region of pixels of even column is aligned with the circuitry region of the pixels of odd column. Except for the first column, photosensitive region of pixels of odd column is aligned with the circuitry region of the pixels of even column. Consequently, along a direction perpendicular to the scanning direction, that is, the length direction of the sensor array, a photosensitive region of which the fill factor is almost 100% is disposed every distance of P.
The present invention has the following features and good effects.
The pixel structure of the CMOS-TDI image sensor is able to realize transfer the output signal of previous pixels to next pixels at exposure time, and obtained the pipelined accumulation of exposure result to the same object by the pixels of the same column. In each exposure period, output of the last line pixels is required to be read out, thus decreasing limitation of the shortest exposure time caused by readout speed, and improving the largest scanning frequency of the sensor. Offset isolation technique is employed to the pixels to remove offset voltage. In addition, only one sampling operation is introduced in the course of receiving forwarded pixel output signal, thus reducing the introduced thermal noise. The layout suitable for this pixel structure may significantly improve fill factor of the pixel photosensitive region without decreasing equivalent central distance of the pixels. The instant invention may better realize TDI function, improve scanning frequency of the CMOS-TDI image sensor, and expand application range of the TDI technique.
The pixel structure employed by a COMS-TDI image sensor of the present invention is illustrated in
Wherein V0 is signal collected during the previous exposure period of the pixel, and iph is photocurrent value of the photodiode. The offset voltage removing capacitor C3 of the pixel has the ability of isolating integration capacitors C1 and C2 from the operational amplifier offset voltage. As a result, integration result output by the pixel contains no offset voltage of the operational amplifier. Moreover, only one input signal sampling operation is introduced in the course of signal accumulation by the pixel. That is, sampling thermal noise is introduced only for one time, thus reducing thermal noise level during accumulated readout.
TDI signal accumulation function is achieved by cascading these pixels. A single column of pixels after cascading N pixels is illustrated in
Vint_tot=Vint(1,1)+Vint(2,2)+Vint(3,3)+. . . +Vint(N,N) (formula 2)
Wherein, from Vint(1,1) to Vint(N,N), each represents exposure result of the same object during a respective transit time from 1 to N by a respective pixel from 1 to N. Accordingly, the output of the Nth pixel is the result of N-leveled integration accumulation. This result is quantitatively output by a subsequent column-parallel ADC during high level period of the clock Read, thus completing the entire reading out process. During each exposure period, the output of the Nth pixel is the result of N times integration accumulation. Therefore, the ADC only needs to perform readout for one time, thus reducing limitation of the scanning frequency imposed by readout speed. A readout time of microsecond level can lead to a scanning frequency of hundreds of KHz.
Operational amplifiers and capacitors are integrated into the pixel structure of the invention, and these circuits certainly reduce fill factor of the photosensitive region of the photodiode. To overcome this problem, the present invention suggests a layout as shown in
To make clear objects, technical solution and advantages of the invention, detailed description will be provided to the embodiments of the invention in connection with examples. In this embodiment, the length of the sensor is 1024 pixels, levels of the TDI are 50, scanning frequency is 100 KHz, the central distance of pixel photosensitive region is 15 μm, and a Cyclic ADC with a resolution of 10 bit and conversion rate of 100 KHz is used as a column-parallel on-chip ADC. The layout of an individual pixel is shown in
Number | Date | Country | Kind |
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201410470253.5 | Sep 2014 | CN | national |
This application claims priority from CN Application No. CN201410470253.5, filed Sep. 15, 2014 and PCT Application No. PCT/CN2014/093752, filed Dec. 12, 2014, the contents of which are incorporated herein in the entirety by reference.
Filing Document | Filing Date | Country | Kind |
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PCT/CN2014/093752 | 12/12/2014 | WO | 00 |