HIGH SIDE RESET LOGIC FOR GATE DRIVER

Abstract

A circuit in a gate driver circuit controlling a half bridge stage having high and low switches, the gate driver circuit having a high side driving circuit for driving the high switch and low side driving circuit for driving the low switch, the circuit ensuring turning OFF of the high side driving circuit and the high switch. The circuit including an input portion for receiving input signals for the high and low side driving circuits and a shutdown signals; and an output portion for providing SET and RESET signals to the high and low side driving circuits, wherein the high side driving circuit is turned OFF when the input signal for the high side driving circuit is inactive and when the input signal for the low side driving circuit becomes active.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a gate driver circuit including the reset circuit of the present invention and a half bridge stage; and

FIG. 2 is a diagram of a circuit of the present invention; and

FIG. 3 is time diagram of signals provided by the circuit of FIG. 1.

Claims

1. A circuit in a gate driver circuit controlling a half bridge stage having high and low switches, the gate driver circuit having a high side driving circuit for driving the high switch and low side driving circuit for driving the low switch, the circuit ensuring turning OFF of the high side driving circuit and the high switch, the circuit comprising: an input portion for receiving input signals for the high and low side driving circuits and a shutdown signal; andan output portion for providing SET and RESET signals to the high and low side driving circuits,wherein the high side driving circuit is turned OFF when the input signal for the high side driving circuit is inactive and when the input signal for the low side driving circuit becomes active.

2. The circuit of claim 1, wherein the RESET signal is a redundant output signal that is sent each time either the shutdown or the input signal to the low side driving circuit is enabled.

3. The circuit of claim 1, wherein the RESET signal is sent when the input signal to the high side driving circuit is disabled.

4. The circuit of claim 3, wherein sending of the SET and RESET signals is triggered by an edge of the input signal for the high side driving circuit.

5. The circuit of claim 3, wherein the RESET signal is sent every time the input signal to the low side driving circuit is enabled.

6. The circuit of claim 7, wherein sending of the RESET signal is triggered by an edge of the input signal for the low side driving circuit and the shutdown input signals.

7. The circuit of claim 1, further comprising: a first inverter circuit for receiving and inverting the input signal for the high side driving circuit, the first inverter providing the inverse of input signal for the high side driving circuit as the SET signal;second and third inverter circuits for receiving and inverting the input signal for the low side driving circuit and the shutdown input signal;a first NOR circuit for receiving the input signals for the high and low side driving circuits;a second NOR circuit for receiving the inverse of the input signals for the high and low side driving circuits from the first and second inverters,a delay circuit for receives the inverse of the input signal for the low side driving circuit from the inverter circuit;a fourth inverter circuit for receiving and inverting an output signal from the delay circuit; anda third NOR circuit for receiving outputs of the first, second, and third NOR circuits and providing an output that is the RESET signal.