High-Side Synchronous Rectifier Circuits and Control Circuits for Power Converters

Abstract

A control circuit for a switching power converter is provided. The control circuit is installed between a secondary side and an output of the power converter and coupled to control a switching device. The control circuit includes a linear predict circuit, a reset circuit, a charge/discharge circuit, and a PWM circuit. The linear predict circuit is coupled to receive a linear predict signal from the secondary side for generating a charging signal. The reset circuit is couple to receive a resetting signal for generating a discharging signal. The charge/discharge circuit is coupled to receive the charging signal and the discharging signal for generating a ramp signal. The PWM circuit is coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to power converters and more particularly, relates to the synchronous rectifier circuits of power converters.

2. Description of the Related Art

A synchronous rectifier controller in nowadays is broadly used to replace really a rectifier for decreasing power loss. A traditional synchronous rectifier controller is installed on the low-side of a secondary side of a power converter. Therefore, a ground terminal of the synchronous rectifier controller is coupled to another ground of the secondary side of the power converter. However, the drawback of the traditional synchronous rectifier controller is that there is switching loss and electric-magnetic-interference (EMI) problem because of the switching operation of the ground of the secondary side of the power converter.

BRIEF SUMMARY OF THE INVENTION

An exemplary embodiment of a control circuit for a switching power converter is provided. The control circuit is installed between a secondary side of the switching power converter and an output of the power converter and coupled to control a switching device. The control circuit comprises a linear predict circuit, a reset circuit, a charge/discharge circuit, and a pulse width modulation (PWM) circuit. The linear predict circuit is coupled to receive a linear predict signal from the secondary side for generating a charging signal. The reset circuit is couple to receive a resetting signal for generating a discharging signal. The charge/discharge circuit is coupled to receive the charging signal and the discharging signal for generating a ramp signal. The PWM circuit is coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal.

An exemplary embodiment of a synchronous rectifier circuit for a power converter is provided. The synchronous rectifier circuit comprises a power switching device, a diode, and a control circuit. The power switching device is coupled between a secondary side of the power converter and an output of the power converter for the rectifying. The diode is coupled to the power switching device in parallel. The control circuit is installed between the secondary side of the power converter and the output of the power converter. The control circuit is operated to receive a linear predict signal and a ramp signal for turning on/off the power switching device.

A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 shows an exemplary embodiment of a switching power converter;

FIGS. 2A and 2B show an exemplary embodiment of a switch controller of the switching power converter in FIG. 1;

FIG. 3 shows an exemplary embodiment of a sample-and-hold circuit of a linear predict circuit in FIGS. 2A and 2B;

FIG. 4 shows an exemplary embodiment of a voltage-to-current converter of a linear predict circuit in FIGS. 2A and 2B;

FIG. 5 shows an exemplary embodiment of a sample-and-hold circuit of a reset circuit in FIGS. 2A and 2B;

FIG. 6 shows an exemplary embodiment of the voltage-to-current converter of a reset circuit in FIGS. 2A and 2B; and

FIG. 7 shows key wave forms of a high-side synchronous rectifier circuit of the switching power converter in FIG. 1.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.

As illustrated in an embodiment of FIG. 1, a transformer T₁ is coupled between an unregulated input voltage V_IN and an output V_O of a switching power converter. As shown in FIG. 1, the transformer T₁ comprises a primary winding N_P and two secondary windings N_S1 and N_S2. A power switch Q₁ is coupled to the primary winding N_P at an input of the transformer T₁ to regulate the transfer of energy from the unregulated input voltage V_IN to the output V_O of the switching power converter. The power switch Q₁ is coupled to receive a switching signal V_G to control switching of the power switch Q₁. A resistor 25 is coupled between the power switch Q₁ and a ground of the primary side of the transformer T₁. A synchronous rectifier circuit 30 is coupled between the high-side of the secondary winding N_S1 of the transformer T₁ and the output V_O.

The synchronous rectifier circuit 30 is composed of a switching controller 100 which serves as a control circuit for the switching power converter. The switching controller 100 generates a pulse width modulation (PWM) signal V_G2 which serves as a switching signal for controlling a power transistor Q₂, wherein the power transistor Q₂ serves as a power switching device for the switching power converter. A diode 40 is connected to the power transistor Q₂ in parallel, wherein the diode 40 is a parasitic diode. The switching controller 100 includes a power terminal VDD, a linear predicting terminal LPC, a reset terminal RES, a ground terminal GND, and a control terminal GATE. The power terminal VDD is coupled to the secondary winding N_S1 to receive a rectified power source through a diode 45 and a capacitor C₆. Resistors R₁ and R₂ are coupled in series between the capacitor C₆ and a ground of a secondary side of the transformer T₁, and a linear predict signal V_LPC is generated at the joint of the resistors R₁ and R₂. Resistors R₃ and R₄ are coupled in series and coupled to the power transistor Q₂ in parallel, and a resetting signal V_RES is generated at the joint of the resistors R₃ and R₄. The linear predicting terminal LPC is coupled to receive the linear predict signal V_LPC for charging and the reset terminal RES is coupled to receive the resetting signal V_RES for resetting. The control terminal GATE is coupled to generate the PWM signal V_G2 to control the power transistor Q₂.

FIGS. 2A and 2B show an exemplary embodiment of the switch controller 100. The switching controller 100 comprises a linear predict circuit 101, a reset circuit 103, a PWM circuit 107, and a charge/discharge circuit. The linear predict circuit 101 is composed of a sample-and-hold circuit 102 and a voltage-to-current converter (V/I) 106. The reset circuit 103 is also composed of a sample-and-hold circuit 104 and a voltage-to-current converter (V/I) 105. The charge/discharge circuit comprises a capacitor C₃ and a switch SW₄. The PWM circuit 107 is composed of an SR-flip-flop 112, an inverter 113, and comparators 108 and 110.

The linear predict circuit 101 is coupled to receive the linear predict signal V_LPC for charging to the capacitor C₃ through a sampling-and-hold operation. The linear predict circuit 101 is composed of the sample and hold circuit 102 and the voltage to current converter (V/I) 106. The sample-and-hold circuit 102 of the linear predict circuit 101 is coupled to receive the linear predict signal V_LPC for sampling at a rising edge of the linear predict signal V_LPC, and then hold a sampling signal V_SL (shown in FIG. 3) at a falling edge of the linear predict signal V_LPC to generate a hold signal V_HL (shown in FIG. 3). The voltage-to-current converter (V/I) 106 is coupled to generate a charging current (also referred as a charging signal) I₃ in response the hold signal V_HL.

The reset circuit 103 is also composed of the sample-and-hold circuit 104 and the voltage-to-current converter (V/I) 105. The reset circuit 103 is coupled to receive the resetting signal V_RES to generate a discharge signal for resetting the PWM circuit 107 through the charge/discharge circuit. The sample-and-hold circuit 104 is coupled to receive the resetting signal V_RES for sampling at a rising edge of the resetting signal V_RES, and hold the sampling result (sampling signal V_SR shown in FIG. 5) at a falling edge of the resetting signal V_RES to generate a hold signal V_HR (shown in FIG. 5). The voltage-to-current converter (V/I) 105 is coupled to generate a discharging current (also referred as a discharging signal) I_DIS in response the hold signal V_HR for resetting the PWM circuit 107 through the charge/discharge circuit.

The charge/discharge circuit comprises the capacitor C₃ and the switch SW₄, which are coupled in series, for receiving the charging current I₃ and receiving the discharging current I_DIS through the switch SW₄. The capacitor C₃ is coupled to receive the charging current I₃ for charging, and the discharging current I_DIS is generated from the voltage-to-current converter (V/I) 105 through the switch SW₄ while the switch SW₄ is turned on as shown in FIG. 2B. A ramp signal V_CT is thus generated at the joint of the capacitor C₃ and the switch SW₄ in response to the charging current I₃ and the discharging current I_DIS.

The SR-flip-flop 112, the inverter 113, and the comparators 108 and 110 develop the PWM circuit 107 for generating the PWM signal V_G2 at the output terminal Q of the SR-flip-flop 112 in response to the linear predict signal V_LPC and the ramp signal V_CT. The setting terminal S of the SR-flip-flop 112 is controlled by an output of the comparator 108. The comparator 108 are coupled to receive the linear predict signal V_LPC and a first threshold V_TH1 for comparison. The resetting terminal R of the SR-flip-flop 112 is controlled by an output of the comparator 110. The comparator 110 is couple to receive the ramp signal V_CT and a second threshold V_TH2 for comparison. The comparator 108 generates an enabling signal E_N according to the comparison result. The inverter 113 is coupled to receive the enabling signal E_N and generate an inverse enabling signal ENB.

FIG. 3 shows an exemplary embodiment of the sample-and-hold circuit 102. A buffer 201, a switch 202, and a capacitor C₁ form a sample circuit, and another switch 203 and a capacitor C₂ form a hold circuit. The linear predict signal V_LPC is coupled to generate a first signal S₁ and a second signal S₂ to control the switch 202 and the switch 203 through pulse generation circuits 204 and 205, respectively. The first signal S₁ is enabled in response to the rising edge of the linear predict signal V_LPC via the pulse generation circuits 204, and the second signal S₂ is enabled in response to the falling edge of the predict signal V_LPC via the pulse generation circuits 205. The sampling signal V_SL is generated through the switch 202 at the rising edge of the linear predict signal V_LPC, and the hold signal V_HL is thus generated in the capacitor C₂ at the falling edge of the linear predict signal V_LPC. The hold signal V_HL is correlated to the high level of the linear predict signal V_LPC.

FIG. 4 shows an exemplary embodiment of the voltage-to-current converter (V/I) 106, wherein an operational amplifier 210, a transistor 211, and a resistor 212 develop a V-to-I circuit to generate a current I₂₁₂ in response to the hold signal V_HL. Transistors 213, 214, 215, 216, and 217 develop current mirrors to generate currents I₂₁₄, I₂₁₅ and I₃ in response to the current I₂₁₂. The charging current I₃ is proportional to the current I₂₁₂. The charging current I₃ is coupled to the capacitor C₃ for charging.

FIG. 5 shows an exemplary embodiment of the sample-and-hold circuit 104. A buffer 301, a switch 302, and a capacitor C₄ form a sample circuit, and another switch 303 and a capacitor C₅ form a hold circuit. The resetting signal V_RES is coupled to generate a first signal S₃ and a second signal S₄ to control switch 302 and switch 303 through pulse generation circuits 304 and 305, respectively. The first signal S₃ is enabled in response to the rising edge of the resetting signal V_RES via the pulse generation circuits 304, and the second signal S₂ is enabled in response to the falling edge of the resetting signal V_RES via the pulse generation circuits 305. The sampling signal V_SR is generated through the switch S₃ at the rising edge of the resetting signal V_RES, and the hold signal V_HR is thus generated in the capacitor C₅ at the falling edge of the resetting signal V_RES. The hold signal V_HR is correlated to the high level of the resetting signal V_RES.

FIG. 6 shows an exemplary embodiment of the voltage-to-current converter (V/I) 105, wherein an operational amplifier 310, a transistor 311, and a resistor 312 develop a V-to-I circuit to generate a current I₃₁₁ in response to the hold signal V_HR. Transistors 313 and 314 develop a current mirror to generate currents I₃₁₄ in response to the current I₃₁₁. Other transistors 315 and 316 develop another current mirror to generate the discharging current I_DIS in response to the current I₃₁₄ and the current I₂₁₄ from the voltage-to-current converter (V/I) 106, so the discharging current I_DIS can be expressed, I_DIS=I₃₁₄−I₂₁₄.

From the above description, and referring to FIG. 4 to FIG. 6. The current I₃₁₄ is mirrored form the current I₃₁₁, and the current I₃₁₁ represents the resetting signal V_RES The I₂₁₄ is mirrored form the current I₂₁₂, and the current I₂₁₂ represents the linear predict signal V_LPC. So the discharging current I_DIS represents the difference between the resetting signal V_RES and the linear predict signal V_LPC.

FIG. 7 shows the key wave forms of the high-side synchronous rectifier circuit. Referring to FIG. 2A to FIG. 6, while the switching signal V_G is enabled, the diode 45 and diode 40 are turned off (reversed biased). The voltage of the linear predict signal V_LPC is in a high level, which can be express as

$V_{\mathrm{LPC}}=\frac{V_{in}}{n}\times \frac{R_2}{R_1+R_2},$

and the PWM signal V_G2 is disabled in response to the high level of the linear predict signal V_LPC at the mean time. The power transistor Q₂ is switched off. While the switching signal V_G is disabled, the diode 45 and diode 40 are turned on (forward biased). The PWM signal V_G2 is enabled in response to the low level of the linear predict signal V_LPC The ramp signal V_CT is discharged in response to the difference between the resetting signal V_RES and the linear predict signal V_LPC. The PWM signal V_G2 is disabled once the voltage of the ramp signal V_CT is lower then the second threshold V_TH2.

In summary, the switching controller can be installed at high-side of secondary side of a switching power converter. Therefore, the ground terminal of the switching controller is no more coupled to a ground of low-side of a secondary side of a power converter but coupled to a relative low voltage of the high side winding. So the switching loss and electric-magnetic-interference (EMI) problem caused by the switching operation of the ground of the secondary side of the switching power converter can be solved.

While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

1. A control circuit for a switching power converter, the control circuit is installed between a secondary side of the switching power converter and an output of the switching power converter and coupled to control a switching device, wherein the control circuit comprises: a linear predict circuit, coupled to receive a linear predict signal from the secondary side for generating a charging signal;a reset circuit, couple to receive a resetting signal for generating a discharging signal;a charge/discharge circuit, coupled to receive the charging signal and the discharging signal for generating a ramp signal; anda pulse width modulation (PWM) circuit, coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switching signal.

2. The control circuit as claimed in claim 1, wherein the linear predict circuit comprises: a sample-and-hold circuit, coupled to receive the linear predict signal and generate a hold signal in response to the linear predict signal; anda voltage-to-current converter, coupled to receive the hold signal and generate the charging signal in response to the hold signal.

3. The control circuit as claimed in claim 1, wherein the reset circuit comprises: a sample-and-hold circuit, coupled to receive the resetting signal and generate a hold signal in response to the resetting signal; anda voltage-to-current converter, coupled to receive the hold signal and generate the discharging signal in response to the hold signal.

4. The control circuit as claimed in claim 1, wherein the charge/discharge circuit comprises: a capacitor, coupled to receive the charging signal and charged by the charging signal; anda switch, coupled to the capacitor in series and receiving the discharging signal;wherein the ramp signal is generated at a joint of the capacitor and the switch in response to the charging signal and the discharging signal.

5. The control circuit as claimed in claim 1, wherein the PWM circuit comprises: a SR-flip-flop, coupled to generate the switching signal in response to the linear predict signal and the ramp signal;a first comparator, coupled to receive the linear predict signal and a first threshold for comparison; anda second comparator, coupled to receive the ramp signal and a second threshold for comparison;wherein a setting terminal of the SR-flip-flop is controlled by an output of the first comparator and a resetting terminal of the SR-flip-flop is controlled by an output of the second comparator.

6. A synchronous rectifier circuit for a power converter comprising: a power switching device, coupled between a secondary side of the power converter and an output of the power converter for the rectifying;a diode, coupled to the power switching device in parallel; anda control circuit, installed between the secondary side of the power converter and the output of the power converter, wherein the control circuit is operated to receive a linear predict signal and a ramp signal for turning on/off the power switching device.

7. The synchronous rectifier circuit as claimed in claim 6, wherein the control circuit comprises: a linear predict circuit, coupled to receive the linear predict signal from the secondary side for generating a charging signal;a reset circuit, couple to receive a resetting signal for generating a discharging signal;a charge/discharge circuit, coupled to receive the charging signal and the discharging signal for generating the ramp signal; anda pulse width modulation (PWM) circuit, coupled to receive the linear predict signal for enabling a switching signal and receive the ramp signal for resetting the switch signal.

8. The synchronous rectifier circuit as claimed in claim 7, wherein the linear predict circuit comprises: a sample-and-hold circuit, coupled to receive the linear predict signal and generate a hold signal in response to the linear predict signal; anda voltage-to-current converter, coupled to receive the hold signal and generate the charging signal in response to the hold signal.

9. The synchronous rectifier circuit as claimed in claim 7, wherein the reset circuit comprises: a sample and hold circuit, coupled to receive the resetting signal and generate a hold signal in response to the resetting signal; anda voltage-to-current converter coupled to receive the hold signal and generate the discharging signal in response to the hold signal.

10. The synchronous rectifier circuit as claimed in claim 7, wherein the charge/discharge circuit comprises: a capacitor, coupled to receive the charging signal and charged by the charging signal; anda switch, coupled to the capacitor in series and receiving the discharging signal;wherein the ramp signal is generated at a joint of the capacitor and the switch in response to the charging signal and the discharging signal.

11. The synchronous rectifier circuit as claimed in claim 7, wherein the PWM circuit comprises: a SR-flip-flop, coupled to generate the switching signal in response to the linear predict signal and the ramp signal;a first comparator, coupled to receive the linear predict signal and a first threshold for comparison;a second comparator, coupled to receive the ramp signal and a second threshold for comparison;wherein a setting terminal of the SR-flip-flop is controlled by an output of the first comparator and a resetting terminal of the SR-flip-flop is controlled by an output of the second comparator.