High speed analog-to-digital converter using cells with back-to-back capacitors for both rough and fine approximation

Abstract

A high conversion speed analog-to-digital converter is constituted by a plurality of comparison cells which in successive steps determine first the four most significant bits of the analog-to-digital conversion and then the least significant bits of the same, having first accomplished the reconversion of the four most significant bits to analog and their subsequent subtraction from the input signal.

Description

.[.DESCRIPTION.].

.Iadd.BACKGROUND AND SUMMARY OF THE INVENTION .Iaddend.

The present invention relates to a high speed analog-to-digital converter .Iadd.and to a method for analog-to-digital conversion. .Iaddend.

Recent developments in the field of digital .[.techniques for the.]. .Iadd.signal .Iaddend.processing .[.of signals.]. have increased interest .[.for.]. .Iadd.in .Iaddend.high speed conversion.

In particular.Iadd., .Iaddend.the processing of signals in the video band creates the need of converters with a .[.band width.]. .Iadd.bandwidth of .Iaddend.10-50 Mhz and dynamic range .[.field.]. .Iadd.range .Iaddend.of 8 bits.

An integrated approach for a digitization system requires the implementation, inside the conversion device itself, of several preprocessing functions.

In .[.such sector.]. .Iadd.this art, .Iaddend.the use is known of flash (or instantaneous) converters having one or two steps. In particular.Iadd., .Iaddend.a single-step flash converter allows the use of conversion speeds of 120 Ms/sec (Megasamples per second) with bipolar technology and of 20 Ms/sec with CMOS technology. This approach does, however, have some drawbacks in terms of dissipated power, silicon area, .Iadd.and .Iaddend.high capacitative load at input.

Such drawbacks are overcome in part by using flash converters having two conversion steps. In this case the conversion operation provides for a first step of rough conversion of the sampled input signal, whereby there are obtained the four most significant bits of the signal at output, and a second step which receives at input a signal equal to the difference between the sampled input signal and the output signal of the first conversion step, reconverted to analog, and .[.operates.]. .Iadd.performs .Iaddend.a fine conversion completing the digital output signal with the four least significant bits.

The use of such two-step conversion devices unfortunately requires conversion times which are longer with respect to the use of single-step converters. It is in fact necessary to execute two successive flash conversions, .[.reconvert to analog.]. .Iadd.including reconverting .Iaddend.the result of the first conversion operation .Iadd.to analog .Iaddend.and .[.execute.]. .Iadd.executing .Iaddend.a subtraction before the second fine conversion step.

The object of the present invention is thus to accomplish an analog-to-digital converter with a very high conversion speed .[.,.]. (.Iadd.e.g. .Iaddend.around 50 Ms/sec in .[.the.]. CMOS technology).Iadd., .Iaddend.which has low input capacitance, low power dissipation.Iadd., .Iaddend.and .[.optimization.]. .Iadd.optimal use .Iaddend.of .[.the.]. silicon area .[.used.]..

According to .Iadd.an illustrated embodiment of .Iaddend.the invention.Iadd.,.Iaddend.such object is accomplished by means of a converter, characterized in that it comprises a plurality of comparison cells which in successive steps determine the four most significant bits of the conversion and then the four least significant bits after the more significant bits have been reconverted to analog and .[.their subsequent subtraction.]. .Iadd.then subtracted .Iaddend.from the input signal.

In particular.Iadd., .Iaddend.each of said comparison cells is constituted by a comparator with the input connected to an intermediate branch point between two condensers in series, .Iadd.the first .Iaddend.one of which is supplied in a first step with an input signal, in a second step with a first reference voltage different for each cell.Iadd., .Iaddend.and in a third step with a selected reference voltage equal to that of said first reference voltages which approximates said input signal .[.downwards.]. .Iadd.from below .Iaddend.with the highest accuracy, .[.and by a .]. .Iadd.with the .Iaddend.second condenser .[.which is.]. .Iadd.being .Iaddend.grounded during said first and second steps, .[.while.]. .Iadd.and connected, .Iaddend.during the third step .[.it is connected.]. .Iadd., .Iaddend.to one .[.respective.]. of a plurality of second reference voltages .Iadd.which are .Iaddend.submultiples of said first reference voltage .Iadd.(e.g. Vr'=Vr/16).Iaddend..

In this way the result is obtained that a single group of comparators accomplishes both analog-to-digital conversion operations, .Iadd.as well as .Iaddend.the operation of intermediate digital-to-analog reconversion of the output signal from the first step of analog-to-digital conversion and .[.that.]. .Iadd.the operation .Iaddend.of subtraction of .[.said signal.]. .Iadd.the .Iaddend.reconverted .[.to.]. analog .Iadd.signal .Iaddend.from the input signal, which in normal two-step flash converters are accomplished by two groups of comparators with a digital-to-analog converter and subtractor connected in between. There follow .[.favourable.]. .Iadd.favorable .Iaddend.results especially in terms of the speed of conversion, of the use of the silicon area and of power dissipation.

These and other features of the present invention shall be made evident by the following detailed description of an embodiment illustrated as an example in the enclosed .[.drawing.]. .Iadd.drawings..Iaddend.

BRIEF DESCRIPTION OF THE DRAWINGS

.[.The FIGURE.]. .Iadd.FIG. 1 .Iaddend.is a schematic diagram of the preferred embodiment of the present invention.

.Iadd.FIG. 2A shows a portion of the circuit of FIG. 1 at a first point in time, FIG. 2B shows the same circuit at a second point in time, and FIG. 2C shows the same circuit at a third point in time..Iaddend.

.Iadd.DESCRIPTION OF THE PREFERRED EMBODIMENTS.Iaddend.

.Iadd.An embodiment of the invention will now be described. It will be understood that implicit in the description of the converter is a method for analog-to-digital conversion..Iaddend.

In detail, .Iadd.as shown in FIG. 1, .Iaddend.the converter comprises a plurality of comparison cells .Iadd.CCi, .Iaddend.in particular 15 in the case comparison is required to be executed in the 8-bit range. The generic comparison cell CCi comprises a comparator Cpi, of the type with one input only and with a digital output whose value depends on the variations of the input voltage, whose input is connected to an intermediate branch point Ni between two series condensers Ci and Ci', respectively.

The condenser Ci is in turn connected, on one side, to the branch point Ni and on the other side it communicates with a parallel of three different switches S1i, S2i, S3i, respectively, which are closed in temporal succession. In particular the switch S1i connects condenser Ci to an input voltage .[.Vi.]. .Iadd.Vin, .Iaddend.the switch S2i connects the condenser Ci to a reference voltage Vri forming part of a voltage divider P constituted by a series of resistances Ri, in the specific case 16, of equal value connected between a terminal supplying a voltage Vr and ground, and switch S3i connects condenser Ci to a .[.supply.]. .Iadd.rough-approximation .Iaddend.line L1 which, by means of switch SWi, is connected to .[.that.]. .Iadd.the one voltage Vrx, .Iaddend.among the different reference voltages Vri.Iadd., .Iaddend.which is in turn selected by a coding logic LC sensitive to the outputs of comparators Cpi as that which approximates the input voltage .[.Vi.]. .Iadd.Vin .Iaddend..[.downwards.]. .Iadd.from below .Iaddend.with the highest accuracy.

Condenser Ci' is in turn connected, on one side, to the branch point Ni, and on the other side communicates with a parallel .Iadd.combination .Iaddend.of two switches, S1i', S3i', respectively, of which S1i' grounds said condenser C1 and S3i' connects said condenser Ci' to a reference voltage Vri' forming part of a voltage divider P' constituted by a series of resistances Ri', in the specific case 16, of equal value connected between a terminal supplying a voltage Vr', where Vr'=Vr/16, and ground.

The input Ii of each comparator is also connected to the respective output Ui by means of a switch SS1i.

Due to the described structure the analog-to-digital converter operates as follows.

During a first step, .Iadd.as shown in FIG. 2A, .Iaddend.switches S1i are closed and the value of the input voltage .[.Vi.]. .Iadd.Vin .Iaddend.is .[.,.]. memorized in condensers Ci. Switches SS1i also are closed to allow automatic cancellation of the offset at the terminals of comparator Cpi. During this step, condensers Ci' are grounded through switches S1i', closed simultaneously with switches S1i .Iadd.and SS1i..Iaddend.

During a second step, .Iadd.as shown in FIG. 2B, .Iaddend.switches S1i, S1i'.Iadd., .Iaddend.and SS1i are open and switches S2i are closed.Iadd., .Iaddend.so that the left-hand .[.armature.]. .Iadd.side .Iaddend.of the generic condenser Ci is brought to a respective reference voltage Vri. As a consequence.Iadd., .Iaddend.while condenser Ci still memorizes the input voltage .[.Vi.]. .Iadd.Vin .Iaddend., the voltage at the branch point Ni changes to a value .[.(Vr-Vi).]. (.Iadd.Vri-Vin) .Iaddend.which according to its .[.the.]. .Iadd.its .Iaddend.sign (+or -) .[.translates.]. .Iadd.is translated .Iaddend.to a logic level 0 or 1 on the generic output .[.Vi.]. .Iadd.Ui .Iaddend.of comparator Cpi. There is thus .[.operated.]. .Iadd.performed .Iaddend.a rough conversion of the input signal .[.obtaining.]. .Iadd.Vin to obtain .Iaddend.(.Iadd.in this example.Iaddend.) the 4 most significant bits of the digitalized signal .[.Vi.]..

During a third step .[.with.]. .Iadd., as shown in FIG. 2C, .Iaddend.switches S2i .Iadd.are .Iaddend.returned .[.in.]. .Iadd.to .Iaddend.open condition.Iadd., and .Iaddend.the coding logic LC, having detected the logic levels at the outputs of comparators Cpi, commands the closing of a selected switch SWi corresponding to the one .Iadd.reference voltage Vrx, of all the .Iaddend.reference voltage.Iadd.s .Iaddend.Vri.Iadd.,.Iaddend.which best approximates the value of the four most significant bits of the input voltage .[.Vi downwards.]. .Iadd.Vin from below, .Iaddend.thereby carrying out a reconversion of .[.said.]. .Iadd.the .Iaddend.four most significant bits into a corresponding analog signal. Switches S3i and S3i' are then closed to connect .Iadd.all of .Iaddend.the condensers Ci to the selected reference voltage (.[.Vrix.].) (.Iadd.Vrx.Iaddend.), and .Iadd.to connect the .Iaddend.condensers Ci' to respective reference voltage.Iadd.s .Iaddend.Vri'. As a consequence, the branch point Ni moves to a voltage .[.Vi-Vrix.]. .Iadd.Vin-Vrx, .Iaddend.thereby subtracting a voltage corresponding to the analog conversion of the four most significant bits of the digital output signal from the input voltage .[.Vi.]. .Iadd.Vin. .Iaddend.According to whether .[.Vin-Vrix.]. .Iadd.Vin-Vrx .Iaddend..[.;.]. is lower or higher than the reference voltage Vri', the voltage at .[.the.]. .Iadd.each .Iaddend.branch point Ni translates to a logic level 0 or 1 on the generic output Ui, thus resulting in .[.to.]. a .[."and delete and allows the operation"; and allows the operation.]. fine conversion .Iadd.operation .Iaddend.giving the 4 least significant bits of the input signal .[.Vi.]. .Iadd.Vin.Iaddend..

Claims

1. .[.High.]. .Iadd.A high .Iaddend.speed analog-to-digital converter, .[.characterized in that it comprises.]. .Iadd.comprising; .Iaddend.

a plurality of comparison cells which in successive steps determine the .[.four.]. most significant bits of the conversion and then.Iadd.,.Iaddend..[.the four least significant bits.]. after the more significant bits have been reconverted to analog and .[.their subsequent subtraction.]. .Iadd.subtracted .Iaddend.from the input signal.Iadd., the least significant bits;.Iaddend.

.[.where.]. .Iadd.wherein .Iaddend.each .[.of.]. said comparison .[.cells is constituted by.]. .Iadd.cell comprises .Iaddend.

a comparator .[.with.]. .Iadd.having an .Iaddend.input connected to an intermediate branch point between .[.two.]. .Iadd.first and second .Iaddend.condensers in series,

.[.one of which is .]. .Iadd.said first condenser being .Iaddend.supplied in a first step with an input signal,

in a second step with a first reference voltage different for each cell.Iadd., .Iaddend.and

in a third step with a selected reference voltage equal to .[.that.]. .Iadd.the one .Iaddend.of said first reference voltages which approximates said input signal .[.downward.]. .Iadd.from below .Iaddend.with the highest accuracy, .[.and by a.].

.Iadd.said second .Iaddend.condenser .[.which is.]. .Iadd.being .Iaddend.grounded during said first and second step.Iadd.s .Iaddend., .Iadd.and connected, during said .Iaddend..[.while in the.]. third step.Iadd., .Iaddend..[.it is connected.]. to .Iadd.a respective .Iaddend.one .[.respective.]. of a plurality of second reference voltages .Iadd.which are .Iaddend.submultiples of said first reference voltage.

2. .[.Converter.]. .Iadd.A converter .Iaddend.according to .[.Claim.]. .Iadd.claim .Iaddend.1, further comprising .[.a.]. decoding logic which detects the value of the outputs of said comparators during said second step.Iadd.,.Iaddend.and .Iadd.accordingly .Iaddend.determines during said third step the choice of said selected reference voltage..Iadd.3. The converter of claim 1, wherein said comparator is a single-input comparator..Iaddend..Iadd.4. The converter of claim 1, further comprising a shorting switch connected to short together an input with an output of said comparator during said first step..Iaddend..Iadd.5. The converter of claim 1, comprising 15 of said cells..Iaddend..Iadd.6. An integrated data conversion circuit, comprising:.Iaddend.

a plurality of comparison cells, each including

first and second capacitors each having a respective first terminal connected to a common node.

a thresholding logic circuit connected to provide a digital output corresonding to the analog voltage of said common node

a first initializing switch connected to selectably connect a second terminal of said first capacitor to an analog input voltage, and a second initializing switch connected to selectably connect a second terminal of said second capacitor to a constant voltage, a reference-connecting switch connected to selectably connect said second terminal of said first capacitor to a particular respective corresponding rough-approximation reference voltage, and a first fine-approximation switch connected to selectably connect said second terminal of said first capacitor to a common rough-approximation line, and a second fine-approximation switch connected to selectably connect said second terminal of said second capacitor to a particular respective corresponding fine-approximation reference voltage which is smaller in magnitude than said particular respective corresponding rough-approximation reference voltage; and

control logic connected to receive the outputs of said thresholding logic circuits, and connected to activate said initializing switches in a first phase, said reference-connecting switch in a second phase, and said fine-approximation switches in a third phase, and, during said second phase, to connect, to said rough-approximation line, one of said rough-approximation reference voltages which is selected in dependence on the outputs of said thresholding logic circuits after said first phase;

whereby the outputs of said thresholding logic circuits provide a two-stage digital output corresponding to said analog input signal..Iadd.7. The integrated circuit of claim 6, wherein said thresholding logic circuit is a single-input comparator..Iaddend..Iadd.8. The integrated circuit of claim 6, further comprising an additional respective switch between each said rough-approximation reference voltage and said rough-approximation line, and wherein said control logic is connected to activate a selected one of said additional switches during said second

phase..Iaddend..Iadd. The integrated circuit of claim 6, further comprising a first resistor ladder which supplies said rough-approximation reference voltages from multiple nodes thereof, and a second resistor ladder which supplies said fine-approximation reference voltages from multiple nodes thereof..Iaddend..Iadd.10. The integrated circuit of claim 6, comprising exactly 15 of said comparison cells..Iaddend..Iadd.11. A method for analog-to-digital data conversion, comprising:

providing a plurality of comparison cells, each including first and second capacitors each having a respective first terminal connected to a common node, and a thresholding logic circuit connected to provide a digital output dependent on the analog voltage of said common node,

during a first phase, connecting an analog input voltage to a second terminal of each said first capacitor, and connecting a second terminal of each said second capacitor to ground;

during a second phase, connecting a different respective one of a first set of reference voltages to said second terminal of each said first capacitor;

selecting a rough-approximation voltage in dependence on the outputs of said thresholding logic at the end of said second phase; and

during a third phase, connecting said rough-approximation voltage to said second terminals of all of said first capacitors, and connecting a different respective one of a second set of reference voltages to said second terminal of each said second capacitor; and

outputting bits corresponding to said outputs of said thresholding logic at the end of said second phase as more significant bits, and outputting bits corresponding to said outputs of said thresholding logic at the end of said third phase as less significant bits, to provide a digital value corresponding to said analog input value..Iaddend..Iadd.12. The method of claim 11, wherein, during said second phase, said second set of reference voltages provides four bits of additional resolution with respect to said first reference voltages..Iaddend..Iadd.13. The method of claim 11, wherein said first set of reference voltages is provided by a first resistor ladder, and said second set of reference voltages is provided by a second resistor ladder..Iaddend..Iadd.14. The method of claim 11, wherein said selecting step is performed by control logic which is connected to receive the outputs of each said thresholding logic circuit..Iaddend..Iadd.15. The method of claim 11, wherein said thresholding logic circuit is a single-input comparator..Iaddend.