High speed analog to digital converter

Abstract

An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1.

Description

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to analog to digital converters (ADC's), and more particularly, to reducing nonlinearities and inter-symbol interference in high-speed analog to digital converters.

[0004] 2. Related Art

[0005] A subranging analog to digital converter (ADC) architecture is suitable for implementing high-performance ADC's (i.e. high speed, low power, low area, high resolution). FIG. 1 shows a generic two-step subranging architecture, comprising a reference ladder 104, a coarse ADC 102, a switching matrix 103, a fine ADC 105, coarse comparators 107, fine comparators 108 and an encoder 106. In most cases, a track-and-hold 101 is used in front of the ADC. In this architecture, an input voltage is first quantized by the coarse ADC 102. The coarse ADC 102 compares the input voltage against all the reference voltages, or against a subset of the reference voltages that is uniformly distributed across the whole range of reference voltages. Based on a coarse quantization, the switching matrix 103 connects the fine ADC 105 to a subset of the reference voltages (called a “subrange”) that is centered around the input signal voltage.

[0006] Modern flash, folding and subranging analog to digital converters (ADC's) often use averaging techniques for reducing offset and noise of amplifiers used in the ADC. One aspect of averaging is the topology that is used to accomplish averaging, i.e., which amplifier outputs in which arrays of amplifiers are averaged together.

[0007] In general, flash, folding and subranging ADC's use cascades of distributed amplifiers to amplify the residue signals before they are applied to the comparators. These residue signals are obtained by subtracting different DC reference voltages from an input signal Vin. The DC reference voltages are generated by the resistive ladder (reference ladder) 104 biased at a certain DC current.

[0008] High-resolution ADC's often use auto-zero techniques, also called offset compensation techniques, to suppress amplifier offset voltages. In general, autozeroing requires two clock phases (φ1 and φ2). During the auto-zero phase, the amplifier offset is stored on one or more capacitors, and during the amplify phase, the amplifier is used for the actual signal amplification.

[0009] Two different auto-zero techniques can be distinguished, which are illustrated in FIGS. 2 and 3. The technique shown in FIG. 2 connects an amplifier 201 in a unity feedback mode during the auto-zero clock phase φ1. As a result, a large part of the amplifier 201 input offset voltage is stored on input capacitors C1a, C1b. The remaining offset is stored on output capacitors C2a, C2b if available.

[0010] The second technique, shown in FIG. 3, shorts the amplifier 201 inputs during the auto-zero phase φ1 and connects them to a DC bias voltage Vres. Here, the amplifier 201 output offset voltage is stored on the output capacitors C2a, C2b. Many ADC architectures use a cascade of several (auto-zero) amplifiers to amplify the input signal prior to applying to the comparators 107, 108. In general, flash, folding and subranging ADC's use arrays of cascaded amplifiers, and averaging and interpolation techniques are used to improve performance.

[0011] Unfortunately, the performance of cascaded arrays of amplifiers degrades significantly at high clock and input signal frequencies. The cause of this degradation is illustrated in FIG. 4 when the reset technique shown in FIG. 3 is used, and where RSW is shown as a circuit element, and the current flow IC is explicitly shown.

[0012] When the amplifier 201 is in the auto-zero phase φ1, the input capacitors C1a, C1b are charged to the voltage Vsample that is provided by the track-and-hold amplifier 101. As a result, a current IC will flow through the input capacitors C1a, C1b and an input switch (not shown). Due to the finite on-resistance RSW of the input switch (see FIG. 4), an input voltage is generated, which will settle exponentially towards zero. This input voltage is amplified by the amplifier 201 and results in an output voltage that also slowly settles towards zero (assuming the amplifier 201 has zero offset).

[0013] Essentially, the auto-zero amplifier 201 is in a “reset” mode one-half the time, and in an “amplify” mode the other one-half the time. When in reset mode, the capacitors C1a, C1b are charged to the track-and-hold 101 voltage, and the current IC flows through the capacitors C1a, C1b and the reset switches, so as to charge the capacitors C1a, C1b.

[0014] When the ADC has to run at high sampling rates, there is not enough time for the amplifier 201 output voltage to settle completely to zero during the reset phase. As a result, an error voltage is sampled at the output capacitors C2a, C2b that is dependent on the voltage Vsample. This translates into non-linearity of the ADC, and often causes inter-symbol interference (ISI).

[0015] The problem of ISI occurs in most, if not all, ADC architectures and various approaches exist for attacking the problem. The most straightforward approach is to decrease the settling time constants. However, the resulting increase in power consumption is a major disadvantage.

[0016] Another approach is to increase the time allowed for settling, by using interleaved ADC architectures. However, this increases required layout area. Furthermore, mismatches between the interleaved channels cause spurious tones. The ISI errors can also be decreased by resetting all cascaded amplifiers during the same clock phase. Unfortunately, this is not optimal for high speed operation either.

SUMMARY OF THE INVENTION

[0017] The present invention is directed to an analog to digital converter topology that substantially obviates one or more of the problems and disadvantages of the related art.

[0018] There is provided an analog to digital converter including a reference ladder, a clock having phases φ1 and φ2, and a track-and-hold amplifier tracking an input signal with its output signal during the phase φ1 and holding a sampled value during the phase φ2. A plurality of coarse amplifiers each input a corresponding tap from the reference ladder and the output sign. A plurality of fine amplifiers input corresponding taps from the reference ladder and a signal corresponding to the output signal, the taps selected based on outputs of the coarse amplifiers. A circuit responsive to the clock receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the corresponding taps to the fine amplifiers during the phase φ2 and substantially rejecting the signal corresponding to the output signal during the phase φ2. An encoder converts outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.

[0019] In another aspect of the present invention there is provided an analog to digital converter including a reference ladder and a two-phase clock having phases φ1 and φ2. A track-and-hold amplifier tracking an input signal with its output signal during the phase φ1 and holding a sampled value during the phase φ2. A plurality of coarse amplifiers each inputting a signal corresponding to the output signal and a corresponding tap from the reference ladder. A switching circuit that receives the signal corresponding to the output signal and has a differential mode transfer function of approximately 1 on the phase φ2 and approximately 0 on the phase φ1. A plurality of fine amplifiers inputting corresponding taps from the reference ladder and the signal corresponding to the output signal through the switching circuit, the taps selected based on outputs of the coarse amplifiers. An encoder converts outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.

[0020] In another aspect of the present invention there is provided an analog to digital converter including a reference ladder and a multi-phase clock. A track-and-hold amplifier tracking an input signal with its output signal during one phase of the multi-phase clock and holding a sampled value during another phase of the multi-phase clock. A plurality of coarse amplifiers each inputting a signal corresponding to the output signal and a corresponding tap from the reference ladder. Switching means that receives the signal corresponding to the output signal and responsive to the multi-phase clock, the means substantially passing the signal corresponding to the output signal to the fine amplifiers during the one phase and substantially rejecting the signal corresponding to the output signal during the another phase. A plurality of fine amplifiers inputting, through the switching means, corresponding taps from the reference ladder and the output signal, the taps selected based on outputs of the coarse amplifiers. An encoder converts outputs of the coarse and fine amplifiers to an N-bit digital signal representing the input signal.

[0021] In another aspect, an input stage includes a track-and-hold amplifier whose output signal tracks an input signal during one clock phase, and holds a sampled value during another clock phase. A coarse amplifier inputting the output signal and a coarse tap. A transfer matrix that substantially passes a signal corresponding to the output signal during the one clock phase and substantially blocks the signal corresponding to the output signal during the another clock phase. A fine amplifier inputting a fine tap and the output signal through the transfer matrix, the fine tap selected based on an output of the coarse amplifier.

[0022] In another aspect, an input stage includes a differential coarse amplifier inputting a signal corresponding to an input signal and a coarse tap during one clock phase, and a sampled value during another clock phase. A plurality of cross-coupled transistors that substantially pass the first signal and a fine tap during the one clock phase and substantially block the first signal and the fine tap during the another clock phase, the fine tap selected based on a signal from the differential coarse amplifier. A differential fine amplifier inputting an output of the plurality of cross-coupled transistors.

[0023] Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

[0024] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE FIGURES

[0025] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

[0026] FIG. 1 illustrates a conventional averaging topology.

[0027] FIGS. 2 and 3 illustrate conventional amplifier topologies with reset switches.

[0028] FIG. 4 illustrates a conventional amplifier topology and the source of the inter-symbol interference problem.

[0029] FIG. 5 illustrates a source of inter-symbol interference in greater detail.

[0030] FIG. 6 illustrates one embodiment of the present invention.

[0031] FIG. 7 illustrates another embodiment of the present invention.

[0032] FIG. 8 illustrates a reduction in inter-symbol interference using the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings.

[0034] Recently, a technique to address the nonlinearity was published by Miyazaki et al., “A 16 mW 30 M Sample/s pipelined A/D converter using a pseudo-differential architecture,” ISSCC Digest of Tech. Papers, pp. 174-175 (2002), see particularly FIG. 10.5.2 therein. The technique applies only to amplifiers that use the auto-zero technique of FIG. 2.

[0035] In Miyazaki, four extra switches and two extra capacitors are required. The resulting circuit topology has a common-mode transfer function of “1” and a differential-mode transfer function of “0” during the reset clock phase.

[0036] However, an important disadvantage of the circuit shown in Miyazaki is that it requires twice the amount of capacitance. This has a serious impact on the ADC layout area. Furthermore, the capacitive loading of the track-and-hold 101 doubles, which significantly slows down the charging of the capacitors C1a, C1b (roughly by a factor of two).

[0037] FIG. 5 shows the rationale for the present invention. In FIG. 5, the track-and-hold amplifier 101 outputs a step function to the sampling capacitors C1a, C1b. Due to the finite resistance RSW, the pulse becomes a spike (i.e., it is effectively high-pass filtered) by the time it gets to the amplifier 201, which is the first amplifier in a cascade. The next set of capacitors C2a, C2b sees a “smeared-out” pulse, which, by the time it is amplified by the next amplifier in a cascade (amplifier 202), and charges the next stage capacitors C3a and C3b, becomes further “smeared-out”. The spike being transferred throughout the cascaded amplifiers causes inter-symbol interference.

[0038] The problem of ISI can be solved in a very elegant way by complementing the reset switches shown in FIG. 3 with some additional switches before the fine amplifiers of the fine ADC 105. The resulting circuit is shown in FIG. 6. The extra switches are contained in the dashed box 510 (a transfer matrix or transfer circuit). FIG. 7 shows a modification of the new circuit that works in a similar way.

[0039] The transfer circuit shown in the dashed box 510 has a transfer function of “1” for common-mode signals at all times, so that the common mode transfer function is HCM (φ1)=1, HCM (φ2)=1. However, the transfer function varies for differential signals depending on the clock phase (φ1 or φ2). More specifically, the transfer function for differential signals is HDM(φ1)=0, and HDM (φ2)=1. Hence, a differential voltage created across nodes 1 and 2 (due to the charging of the input capacitors C1a, C1b) is not transferred to input nodes 3 and 4 of the amplifier 201 during φ1. Therefore, the output voltage of the amplifier 201 is not affected by Vsample in any way, reducing the occurrence of ISI. The input capacitors C1a, C1b subtract track-and-hold amplifier 101 voltage from a reference ladder 104 voltage.

[0040] The technique presented herein can find application in various types of ADC architectures that use auto-zero techniques for combating amplifier offsets.

[0041] FIG. 6 shows one embodiment of the present invention. φ1 and φ2 represent two phases of a clock, preferably non-overlapping phases. As shown in FIG. 6, the sampling voltage Vsample is differentially connected to two sampling capacitors C1a and C1b, which are in turn connected to three switch transistors Ma, Mb and Mc. Gates of the switch transistors Ma, Mb, Mc are connected to φ1, a drain of the transistor Ma is connected to Vres, and a source of the transistor Mc is connected to the reset voltage Vres. Between the amplifier 201 and the switch transistors Ma, Mb, Mc, the transfer matrix 510 comprises four transistors M1, M2, M3 and M4. Gates of the transistors M2 and M3 are connected to φ1. Gates of the transistors M1 and M4 are connected to Vdd, the supply voltage. Sources of the transistors M1 and M2 are tied together and to the node 1, which is also connected to the sampling capacitor C1a. Sources of the transistors M3 and M4 are tied together and also connected to a node 2, which is also connected to the sampling capacitor C1b. Drains of the transistors M3 and M1 are tied together and to node 3, which is the “+” input of the amplifier 201. Drains of the transistors M2 and M4 are tied together and to node 4, which is also connected to the “−” input of the amplifier 201.

[0042] Thus, the circuit within the dashed box 510 may be referred to as a transfer matrix that has a property such that its differential mode transfer function H(φ1)=0, H(φ2)=1. This is different from a conventional approach, where the transfer function may be thought of as being H=1 for both φ1 and φ2.

[0043] It will be appreciated that while the overall transfer function of the transfer matrix 510 is HDM (φ1)=0, HDM (φ2)=1, HCM (φ1)=1, HCM (φ2)=1, this is primarily due to the switches M1-M4, which essentially pass the differential voltage of nodes 1 and 2 through to nodes 3 and 4 respectively, on φ2. However, the gain factor need not be exactly 1, but may be some other value. The important thing is that it be substantially 0 on φ1.

[0044] FIG. 7 represents another embodiment of the present invention. The elements of FIG. 7 correspond to the same-numbered elements of FIG. 6, however, the position of the transfer matrix 510 is before the three transistors Ma, Mb and Mc, rather than after. This results in lower noise operation, compared to the embodiment shown in FIG. 6. The embodiment shown in FIG. 6, however, generally allows for higher frequency operation, compared to the embodiment of FIG. 7.

[0045] Note that either PMOS or NMOS transistors may be used as switches in the present invention. Note further that given the use of the FET transistors as switches (rather than the amplifiers), the drain and the source function equivalently.

[0046] FIG. 8 illustrates the improvement in the signal due to the transfer matrix 510. Note that the transistors Ma, Mb, Mc and the transistors of the transfer matrix M1-M4, are PMOS transistors, with the negative supply Vss used instead of the positive supply Vdd. As may be seen from FIG. 8, the amount of spike seen by the amplifier 201 after a step function outputted from the track-and-hold 101 is dramatically decreased due to the transfer function of the transfer matrix 510. φ1e in FIG. 8 refers to an “early” phase φ1 of the two-phase clock. The small spike seen in FIG. 8 is due to a mis-match of the transistors M1-M4, and disappears entirely if the transistors are made bigger. In the event there is no spike (i.e., the transistors M1-M4 are perfectly matched), an approximately 50% improvement in speed is expected.

[0047] Note further that in the event of using a plurality of cascaded amplifier stages for a pipeline architecture (designated A, B, C, D), if the A and B stage switches are driven by the phase φ1, and the C and D stages are driven by φ2, the transfer matrix 510 is only needed for the A stage and the C stage. On the other hand, if the switches of the stages A, B, C and D are driven by alternating clock phases (i.e., φ1, φ2, φ1, φ2), each stage will need its own transfer matrix 510.

[0048] It will be appreciated that the various aspects of the invention as further disclosed in related application Ser. No. 10/158,595, Filed: May 31, 2002, Titled: HIGH SPEED ANALOG TO DIGITAL CONVERTER, Inventor: Jan Mulder; application Ser. No. 10/153,709, Filed: May 24, 2002, Titled: Distributed Averaging Analog To Digital Converter Topology, Inventors: Mulder et al.; application Ser. No. 10/158,773, filed on May 31, 2002, Titled: Subranging Analog To Digital Converter With Multi-Phase Clock Timing; application Ser. No. 10/158,774, Filed: May 31, 2002; Titled: Analog To Digital Converter With Interpolation of Reference Ladder, Inventors: Mulder et al.; and application Ser. No. 10/158,193, Filed: May 31, 2002, Inventor: Jan Mulder; Titled: CLASS AB DIGITAL TO ANALOG CONVERTER/LINE DRIVER, Inventors: Jan Mulder et al., all of which are incorporated by reference herein, may be combined in various ways, or be integrated into a single integrated circuit or product.

[0049] It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. Thus, the breadth and scope of the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. An input stage comprising: a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1.

2. The input stage of claim 1, further comprising a track-and-hold amplifier tracking the input signal with its output signal during clock phase φ1 and holding a sampled value during the clock phase φ2, the first autozero amplifier in each array receiving its input signal from the track-and-hold amplifier.

3. The input stage of claim 2, further comprising a sampling capacitor at each input of the autozero amplifiers for sampling the output of the track-and-hold amplifier.

4. The input stage of claim 2, wherein the output signal of the track-and-hold amplifier includes positive and negative differential outputs, and further comprising a transistor connected between positive and negative differential outputs of the circuit, a gate of the transistor being driven by the clock phase φ1.

5. The input stage of claim 4, wherein, for each autozero amplifier, the circuit includes two cross-coupled transistors, two signal inputs and two signal outputs, the two signal outputs differentially connected to differential inputs of each corresponding autozero amplifier, the two signal inputs differentially connected to the output signal of the track-and-hold amplifier.

6. The input stage of claim 4, wherein the circuit includes first, second, third and fourth transistors, wherein sources of the first and second transistors are connected to a positive differential output of the track-and-hold amplifier through a first sampling capacitor, wherein sources of the third and fourth transistors are connected to a negative differential output of the track-and-hold amplifier through a second sampling capacitor, wherein drains of the first and third transistors are connected to a positive differential input of the each autozero amplifier, wherein drains of the second and fourth transistors are connected to a negative differential input of the each autozero amplifier, and wherein gates of the second and third transistors are driven by the clock phase φ1.

7. The input stage of claim 1, wherein, for each autozero amplifier, the circuit includes a plurality of transistors driven by either a supply voltage or the clock phase φ1.

8. The input stage of claim 1, further comprising a transistor connected between the positive and negative differential outputs of the circuit, a gate of the transistor being driven by the clock phase φ1.

9. The input stage of claim 1, further comprising a transistor connected between the positive and negative differential inputs of the circuit, a gate of the transistor being driven by the clock phase φ1.

10. The input stage of claim 9, further comprising: a first reset transistor connected between a reset voltage and the positive differential output; a second reset transistor connected between the reset voltage and the negative differential output, wherein gates of the first and second reset transistors are driven by the clock phase φ1.

11. The input stage of claim 1, wherein at least some of the autozero amplifiers comprise a plurality of amplifier stages, and wherein the circuit is coupled to an input of a first stage of such an autozero amplifier.

12. The input stage of claim 1, wherein at least some of the autozero amplifiers include a plurality of amplifier stages, and wherein the circuit is coupled to a first stage of such an autozero amplifier.

13. The input stage of claim 1, wherein each of the autozero amplifiers includes a plurality of amplifier stages, and wherein the circuit is coupled to inputs of alternating stages.

14. The input stage of claim 1, further comprising an encoder converting outputs of the autozero amplifiers to an N-bit digital signal representing the input signal

15. An input stage comprising: a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2; a plurality of amplifiers inputting reference voltages and a signal corresponding to the output signal; and a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ1.

16. The input stage of claim 15, wherein, for each amplifier, the circuit comprises a plurality of transistors driven by either a supply voltage or the clock phase φ1.

17. The input stage of claim 16, wherein the transistors are FET transistors.

18. The input stage of claim 15, wherein, for each amplifier, the circuit comprises two cross-coupled transistors, two signal inputs and two signal outputs, the two signal outputs differentially connected to differential inputs of each corresponding amplifier, the two signal inputs differentially connected to the output signal of the track-and-hold amplifier.

19. The input stage of claim 15, wherein the output signal comprises positive and negative differential outputs of the track-and-hold amplifier, wherein the circuit includes first, second, third and fourth transistors, wherein sources of the first and second transistors are connected to a positive differential output of the track-and-hold amplifier through a first sampling capacitor, wherein sources of the third and fourth transistors are connected to a negative differential output of the track-and-hold amplifier through a second sampling capacitor, wherein drains of the first and third transistors are connected to a positive differential input of the each amplifier, wherein drains of the second and fourth transistors are connected to a negative differential input of the each amplifier, and wherein gates of the second and third transistors are driven by the clock phase φ1.

20. The input stage of claim 19, further comprising an encoder converting outputs of the amplifiers to an N-bit digital signal representing the input signal.

21. The input stage of claim 15, wherein the output signal includes positive and negative differential outputs of the track-and-hold amplifier, and further comprising a transistor connected between the positive and negative differential outputs of the track and hold amplifier, a gate of the transistor being driven by the clock phase φ1.

22. The input stage of claim 21, further comprising: a first reset transistor connected between a reset voltage and the positive differential output; and a second reset transistor connected between the reset voltage and the negative differential output, wherein gates of the first and second reset transistors are driven by the clock phase φ1.

23. The input stage of claim 21, further including sampling capacitors at the positive and negative differential outputs of the track-and-hold amplifier.

24. The input stage of claim 15, wherein a transfer function of the circuit for differential mode is HDM(φ1)=0, HDM(φ2)=1, and a transfer function for common mode is HCM(φ1)=1, HCM(φ2)=1.

25. The input stage of claim 15, wherein each of the amplifiers comprises a plurality of amplifier stages, and wherein the circuit is coupled to an input of a first stage for each amplifier.

26. The input stage of claim 1, wherein each of the amplifiers comprises a plurality of amplifier stages, and wherein the circuit is coupled to inputs of each stage.

27. The input stage of claim 15, further comprising a sampling capacitor at each input of the amplifiers for sampling the output of the track-and-hold amplifier.

28. An analog to digital converter comprising: a track-and-hold amplifier tracking an input signal with its output signal during a clock phase φ1 and holding a sampled value during a clock phase φ2; a first plurality of amplifiers each inputting a signal corresponding to the output signal and a reference voltage; a switching circuit that receives the signal corresponding to the output signal and has a differential mode transfer function of approximately 1 on the clock phase φ2 and approximately 0 on the clock phase φ1; and a second plurality of amplifiers inputting the reference voltages and the signal corresponding to the output signal through the switching circuit, the reference voltages selected based on outputs of the first plurality of amplifiers.

29. An input stage comprising: a multi-phase clock; a track-and-hold amplifier tracking an input signal with its output signal during one phase of the multi-phase clock and holding a sampled value during another phase of the multi-phase clock; a first plurality of amplifiers each inputting a signal corresponding to the output signal and a reference voltage; switching means that receives the signal corresponding to the output signal and responsive to the multi-phase clock, the means substantially passing the signal corresponding to the output signal to a second plurality of amplifiers during the one phase and substantially rejecting the signal corresponding to the output signal during the another phase; and the second plurality of amplifiers inputting, through the switching means, the reference voltages and the output signal, the reference voltages selected based on outputs of the first plurality of amplifiers.

30. An input stage comprising: a plurality of amplifiers each sampling an input signal at an end of a clock phase φ1 and each inputting a voltage reference at an end of a clock phase φ2; a plurality of fine amplifiers inputting reference voltages and a signal corresponding to the sampled input signal; and a circuit responsive to the clock that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase φ2 and substantially rejecting the signal corresponding to the output signal during the clock phase φ2.