The present disclosure relates to the field of integrated circuit technologies, and in particular, to a high-speed and high-precision analog-to-digital converter and an analog-to-digital converter performance improvement method.
An analog-to-digital converter is an electronic component that converts an analog signal into a digital signal. Quality of signal collection and conversion depends on a speed and precision of the analog-to-digital converter. With development of information technology, a requirement for signal collection and conversion is increasingly high, and a high-speed and high-precision analog-to-digital converter is a hotspot required by an integrated system.
One or more embodiments of the present disclosure provide a high-speed and high-precision analog-to-digital converter technical solution, to resolve problems of a decrease in a signal-to-noise ratio and reduction of linearity that are caused by a process deviation and an insufficient component intrinsic gain, and a problem of a decrease in the signal-to-noise ratio that is caused by dither injection.
To achieve the foregoing objective and other related objectives, the present disclosure provides the following technical solutions.
A high-speed and high-precision analog-to-digital converter is provided, and includes an input configuration module, an analog-to-digital conversion module, an adaptive parameter extraction module, and a full-period data restoration module.
The adaptive parameter extraction module sends a configuration control signal to the input configuration module, and the input configuration module configures and generates an analog signal, quantization control signals, and an output mode control signal under the control of the configuration control signal.
The analog-to-digital conversion module receives the analog signal, the quantization control signals, and the output mode control signal, performs analog-to-digital conversion on the analog signal to obtain digital signals, and under the control of the quantization control signals and the output mode control signal, rearranges the digital signals when the high-speed and high-precision analog-to-digital converter is in a parameter extraction working mode to obtain rearranged digital signals, and calibrates the digital signals based on correction parameters when the high-speed and high-precision analog-to-digital converter is in a normal working mode to obtain corrected digital signals.
The adaptive parameter extraction module sends output data mode information to the full-period data restoration module, and the full-period data restoration module receives the output data mode information and the rearranged digital signals, and restores the rearranged digital signals to full-period data based on the output data mode information, to obtain and output full-period rearranged digital signals.
The adaptive parameter extraction module receives the full-period rearranged digital signals, extracts the correction parameters from the full-period rearranged digital signals by using an adaptive parameter extraction method, and then sends the correction parameters to a parameter memory inside the analog-to-digital converter for storage.
The correction parameters include at least a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter.
In an embodiment, the analog-to-digital conversion module includes a first operation circuit, n stages of quantization circuits cascaded in sequence, n random number generation circuits, and n analog random signal generation circuits, the n random number generation circuits are connected to the n analog random signal generation circuits in a one-to-one correspondence, the random number generation circuit generates a random digital signal, and the analog random signal generation circuit performs digital-to-analog conversion on the random digital signal to obtain a random analog signal; a first input terminal of the first operation circuit is connected to the analog signal, a second input terminal of the first operation circuit is connected to a first random analog signal, an output terminal of the first operation circuit is connected to an analog input terminal of a first stage of quantization circuit, and the first operation circuit performs an additive operation on the analog signal and the first random analog signal; a feedback adjustment input terminal of the first stage of quantization circuit is connected to a second random analog signal, a control input terminal of the first stage of quantization circuit is connected to a first quantization control signal, an analog output terminal of the first stage of quantization circuit is connected to an analog input terminal of a second stage of quantization circuit, and a digital output terminal of the first stage of quantization circuit outputs a first stage of digital signal; a feedback adjustment input terminal of an ith stage of quantization circuit is connected to an (i+1)th random analog signal, a control input terminal of the ith stage of quantization circuit is connected to an ith quantization control signal, an analog output terminal of the ith stage of quantization circuit is connected to an analog input terminal of an (i+1)th stage of quantization circuit, and a digital output terminal of the ith stage of quantization circuit outputs an ith stage of digital signal; a digital output terminal of an nth stage of quantization circuit outputs an nth stage of digital signal; and n is an integer greater than or equal to 2, and i is an integer of 2 to n−1.
In an embodiment, a jth stage of quantization circuit includes an analog-to-digital sub-converter and a multiplication digital-to-analog converter, an analog input terminal of the analog-to-digital sub-converter serves as an analog input terminal of the jth stage of quantization circuit, the analog-to-digital sub-converter is connected to an analog input signal and performs analog-to-digital conversion on the analog input signal to obtain a digital output signal, and a digital output terminal of the analog-to-digital sub-converter serves as a digital output terminal of the jth stage of quantization circuit; the multiplication digital-to-analog converter includes a digital-to-analog sub-converter, a second operation circuit, and an amplifier, the digital-to-analog sub-converter is connected to the digital output signal and performs digital-to-analog conversion on the digital output signal to obtain an analog output signal, a first input terminal of the second operation circuit is connected to the analog input terminal of the analog-to-digital sub-converter, a second input terminal of the second operation circuit is connected to the analog output signal, a third input terminal of the second operation circuit serves as a feedback adjustment input terminal of the jth stage of quantization circuit, the third input terminal of the second operation circuit is connected to the random analog signal, an output terminal of the second operation circuit is connected to an input terminal of the amplifier, and the second operation circuit performs an operation of “the analog input signal−the analog output signal+the random analog signal”; an output terminal of the amplifier serves as an analog output terminal of the jth stage of quantization circuit; and j is an integer of 1 to n−1.
In an embodiment, the nth stage of quantization circuit includes an analog-to-digital sub-converter, an analog input terminal of the analog-to-digital sub-converter serves as an analog input terminal of the nth stage of quantization circuit, the analog-to-digital sub-converter is connected to an analog input signal and performs analog-to-digital conversion on the analog input signal to obtain a digital output signal, and a digital output terminal of the analog-to-digital sub-converter serves as a digital output terminal of the nth stage of quantization circuit.
In an embodiment, the analog-to-digital conversion module further includes a data alignment unit, and the data alignment unit receives n random digital signals and n stages of digital signals, and performs alignment processing on a random digital signal and a digital signal of each stage of quantization circuit.
In an embodiment, the analog-to-digital conversion module further includes a data rearrangement unit, and the data rearrangement unit is connected to the output mode control signal and the aligned n random digital signals and n stages of digital signals, rearranges, under the control of the output mode control signal when the high-speed and high-precision analog-to-digital converter is in the parameter extraction working mode, the n random digital signals and the n stages of digital signals that are obtained after one-time sampling and alignment, to obtain the rearranged digital signals, and outputs the rearranged digital signals in batches.
In an embodiment, the analog-to-digital conversion module further includes a digital calibration unit, the digital calibration unit is separately connected to the data alignment unit and the parameter memory, and when the high-speed and high-precision analog-to-digital converter is in the normal working mode, the digital calibration unit calibrates and corrects, based on the correction parameters stored in the parameter memory, the n random digital signals and the n stages of digital signals that are obtained after one-time sampling and alignment, to obtain the corrected digital signals.
In an embodiment, the analog-to-digital conversion module further includes an output interface unit, and the output interface unit is separately connected to the data rearrangement unit, the digital calibration unit, and the full-period data restoration module; when the high-speed and high-precision analog-to-digital converter is in the parameter extraction working mode, the output interface unit receives the rearranged digital signals and sends the rearranged digital signals to the full-period data restoration module in batches; and when the high-speed and high-precision analog-to-digital converter is in the normal working mode, the output interface unit receives the corrected digital signals and outputs the corrected digital signals.
In an embodiment, the parameter memory includes:
In an embodiment, the dither correction parameter includes an actual weight of each random analog signal, the gain correction parameter includes an actual gain of each stage of quantization circuit, and the mismatch error correction parameter includes an actual weight of the digital-to-analog sub-converter in each stage of quantization circuit.
An analog-to-digital converter performance improvement method is provided, and includes:
The correction parameters include at least a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter.
In an embodiment, extracting correction parameters of each stage of quantization circuit in the analog-to-digital converter through cooperation of the input configuration module, the data rearrangement unit, the full-period data restoration module, and the adaptive parameter extraction module includes:
The inventors find, through research, that, with high-speed and high-precision development of an analog-to-digital converter, progress of a manufacturing process leads to a decrease in a signal-to-noise ratio and reduction of linearity of the analog-to-digital converter while bringing about an increase in a speed, and there are shortcomings in at least the following aspects:
Therefore, currently, a technical solution of a high-speed and high-precision analog-to-digital converter is required, to resolve problems of a decrease in a signal-to-noise ratio and reduction of linearity of the analog-to-digital converter that are caused by a process deviation and an insufficient component intrinsic gain, and a problem of a decrease in the signal-to-noise ratio that is caused by dither injection.
Based on this, the present disclosure provides a high-speed and high-precision analog-to-digital converter technical solution: A dither generation structure is added to an analog-to-digital converter, to generate a plurality of random analog signals by using the dither generation structure, and inject dithers into the analog-to-digital converter, thereby improving linearity of the analog-to-digital converter. A correction parameter extraction structure is added to the analog-to-digital converter, to extract correction parameters of each stage of quantization circuit in the analog-to-digital converter by using the correction parameter extraction structure. The correction parameters include at least a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter. A parameter memory is added to the analog-to-digital converter, and the parameter memory combines one-time storage and solidification storage to improve storage efficiency. A digital calibration unit is added to the analog-to-digital converter, and the digital calibration unit calibrates and corrects, with reference to the correction parameters, digital signals obtained through analog-to-digital conversion of the analog-to-digital converter, to implement digital calibration, thereby preventing performance of the analog-to-digital converter from being affected by an increasingly small intrinsic gain and an increasingly large mismatch error that are caused by reduction of a process size, and completely eliminating injected random dithers.
The following describes implementations of the present disclosure by using specific examples. A person skilled in the art can easily understand other advantages and effects of the present disclosure based on the content disclosed in this specification. The present disclosure may be further implemented or applied by using other different specific implementations. Various details in this specification may also be modified or altered based on different viewpoints and applications without departing from the present disclosure.
Refer to
As shown in
The adaptive parameter extraction module 13 sends a configuration control signal Cv to the input configuration module 11. The input configuration module 11 configures and generates an analog signal Vin, quantization control signals Ctl1 to Ctl(n−1), and an output mode control signal Ct1 under the control of the configuration control signal Cv.
The analog-to-digital conversion module 12 receives the analog signal Vin, the quantization control signals Ctl1 to Ctl(n−1), and the output mode control signal Ct1, performs analog-to-digital conversion on the analog signal Vin to obtain digital signals D1 to Dn, and under the control of the quantization control signals Ctl1 to Ctl(n−1) and the output mode control signal Ct1, rearranges the digital signals D1 to Dn when the high-speed and high-precision analog-to-digital converter is in a parameter extraction working mode to obtain rearranged digital signals, and calibrates the digital signals based on correction parameters when the high-speed and high-precision analog-to-digital converter is in a normal working mode to obtain corrected digital signals.
The adaptive parameter extraction module 13 sends output data mode information to the full-period data restoration module 14, and the full-period data restoration module 14 receives the output data mode information and the rearranged digital signals, and restores the rearranged digital signals to full-period data based on the output data mode information, to obtain and output full-period rearranged digital signals.
The adaptive parameter extraction module 13 receives the full-period rearranged digital signals, extracts the correction parameters from the full-period rearranged digital signals by using an adaptive parameter extraction method, and then sends the correction parameters to a parameter memory 8 inside the analog-to-digital converter 12 for storage.
The correction parameters include at least a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter.
In detail, as shown in
In more detail, as shown in
The kth stage of random number generation circuit 3k is configured to generate the random integral random digital signal Ditherk, where the signal may be generated or not generated according to a system requirement. The kth stage of analog random signal generation circuit 4k is configured to convert the input random digital signal Ditherk into the corresponding analog random signal ditherk for output, where the signal may be generated or not generated according to a system requirement.
In more detail, as shown in
Bit of the analog-to-digital sub-converter 201 is the same as the bit of the digital-to-analog sub-converter 2021, for example, both kj-bit, kj-bit analog-to-digital sub-converter 201 and kj-bit digital-to-analog sub-converter 2021. The digital output signal Dj generated has kj bits, Dj1, Dj2, Dj3, . . . , and Dj2kj. A gain of the amplifier 2023 is usually Gj=2kj−1, and may be adjusted under the control of Ctlj.
In more detail, as shown in
A quantity of bits of the analog-to-digital sub-converter 203 may be set as required. This is not limited herein. For example, a quantity of bits of the analog-to-digital sub-converter 203 is kn, the digital output signal Dn generated by the kn-bits analog-to-digital sub-converter 203 has kn bits, Dn1, Dn2, Dn3, . . . , and Dn2kn.
It should be noted that when the high-speed and high-precision analog-to-digital converter is in the parameter extraction working mode, for correction parameter extraction of an mth stage of quantization circuit 2m, an amplitude of an analog output signal of an (m−1)th stage of quantization circuit 2(m−1) is increased (for example, by two times) through control and adjustment of the quantization control signals Ctl1 to Ctl(m−1), so that expected application ranges are traversed for correction parameter extraction of the mth stage of quantization circuit 2m, where m is an integer of 2 to n. The input configuration module 11 configures a required input signal amplitude for correction parameter extraction of the first stage of quantization circuit 21. Details are not described herein.
As shown in
In details, in an optional embodiment of the present disclosure, as shown in
In more details, step S11 of configuring the input signal and the output mode includes: configuring an amplitude of the input signal of each stage and a threshold voltage of comparators at each stage, and configuring an output interface to send all output results of the comparators at each stage.
The analog-to-digital converter includes n conversion stages; when a gain correction parameter and a mismatch error correction parameter of the ith conversion stage are extracted, a maximum value of the input signal of the ith stage is greater than the maximum comparator threshold of the ith conversion stage, and a minimum value of the input signal of the ith stage is smaller than the minimum comparator threshold of the ith conversion stage, for example, an input signal that is 1 dB less than a full amplitude is usually input; when i≥2, a threshold voltage of comparators at a pre-stage is configured so that the signal amplitude always does not exceed a comparator threshold thereof, and the input signal reaches the approximately full amplitude when the input signal is transmitted to the ith stage, wherein n is an integer greater than or equal to 2, and i is an integer of 1−n.
In more details, in the step S12, output data are collected, and the amount of the collected data is usually several thousands of data points. The data amount may be increased or decreased according to the precision of the analog-to-digital converter, which is not limited herein.
As shown in
Specifically, in an optional embodiment of the present disclosure, as shown in
In more details, in the step S131, the actual output sequence of the analog-to-digital converter is obtained based on the output codes of the comparators at each stage:
In more detail, in the step S132, a fitting output sequence {circumflex over (D)}out(m) is obtained as an ideal output sequence under a constraint of a minimum mean square error based on a characteristic of the input signal and the actual output sequence.
In more detail, in the step S133, an error sequence is obtained according to the actual output sequence and the ideal output sequence:
In more detail, in the step S134, the actual inter-stage gain (namely, the gain correction parameter) and the actual weight (namely, the mismatch error correction parameter) of each quantization unit are calculated based on the error sequence, and the calculation formulas for the gain correction parameter and the mismatch error correction parameter are respectively as follows:
The above iteration takes a form of a variable step size, and both of the iteration step sizes μigk and μiwk are selected in a descending order, so as to increase a convergence speed thereof.
In detail, in the step S02, the first correction is performed on the analog-to-digital converter according to the gain correction parameters and the mismatch error correction parameters, and a calculation formula for performing the first correction on the analog-to-digital converter is as follows:
In detail, the step S03 of extracting the dither correction parameters of all the conversion stages of the analog-to-digital converter after the first correction further includes:
In more detail, in the step S31, the input signal and the output mode are configured based on a quantity of errors that need to be extracted, and when the dither correction parameters (namely, jitter weights) are extracted, the threshold voltages of the comparators at all stages are restored to a normal working state, and no special requirement is imposed on the input signal. When the dither correction parameters are extracted, the input signal is set to a predetermined threshold (a signal with a small amplitude) or the input signal is disabled, so as to increase a convergence speed thereof.
In more detail, in the step S32, the jitter digital codes of all stages are opened, and only the jitter digital codes (namely, jitter signals) of one stage are opened and extracted each time. In other words, the jitter digital codes of one stage are successively opened and extracted, and the order of opening and extracting the jitter digital codes of all stages is not limited.
In more detail, in the step S33, the dither correction parameters of all the conversion stages are calculated according to the jitter digital codes and the second test output data. A corresponding calculation formula is as follows:
After completion, the jitter signals of the current stage are disabled.
In detail, as shown in
In more detail, as shown in
In more detail, as shown in
The data rearrangement unit 6 is used only in the parameter extraction working mode. Because a quantity of output data ports required in the normal working mode is less than a volume of data that needs to be sent out in the parameter extraction mode, to ensure that output data Ditherk and Dk that need to be used for parameter extraction are output as required, data obtained through one-time sampling needs to be rearranged, and then sent out from an output interface unit 9 in batches. All quantized intermediate parameters may be sent out as required in a manner of combining data rearrangement with multiple-time output without changing an output interface, thereby resolving a problem that a conventional analog-to-digital converter cannot send out all quantized intermediate parameters.
In more detail, as shown in
In more detail, as shown in
In more detail, as shown in
The parameter memory 8 can flexibly implement one-time storage in a test phase in a manner of combining one-time storage with solidification storage, and performing solidification storage after a test is completed effectively improves storage efficiency.
It should be noted that, when the high-speed and high-precision analog-to-digital converter is in the parameter extraction working mode, the correction parameters of each stage of quantization circuit are extracted stage by stage, to obtain a plurality of correction parameters of each stage of quantization circuit.
In more detail, the adaptive parameter extraction module 13 extracts the correction parameters from the full-period rearranged digital signals by using an adaptive parameter extraction method, where the correction parameters include at least a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter. The dither correction parameter includes at least actual weights of the random analog signals dither0 to dither(n-1), the gain correction parameter includes at least actual gains G1_real to Gn-1_real of the stages of quantization circuits, and the mismatch error correction parameter includes at least actual weights W1_real to Wn_real of the digital-to-analog sub-converters of the stages of quantization circuits.
In more detail, when the high-speed and high-precision analog-to-digital converter is in the parameter extraction working mode, the input configuration module 11, the data rearrangement unit 6 and the output interface unit 9 in the analog-to-digital conversion module 12, the adaptive parameter extraction module 13, and the full-period data restoration module 14 are combined into a correction parameter extraction structure, and the correction parameter extraction structure extracts the correction parameters of each stage of quantization circuit in the analog-to-digital conversion module 12. When the high-speed and high-precision analog-to-digital converter is in the normal working mode, the digital calibration unit 7 and the parameter memory 8 in the analog-to-digital conversion module 12 are combined into a correction structure, and the correction structure calibrates and corrects the digital signals obtained through analog-to-digital conversion of the analog-to-digital converter, to implement digital calibration. In addition, a dither signal may be or may not be added to each stage of quantization circuit of the analog-to-digital conversion module 12, to selectively improve linearity of the analog-to-digital conversion module 12.
The adaptive parameter extraction module 13 uses the adaptive parameter extraction method, which requires a small quantity of samples, thereby greatly reducing a computational amount of parameter extraction. Intermediate parameter output is combined with the adaptive parameter extraction method, to implement extraction of a plurality of correction parameters of a plurality of stages of the analog-to-digital converter, to resolve a problem that the conventional analog-to-digital converter cannot extract the plurality of correction parameters of the plurality of stages. Linearity of the analog-to-digital converter is improved by injecting dithers, and the extracted correction parameters include the dither correction parameter, so that the injected dithers can be precisely eliminated through dither correction in the digital calibration unit 7, thereby preventing imprecise dither elimination from decreasing a signal-to-noise ratio of the system. The digital calibration unit 7 uses a digital calibration manner that has higher error calibration precision compared with an analog calibration manner.
Based on an overall structural design of “the input configuration module+the analog-to-digital conversion module+the adaptive parameter extraction module+the full-period data restoration module”, when the high-speed and high-precision analog-to-digital converter is in the parameter extraction working mode, the correction parameters can be extracted through cooperation of the input configuration module, the analog-to-digital conversion module, the adaptive parameter extraction module, and the full-period data restoration module; and when the high-speed and high-precision analog-to-digital converter is in the normal working mode, digital calibration and correction of the digital signals obtained after digital-to-analog conversion are implemented by using the analog-to-digital conversion module and the correction parameters. The correction parameters include at least a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter. Therefore, a signal-to-noise ratio of the analog-to-digital converter is effectively increased and linearity of the analog-to-digital converter is effectively improved, performance of the analog-to-digital converter is prevented from being affected by an increasingly small intrinsic gain and an increasingly large mismatch error that are caused by reduction of a process size, injected random dithers are completely eliminated, and the signal-to-noise ratio of the analog-to-digital converter is prevented from being affected by the injected random dithers. In addition, the adaptive parameter extraction module extracts the correction parameters by using the adaptive parameter extraction method, which requires a small quantity of samples, thereby greatly reducing a computational amount of parameter extraction. A calibration manner is digital calibration that has higher error calibration precision compared with an analog calibration manner while resolving problems of a decrease in the signal-to-noise ratio and reduction of linearity of the analog-to-digital converter that are caused by a process deviation and an insufficient component intrinsic gain.
In addition, based on the foregoing design concept of the high-speed and high-precision analog-to-digital converter, the present disclosure further provides an analog-to-digital converter performance improvement method. As shown in
The correction parameters include at least a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter.
In detail, in S1, the random number generation circuit and the analog random signal generation circuit form a dither generation structure, and the dither generation structure generates the plurality of random analog signals to inject the dithers into the analog-to-digital converter, thereby effectively improving linearity of the analog-to-digital converter. The dither generation structure may selectively inject dither signals (that is, the random analog signals) into some or all quantization stages in the analog-to-digital converter. This is not limited herein.
In detail, as shown in
The adaptive parameter extraction module extracts the correction parameters by using the adaptive parameter extraction method, which requires a small quantity of samples, thereby greatly reducing a computational amount of parameter extraction. S2 shows only a correction parameter extraction process for one stage of quantization circuit in the analog-to-digital converter. In the present disclosure, the correction parameters of each stage of quantization circuit in the analog-to-digital converter need to be separately extracted stage by stage. Details are not described herein.
In detail, in S3, the parameter memory is added to the analog-to-digital converter, and the parameter memory combines one-time storage and solidification storage. Solidification storage can be performed only after the correction parameters of each stage of quantization circuit in the analog-to-digital converter pass a verification test, thereby effectively improving storage efficiency.
In detail, in S4, the digital calibration unit is added to the analog-to-digital converter. In the digital calibration unit, the digital signals obtained through analog-to-digital conversion of the analog-to-digital converter are calibrated and corrected based on the correction parameters stored in the parameter memory to obtain the corrected digital signals for implementing digital calibration. The correction parameters include at least a dither correction parameter, a gain correction parameter, and a mismatch error correction parameter. Therefore, a signal-to-noise ratio of the analog-to-digital converter is effectively increased and linearity of the analog-to-digital converter is effectively improved, performance of the analog-to-digital converter is prevented from being affected by an increasingly small intrinsic gain and an increasingly large mismatch error that are caused by reduction of a process size, injected random dithers are completely eliminated, and the signal-to-noise ratio of the analog-to-digital converter is prevented from being affected by the injected random dithers. A calibration manner is digital calibration that has higher error calibration precision compared with an analog calibration manner while resolving problems of a decrease in the signal-to-noise ratio and reduction of linearity of the analog-to-digital converter that are caused by a process deviation and an insufficient component intrinsic gain.
The foregoing embodiments merely illustrate principles and effects of the present disclosure, but are not intended to limit the present disclosure. Any person skilled in the art may modify or alter the foregoing embodiments without departing from the scope of the present disclosure. Therefore, all equivalent modifications or alterations completed by a person of ordinary skill in the art should still be covered by the claims of the present disclosure.
Number | Date | Country | Kind |
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202211735360.7 | Dec 2022 | CN | national |
202211739280.9 | Dec 2022 | CN | national |
PCT/CN2023/074200 | Feb 2023 | WO | international |
PCT/CN2023/096787 | May 2023 | WO | international |
The present application is a continuation application of PCT Application No. PCT/CN2023/074200 filed on Feb. 2, 2023, and a continuation application of PCT Application No. PCT/CN2023/096787, filed on May 29, 2023; PCT/CN2023/074200 claiming the benefit of priority to a Chinese Patent Application number CN202211739280.9, filed on Dec. 31, 2022, and PCT/CN2023/096787 claiming the benefit of priority to a Chinese Patent Application number CN 202211735360.7, filed on Dec. 31, 2022, each disclosure of the above applications is hereby incorporated by reference in its entirety for all purposes.
Number | Date | Country | |
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Parent | PCT/CN2023/074200 | Feb 2023 | WO |
Child | 19026465 | US | |
Parent | PCT/CN2023/096787 | May 2023 | WO |
Child | 19026465 | US |